EEN-611 Lecture 2-4

Verilog
EEN-611 FPGA Implementation of Signal Processing

Monday, August 12, 2019 2
Systems, Department of Electrical Engg., IIT Roorkee
HDL Tool Suites
1. Text editor – allows you to write , edit and save an HDL program
2. Compiler – responsible for parsing the HDL program, finding syntax errors,
and figuring out what the program says.
3. A Synthesizer – targets the design to a specific hardware technology such
as a PLD, CPLD, FPGA or ASIC
4. Simulator- the inputs to the simulator are the HDL program and a timed
sequence of inputs for the hardware it describes.
5. Test bench – The input sequence can be contained in another HDL
program, which is written in same language
6. Waveform editor - or it can be described graphically using another tool
The simulator runs the specified input sequence on the described

hardware and determines the values of the hardware’s internal signals and
its outputs over a specified over a period time.
The output of the simulator can include waveforms to be viewed using the
waveform editor, text files which lists signal values over simulated time,
error and warning messages that highlight unusual conditions.
HDL integrated Tool Suite:
1. Template generator – creates a text file with the outline of a commonly
used program structure, so the designer “can fill the blanks” to create a
source code.
input output declarations, logic structures like decoders, adder, and
registers and test benches.
2. Schematic viewer – may create a schematic diagram corresponding to a
HDL program based on the intermediate-language output of the compiler.
3. Translator- targets the compiler’s intermediate-language output to a real
device such as PLD, FPGA or ASIC.
4. Fitter –which fits the translated realization into the available resources on
the real device.
5. Chip viewer-lets the designer see how the design has been laid out on the
chip.
6. Timing analyzer – calculates the delays through some or all of the signal
paths in the final chip and produces a report showing the worst case paths
and their delays
7. Back annotator inserts delay clauses or statements in the original HDL
source program, corresponding to the delays calculated by the timing
analyzer.
HDL Based Design Flow
Front end begins with figuring out the basic approach and building blocks at
the block-diagram level.
Large logic designs, like software programs, are hierarchical and VHDL and
Verilog give a framework for defining modules and their interfaces
Writing HDL codes for modules, their interfaces and their internal details.
HDL compiler checks for syntax error and compatibility with other modules.
EEN-611 FPGA Implementation of Signal
Monday, August 12, 2019 Processing Systems, Department of Electrical 5
Engg., IIT Roorkee
Simulation allows to apply inputs to your design
Its just on piece of a larger step called verification
Verification – functional verification, timing verification

Functional verification- study the circuit logical operation independent of
timing considerations; gate delays and other timing parameters are
considered to be zero.
Timing verification-study the circuit’s operation including estimated
delays, and verify that the setup, hold and other timing requirements for
sequential devices are met.
Back-end stage
Synthesis- converting the HDL description into a set of primitives or
components that can be assembled in the target technology.
Fitting – maps the synthesized primitives or components into available
device resources.
Post fitting timing verification- In this stage the actual circuit delays due
to wire lengths, electrical loading, and other factors can be calculated
with reasonable precision.

Features:
Design may be decomposed hierarchically

Each design element has both a well-defined interface and a precise
functional specification
Functional specifications can use either a behavioral algorithm or an
actual hardware structure to define an elements operation.
Concurrency , timing, clocking can all be modeled. VHDL handles
asynchronous and synchronous sequential structures.
The logic operation and timing behavior of a design can be simulated.

Module is a text file containing declarations and statements

Module is a text file containing declarations and statements.
Declarations describe the names and types of the module’s inputs and
outputs, local signals, constants, variables and functions. These are strictly
used inside the module and are not visible outside.
Statements specify the operation of the module’s output and internal
signals.
Modelling:
1. Behavioural
2. Structural
3. Data Flow

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Verilog modules can instantiate other modules.
Higher level module may use lower level module multiple times.
Top-level modules may use the same lower level one.

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Comments
Single line comments begin with double slashes and end at the end of the
line //.
Multi-line long comments begin anywhere with /* and end anywhere with
*/.
Reserved words or Keywords:
module, input, output, assign and endmodule.

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Identifiers:
User identifier begin with letter or underscore and can contain letters,
digits, underscore (_), and dollar sign($).
Identifiers are
VrInhibit, X, Y, and Z.
Verilog is case sensitive for both keywords (lower case only) and
identifiers.
Identifiers XY, xy, Xy, xY are different.

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1. Keyword
2. Identifier
3. List of identifiers
4. Declarations
5. keyword
Input, output ports are signals through which module communicates with
other modules.

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Each port that is named in input/output list must have input, output, or
inout declarations.
The keyword input, output, inout is followed by comma separated list of

identifiers for signals or ports of corresponding type.

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The keyword specifies the signal direction as follows.
input The signal is an input to the module
output The signal is an output of the module.
reg declaration is needed to read inside other modules.
inout The signal can be used as a module input or output.
The signal can be multi-bit or vector.

It can be declared by range specification [msb:lsb]
A range can be ascending or descending.

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Logic system
Verilog uses four valued logic system. 1-bit signal can take on one of only four
possible values.

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Verilog actually has two classes of signals
1. nets
2. Variables
A net corresponds to roughly a wire in a physical circuit. This provides

connectivity
between the modules and other elements in a structural module.
Input/output port lists are often nets.
The default net type is wire : any signal name that appears in input/output
port list but not in a net declaration which is assumed to be a wire.
It provides basic connectivity.

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Verilog variables store values during program execution, they need
to have physical significance in a circuit.
Variables are
1. reg
2. Integer
reg may be a single bit or vector of bits.
Variable values can be changed within the procedural code within a
module, it can not be changed from outside the module.
Therefore input inout ports cannot have variable type, they must
have a net type as wire.
Output ports can have either a net or a reg type. It can drive input
and inout ports of the other modules.

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Bit select: byte1[7] , Zbus[16]
Part select : Zbus[2:5]
Literals:
n’ B ddd…d
n is a decimal number size of the literal in bits. No of bits

B is a single letter specifying the base may be b(binary),
o(octal),h(hexadecimal), d (decimal and the default)
ddd…d is the string of one or more digits in the specified base.

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Concatenation: { }
{2’ b00, 2’ b01} = 4’ b0001
{byte1, byte1, byte2, byte3} = 32 bit vector
Replication operator : n { }
{2{byte1}, 2{byte2}}

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Padding: vectors are aligned with rightmost bit, left
bits are appended with zeros.
The value of 2’ b11 & 4’ b 0101 is 4’ b0001

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Shift operators:
8’ b11010011<<3 is 8’ b10011000

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1’ b1 is true
1’ b0 is false
4’ b0100 is true
4’ b1111 is also true
But 4’ b0000 is false
4’ b0100 && 4’ b1011 is true && true

But bitwise will be 4’ b0000 –false
Logical operations are preferred in

conditional operations.

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Structural Design elements

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4-1 Multiplexer - Structural Verilog Description
module multiplexer_4_to_1_st_v(S, I, Y);
input [1:0] S; // S is a vector with components S[1] and S[0]
input [3:0] I; // I is a 4-bit input; vectors: I[0]…I[3]
output Y;
wire [1:0] not_S; // connecting NOT-AND

wire [0:3] D, N; // D connecting AND-AND
not // N  AND outputs
gn0(not_S[0], S[0]), // gn0(output, input)
gn1(not_S[1], S[1]);
and S[0] not_S[0]
g0(D[0], not_S[1], not_S[0]),
g1(D[1], not_S[1], S[0]), D0
g2(D[2], S[1], not_S[0]), g0 N[0]
g4
g3(D[3], S[1], S[0]),
g4(N[0], D[0], I[0]),
g5(N[1], D[1], I[1]),
g6(N[2], D[2], I[2]),
g7(N[3], D[3], I[3]);
or go(Y, N[0], N[1], N[2], N[3]); EEN-611 FPGA Implementation of Signal
endmodule Engg., IIT Roorkee
2-to-4 Line Decoder Structural Verilog
// 2-to-4 Line Decoder: Structural Verilog Description.
module decoder_2_to_4_st_v(EN, A0, A1, D0, D1, D2, D3);
input EN, A0, A1;
output D0, D1, D2, D3;
wire A0_n, A1_n, N0, N1, N2, N3;

not
go(A0_n, A0), A1_n
g1(A1_n, A1); A0_n
and N0
g3
g3(N0, A0_n, A1_n),
N1
g4(N1, A0, A1_n),
g5(N2, A0_n, A1),
g6(N3, A0, A1),
g7(D0, N0, EN), g6 N3
g8(D1, N1, EN),
g9(D2, N2, EN),
g10(D3, N3, EN);
endmodule
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Dataflow Verilog Modeling
1. A dataflow description is based on function rather than

structure.
2. A dataflow uses a number of operators that act on operands
to produce the desired function  Boolean equations are used
in place of logic schematics.

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A continuous assignment is the most basic
statement in data flow modeling, used to drive a
value onto a net. A continuous assignment
replaces gates in the description of the circuit
and describes the circuit at a higher level of
abstraction.
A continuous assignment statement starts with
the keyword assign.

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// Verilog code for AND-OR-INVERT gate
module AOI (input A, B, C, D, output F);
assign F = ~((A & B) | (C & D));
endmodule
// end of Verilog code

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OR Gate using Data flow modeling
module or2 (a,b,c);

input a,b;
output c;
assign c= a|b;
endmodule

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4-1 Multiplexer - Dataflow Verilog
// 4-to-1 Line Multiplexer: Dataflow Verilog Description (Boolean)
module multiplexer_4_to_1_df_v(S, I, Y);
input [1:0] S;
input [3:0] I;
output Y;
assign Y = (~ S[1] & ~ S[0] & I[0])| (~ S[1] & S[0] & I[1])
| (S[1] & ~ S[0] & I[2]) | (S[1] & S[0] & I[3]);
endmodule

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2-to-4 Line Decoder Dataflow Verilog
// 2-to-4 Line Decoder with Enable: Dataflow Verilog Desc.
module decoder_2_to_4_df_v(EN, A0, A1, D0, D1, D2, D3);
input EN, A0, A1;
output D0, D1, D2, D3;
assign D0 =(EN & ~A1 & ~A0);

assign D1 =(EN & ~A1 & A0);
assign D2 =(EN & A1 & ~A0);
assign D3 =(EN & A1 & A0);
endmodule

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Sensitivity list
Procedural statements in an always block executes sequentially.

However, always block itself executes concurrently with other
concurrent statements in the same module (instance,
continuous statement, and always)

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Blocking statement – immediate assignment
Non-blocking statement – late assignment

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A non-blocking statement evaluates its right-hand side
immediately, but does not assign this value to the left-hand side
until an infinitesimal delay after the entire always block has
completed execution

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Learn the rules

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Points to be noted

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Points to be noted

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Verilog

EEN-611 FPGA Implementation of Signal Processing

The simulator runs the specified input sequence on the described

Verification – functional verification, timing verification

EEN-611 FPGA Implementation of Signal Processing

Design may be decomposed hierarchically

EEN-611 FPGA Implementation of Signal Processing

EEN-611 FPGA Implementation of Signal Processing

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

Reserved words or Keywords:

module, input, output, assign and endmodule.

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

The keyword input, output, inout is followed by comma separated list of

EEN-611 FPGA Implementation of Signal

The signal can be multi-bit or vector.

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

A net corresponds to roughly a wire in a physical circuit. This provides

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

n is a decimal number size of the literal in bits. No of bits

EEN-611 FPGA Implementation of Signal

{2’ b00, 2’ b01} = 4’ b0001

{byte1, byte1, byte2, byte3} = 32 bit vector

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

4’ b0100 && 4’ b1011 is true && true

Logical operations are preferred in

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

wire [1:0] not_S; // connecting NOT-AND

wire A0_n, A1_n, N0, N1, N2, N3;

1. A dataflow description is based on function rather than

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

module or2 (a,b,c);

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

assign D0 =(EN & ~A1 & ~A0);

EEN-611 FPGA Implementation of Signal

Procedural statements in an always block executes sequentially.

EEN-611 FPGA Implementation of Signal

Non-blocking statement – late assignment

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

EEN-611 FPGA Implementation of Signal

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