An embedded system is an electronic/electro-mechanical

system designed to perform a specific function involving

a combination of both hardware and firmware (software).

• Electronic/Electro-Mechanic
• A Specific Function
• Combination of Hardware & Firmware.
• Respond, monitor, control external
environment using sensors and actuators.

“ A Combination of hardware (electro

/electro-mechanical ) & Software performing
a specific task without human intervention”
2
 A General Purpose
Operating System in
the hard-disk to run
large number of
applications( Microsoft
Onboard Hard disk
word, games, drivers so A General Purpose
Drive and gigabytes
on Processor
size RAM
Which are re-installable

Peripherals: USBs,
A General Wifi, Ethernet,
A CD Reader/Writer Computing System Bluetooth, Video port
so on…

3
A general purpose Computing system is
 A combination of general purpose processor and operating
system used to run large number of applications.
 All these Operating system and applications are changeable and
re-installable.
 The selection criteria for a general purpose computing system is
it’s performance. Always “FASTER IS BETTER”
 Power Management
 Less/Not tailored to reduce the operating power requirements.
 No options for different levels of power management
 Response Requirement of applications running on general purpose
system are Not Time Critical.
 Execution behavior Need NOT be deterministic.
4
 NO: It is Not possible to ANY
changes by the End User in a
Embedded System. It is
designed for doing a specific
Is it possible to write task.
a application and Can we change the
No provision to change OS,
download into Operating System ?
Functionality, new
existing embedded (Can you change OS
applications written can not
System? DVD of DVD?)
be downloaded.

NO NO
Can you add a A Embedded Is it possible to change
software / driver to System the Functionality of a
interface any other (DVD/Washing existing Embedded
NO NO System?
device ? Machine)
DVD to Television?
DVD IS INTERFACED WITH A DISPLAY DEVICE CONTROLLED BY A REMOTE :
IT BASICALLY DECODES DIGITAL VIDEO SIGNAL AND GENERATES VIDEO AS THE O/P
5
DISPLAYED ON MONITOR
 Embedded System are combination of special purpose hardware
and firmware for performing specific task.
 It may/may not have have Operating System.
 A firmware of embedded system is pre-programmed and not
alterable by end user (Exceptions in System supporting OS kernal
image flashing is allowed )
 Key features like performance, Power requirements, Memory
usage etc. are deciding factors for selection of embedded system.
 Highly Tailored to take advantage of Power Saving Modes by
hardware and software.
 Response time is highly critical in some embedded system.
 Execution behaviour is deterministic for certain types of
embedded system” REAL TIME SYSTEMS”

6
 Generation based classification (Size and type of MP/MC,
Programming Language, Operating system)
 Based on generation as
▪ First Generation
▪ Second Generation
▪ Third Generation and
▪ Fourth Generation
 Complexity and performance requirements
▪ Small Scale Embedded System
▪ Medium Scale Embedded System
▪ Large Scale Embedded System
 Based on deterministic behavior
 Based on triggering.

7
Generation Size and Type of Programming Operating Examples
MP/MC System
FIRST 8/4 bit (8085/Z80) Assembly NO Digital Telephone
Key pad, SM Control

SECOND 16 bit MP & 8/16 Bit Assembly with May / May Not DAS ,Supervisory
MC Complex Control & DA(scada)
Instruction Sets
THIRD 32 bit MP and 16 bit More Powerful Dedicated RTOS
MCUs, and Complex and General
Domain(DSP) & Instruction with Purpose OS
Application Specific Pipelining.
ICs (ASIC)
FOURTH SoC, More Powerful RTOS
Reconfigurable and Complex
Processors and Instruction with
Multicore Pipelining.
8/28/2019
Processors 8
1. Small-scale Embedded system:
▪ Simple in application need
▪ Performance not time-critical.
▪ Built around low performance & low cost 8
or 16 bit µp/µc.
▪ Example: an electronic toy.
2. Medium-scale:
▪ Slightly complex in hardware & firmware
requirement.
▪ Built around medium performance & low cost
16 or 32 bit µp/µc.
▪ Usually contain operating system.
▪ Examples: Industrial machines
3.Large-scale:
▪ Highly complex hardware & firmware.
▪ Built around 32 or 64 bit RISC µp/µc or PLDs or
Multicore Processors.
▪ Response is time-critical.
▪ Examples: Mission critical applications.
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 This classification is applicable for “Real Time” systems.
 Real Time Operations: Operations must be completed by
deadlines.
 The task execution behavior of an embedded system
may be
▪ Deterministic (if the response time is predictable)or
▪ Non-deterministic.

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Based on execution behavior Real Time embedded systems are divided into Hard
and Soft.

HARD REAL TIME SOFT REAL TIME

Missing Deadlines causes failure.

Therefore we can not miss the Missing deadlines results in degraded
deadlines. performance.

Ex: Planes, A Nuclear Reactor, Ex: ATM, Bill payment device.

8/28/2019 11
 Embedded systems which are “Reactive” in nature can
be based on triggering.
 Reactive systems can be:
▪ Event triggered
▪ Time triggered
Example: Process Control System in Industrial Control Application

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 Control (sensors and
Data (signal) processing Data collection/ Storage/
actuators)
(speech and audio codec) Representation

Purpose of
Embedded System Data communication
Monitoring (patient) (satellite communication)
ASIC & SoC

13
 Embedded Systems Designed for Data Collection perform acquisition of data
from external world.
 Data Collection is done for
 Storage
 Analysis
 Manipulation and
 Transmission.
 Data refers to any kind of information viz a text,voice,video,electrical signal or
any other measurable quantity.
 Data acquired may be analog/Digital in nature.
 Embedded system may be with analog capturing capability where analog
signals can be directly captured or with digital capturing capability.
 A Analog to Digital conversion may be required if a analog data is captured by
a digital embedded system. If data is digital it can be directly captured.

14
 Collected data
▪ May be Directly stored in the system or Transmitted to other
system or Processed by the system or May be deleted instantly
after giving meaningful representation.
Ex: Pure Measurement applications without storage.
Control and Instrumentation domain, collect data and give
meaningful representation of collected data graphically and delete
the collected data when new data arrives at the data collection
terminal( A analog/digital CROs),Medical Domain for Monitoring.
Collected data stored for the purpose of processing and analysis :
Monitoring instruments with storage memory card -Medical

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 The data collected by a embedded terminal may require
transmitting of same to other system located remotely.
 The transmission is achieved by either
▪ Wire-line medium (RS232C,USB,TCP/IP etc) or
▪ Wireless Medium (Bluetooth,Wifi,ZigBee,GPRS etc)
 Wireless Medium offers cheaper connectivity solution and
make the communication link free from hassle of wire
bundles.
 Data can be either transmitted by analog /digital means

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 Data(Signal) Processing  Monitoring

 Embedded System with  Embedded systems used for

signal processing Monitoring purpose are
functionalities are used to determining the
employed in applications state of some variables
demanding signal using input with
processing like speech monitoring functionality
coding, synthesis, audio  Ex: ECG ,CROs
video codec, transmission  These devices can not be
applications used for controlling.
 Ex: A digital hearing aid

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 Consumer Electronics: Camcorders, Cameras.
 Household appliances: Washing machine, Refrigerator.
 Automotive industry: Anti-lock breaking system(ABS),
engine control.
 Home automation & Security systems: sprinklers, fire
alarms.
 Telecom: Cellular phones, telephone switches.
 Computer peripherals: Printers, scanners.
 Computer networking systems: Network routers and
switches.
 Healthcare: EEG,ECG machines.
 Banking & Retail: Automatic teller machines, point of
sales.
 Card Readers: Barcode, smart card readers.
18
Communication
Interface Embedded Firmware
(USB,DB9,Ethernet) Embedded to perform a
Memory
Particular Task

I/P PORT System Core O/P PORT

(SENSORS) (ASIC/SoC/FPGA DAC+ (Actuators)
+ADC /DSP/MP/MCU) LED,BUZZER,RELAY

Other Supporting Integrated Diagnostic Unit

Circuits & Subsystems 1. Fault Detection and
(Human Interface, Diagnostic correction
tools, Heat Management) 2. Self Test Tools
19
8/28/2019 20
8/28/2019 21
 Embedded systems are domain and application specific and are built around a
central core.
 The core of the embedded system falls into any of the following categories:
 General purpose and Domain specific processor.
▪ General Purpose Processors: Microprocessors (GPP)
▪ Domain Specific - Application Specific Instruction Processors(ASIP) :
They have processor with architecture and instruction set optimized to
specific-domain/application requirements
 Microcontrollers(industrial)
 Digital signal processors(DSP) ,Networking Processors.
 Automotive and telecom
 Application Specific Integrated Circuits (ASIC)
 Programmable logic devices (PLD’s):CPLDs & FPGA
 SoC (Multiprocessor cores (ARM +DSP + Peripherals))
22
 ASIP: MCU, DSP,N/W
GPP:PENTIUM4,8086,AMD PROCESSOR,SOC
 CPU
On-Chip Peripherals
(ADC,DAC,TIMER,PROTO ICU
CONTROL COLS…)
UNIT
ALU PROGRAM
CPU
MEMORY
SET OF (ALU,
I/O
REGISTERS CONTROL
PORT
UNIT,
DATA
REGISTERS)
MEMORY

8/28/2019 23
 MPUs MCUs
CHIP It is Silicon chip representing CPU It is highly integrated chip containing CPU,
capable of performing Arithmetic and RAM,ROM,GPRs,SFRs,ADC,TIMERI/OPORTS,
Logical operations according to PROTOCOLS like UART, SPI, I2C so on
predefined set of Instructions
Processor Type It is General Purpose Processor Application Specific Instruction Set (ASIP)
processor.
Dependent/ It is a Dependent Unit. System It is independent Unit as it has all the
Independent Designed using GPPs are dependent on requirement units on its chip to work as a
external Memory, IO devices and so on. system.
Application Most of the time it is used in general It is used in application specific / domain
purpose applications specific applications
I/O PORT External Programmable Peripheral Inbuilt Multiple I/O ports are present through
Interface(PPI) -8255 is required to which I/O devices can be interfaced easily.
interface IO devices.
Power Saving Limited Power Saving options Includes lot of power saving options
Options
Pin functions Most of the pins of processor IC do Most of the pins of MCUs do multifunction.
single function.
Bit Handling Rarely find bit handling instructions Find more bit handling instructions
Access Access Time , PCB size of system Access Time , PCB size will be small as they
Time/PCB designed will be more. A glue logic is have onchip peripherals and memory. No glue
Size/Glue logic required in GPP based system logic required as NO external Mmory.
8/28/2019 24
 Processors/Controllers are broadly use the following
hardware charecteristics
 Instruction Set Architecture(ISA):
▪ Reduced Instruction Set Computer (RISC) and
▪ Complex Instruction Set Computer(CISC).
 Bus architecture:
▪ Harvard Bus Architecture and
▪ Van-Neuman Bus Architecture
 Order of Data storage:
▪ Big Endian and
▪ Little Endian

25
 Nature of Instruction Sets: Each instruction perform a single function (not
multiple functions).i.e., Instructions are simple, performing single task.
 Number of machine cycles(clock) required for execution of all the
instructions will be same.
 Pipelined Mode of Execution: Instruction Pipelining is possible as
execution of each instruction uses same T states. This increases the speed of
execution.
 Operations are done on registers only. Operands supported by arithmetic
instructions are registers only. Only LOAD and STORE instructions deal with
memory.
 Number of general purpose registers are large.
 Instruction Formats: Fixed format leading to ALL instruction with same
length.
 Length of program to preform a task would be more as instructions are
simpler doing single task.
 Complexity of Instruction decoder, control & Sequence Generator: Less
 Complexity of Compilers and software developed : More
 Micro coded /Hardwired Instructions: Hardwired
 Debugging of code /firmware developed : Not easy
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8/28/2019 27
 The RISC processors instruction set is orthogonal: it operates on
register.
 The memory access related operations are performed by special
instructions LOAD and STORE :
 Load : the content of memory is loaded to register specified.
 Eg: LOAD R1, Memory Address X :
Memory Location Register

 Store: store the data from a specified register to a specified

memory location.
 Eg : Store R3, Memory Address Z : R3 =7F  Z = 7F.

Register Memory Location

28 August 2019 28
 R1 R2 R3
LOAD R1,x
LOAD R2,y
ADD R3,R1,R2
STORE R3,Z

ALU
01H x
7FH y
2DH z

8/28/2019 29
 Wash 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Non-pipelined Pipelined
Dry 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

non-pipelined dish cleaning Time pipelined dish cleaning Time

Fetch-instr. 1 2 3 4 5 6 7 8

Decode 1 2 3 4 5 6 7 8

Fetch ops. 1 2 3 4 5 6 7 8 Pipelined

Execute 1 2 3 4 5 6 7 8
Instruction 1
Store res. 1 2 3 4 5 6 7 8

Time
pipelined instruction execution

30 August 2019
28
 Bus
Architecture Van Neumann

 IT SHARES COMMON
BUS FOR FETCHING
PROGRAM AND DATA P
MEMORY r Data
Memory
 PROGRAM MEMORY o
AND DATA MEMORY Space
MAY BE SHARED IN s
THE SAMAE CHIP. THIS s
MAY LEAD TO
ACCIDENTAL e Program
CORRUPTION OF
s Memory
PROGRAM MEMORY.
Space
o
 LOW PERFORMANCE
r
 CHEAPER

8/28/2019 31
Bus
Architecture Harvard

 IT HAS SEPARATE
BUS FOR FETCHING
PROGRAM AND DATA P
MEMORY AND EVEN
r Data
CONTROL LINES ARE
SEPERATE o Memory
Space
 PROGRAM MEMORY c
AND DATA MEMORY
ARE IN SEPARATE e
CHIP. THEREFORE
NO ACCIDENTAL
s Program
CORRUPTION OF s Memory
PROGRAM MEMORY. Space
o
 HIGH
PERFORMANCE r
 HIGH COST

32
8/28/2019 33
LITTLE ENDIAN BIG ENDIAN

8/28/2019 34
 DSPs are powerful special purpose 8/16/32 bit microprocessor
designed to meet the computational demands and power
constraints of today’s embedded audio, video and
communication applications.
 DSP are 2 to 3 times faster than general purpose
microprocessors in signal processing applications. This is
because of the architectural difference between DSP and general
purpose microprocessors.
▪ DSPs implement algorithms in hardware which speeds up the execution-
Hardwired

28 August 2019 35
 Data Data
Memory 1 Memory 1

Computational Engine:
1. Shifter Input/
Program
2. Hardwired Multipliers Output
Memory
3. MAC PORT
4. ALU

8/28/2019 36
 ASICs is a microchip design to perform a specific
and unique applications.
 Use of single chip to integrate several functions
reduces the system development cost.
 Most of the ASICs are proprietary (which having
some trade name) products, it is referred as
Application Specific Standard Products(ASSP).
 As a single chip ASIC consumes a very small area in
the total system. Thereby helps in designing smaller
system with high capabilities or functionalities.

37
 A PLD is an electronic component. It used to build
digital circuits which are reconfigurable.
 A logic gate has a fixed function but a PLD does not have a
defined function at the time of manufacture.
 PLDs offer customers a wide range of logic capacity,
features, speed, voltage characteristics.
 PLDs can be reconfigured to perform any number of
functions at any time.
 A variety of tools are available for the designers of PLDs
which are inexpensive and help to develop, simulate and
test the designs.
 Ex: FPGAs(Field Programmable Gate arrays) :1000 gates
CPLD(Complex Programmable Logic Device):Highest
Logical density

28 August 2019 38
 More flexibility during the design cycle.
 Not require long lead times for prototypes or
production parts as PLDs are already on a
distributors shelf and ready for shipment.
 PLDs can be reprogrammed even after a piece of
equipment is shipped to a customer

28 August 2019 39
 FLASH ROM NVRAM

MROM PROM EPROM EEPROM

8/28/2019 40
  Masked ROM are hardwired devices that contain preprogrammed set of
data/instruction.
 One Time Programmable device.
 Device is factory programmed by masking and metallization at the time of
production itself according to data provided by end user.
 MROM need to be used
 Once design is proven and the firmware requirements are tested and
frozen, then the binary data corresponding to it can be given to MROM
fabricators.
Advantages:
Low cost for High volume production. Per bit, mask ROM is more compact
than any other kind of semiconductor memory. Size defends on firmware size.
Drawback:
Inability to modify the device –that is not possible to alter the bit information.
8/28/2019 41
 It is One Time Programmable device is not programmed by
manufacturer. End user is responsible for programming.
 This memory has nichrome / polysilicon wires arranged in
matrix.
 These wires can be functionally viewed as fuse. These fuses are
blown selectively according to bit patterns by PROM
programmer.
▪ If fuse is not blown/burnt – logic 1 : It is default state and
▪ if fuse is blown/burnt – logic 0
 Use: Commercial Embedded system once prototype is finalized.
 Drawback: Not reprogrammable. Therefore NOT useful and
worth for development purpose as development phase involves
continuous changes in firmware before finalizing. Use of OTP
at development stage is not economical.
42
EPROM
 These are re-programmable
devices. These use gate of MOS
devices to store the data.
 The crystal quartz crystal
window exposed to UV rays for
fixed interval of time erases the
stored information.
 Drawback: Every time memory
unit need to removed from
circuit board and put in UV
erased for fixed time(20 to 30
min). It is tedious and time
consuming.
ELECTRICALLY EPROM
 Information stored in
EEPROM can be erased by
using electrical signals at the
register / byte level
 Advantage: Erased and
reprogrammed in the circuit
itself.
 Drawback : Capacity is
limited (kilo bytes)

8/28/2019 43
FLASH NVRAM
 These are High capacity re-  Non Volatile RAM with
programmable devices battery back up.
arranged in matrix form as
pages.  It uses static RAM cells with
 Stores information in array of battery packed in single
floating gate of MOS. package.
 Erasing of memory can be
done at page level without
affecting other pages.
 Each page need to be erased
before re-programming.
 Erasable capacity is 1000
cycles

8/28/2019 44
 RAM

SRAM DRAM NVRAM

FPMRAM EDORAM SDRAM ESDRAM Rambus

Fast Page Mode Extended Data Output Synchronous Enhanced SDRAM Rambus

8/28/2019 45
Basic DRAM

Address bus multiplexed

between row and data Refresh
column components Circuit
Row and column

ColAddr. Buffer
DataIn Buffer
addresses are latched in,
sequentially, by strobing Sense
ras and cas signals, Amplifiers
respectively
Refresh circuitry can be rd/ wr cas Col Decoder
external or internal to

cas,ras, clock
DRAM device DataOut Buffer

Row Decoder
strobes consecutive

RowAddr.Buffer
memory address
periodically causing
memory content to be
refreshed
Refresh circuitry ras
disabled during read address
or write operation Bit storage array

46
 Each row of memory bit array is viewed as a page
 Page contains multiple words
 Individual words addressed by column address
 Timing diagram:
 row (page) address sent
 3 words read consecutively by sending column address for each
 Extra cycle eliminated on each read/write of words from same page

ras

cas

row col col col

address

data data data data

47
 Improvement of FPM DRAM
 Extra latch before output buffer
 allows strobing of cas before data read operation completed
 Reduces read/write latency by additional cycle

ras

cas

addres row col col col

s
data data data
data
Speedup through overlap

48
 SDRAM latches data on active edge of clock
 Eliminates time to detect ras/cas and rd/wr signals
 A counter is initialized to column address then incremented
on active edge of clock to access consecutive memory
locations
 ESDRAM improves SDRAM
 added buffers enable overlapping of column addressing
 faster clocking and lower read/write latency possible

clock

ras

cas

address row col

data data data data
49
 More of a bus interface architecture than
DRAM architecture
 Data is latched on both rising and falling edge
of clock
 Broken into 4 banks each with own row
decoder
 can have 4 pages open at a time
 Capable of very high throughput

50
 SRAM stores data in the form of
voltage.
 Made up of Flip-flops.
 SRAM is realized using 6
MOSFETs
 4 Transistor are used for
building latch(flip-flops) part of
memory cell.
 2 for controlling the access.
 SRAM is fast in operation due to
switching capabilities.

28 August 2019 51
28 August 2019 52
 High Capacity.
 Less expensive and slow.
 Made up of MOSFET and a capacitor.
 MOSFET acts as gate for incoming and
outgoing data.
 Capacitor acts as the bit storage unit.
 Disadvantage is that information is stored
as charge it gets leaked off with time and
hence requires Refreshing.

28 August 2019 53
 Execution of the ROM is very slow compared to SRAM.
 RAM access is 3 times as fast as ROM access.
 Shadowing of memory is a technique adopted to solve the
execution speed problem in processor-based systems.
 ROM BIOS stores the hardware configuration information
like address assigned for various serial ports and other non-
plug ‘n ‘ play devices.
 So this BIOS is read and system is configured according to it
during system boot up and it is time consumed.
 During the Boot up copy the BIOS to the shadowing RAM
and Write protect the RAM then disable the BIOS reading.

28 August 2019 54
8/28/2019 55
 The controller accepts the information from the sensing unit, makes
decisions based on the control algorithm, and outputs commands to the
actuating unit. The actuating unit consists of an actuator and optionally a
power supply and a coupling mechanism.
 Sensor is a device that when exposed to a physical phenomenon
(temperature, displacement, force, etc.) produces a proportional output
signal (electrical, mechanical, magnetic, etc.).
 The term transducer is often used synonymously with sensors. However,
ideally, a sensor is a device that responds to a change in the physical
phenomenon. On the other hand, a transducer is a device that converts
one form of energy into another form of energy.
 Sensors are transducers when they sense one form of energy input and
output in a different form of energy. For example, a thermocouple
responds to a temperature change (thermal energy) and outputs a
proportional change in electromotive force (electrical energy). Therefore,
a thermocouple can be called a sensor and or transducer.
8/28/2019 56
 Signal Conditioning
 Normally, the output from a sensor requires post processing of the
signals before they can be fed to the controller.
 The sensor output may have to be demodulated, amplified, filtered,
linearized, range quantized, and isolated so that the signal can be
accepted by a typical ADC of the controller.
 Some sensors are available with integrated signal conditioners, such
as the microsensors. All the electronics are integrated into one
microcircuit and can be directly interfaced with the controllers.
 Calibration
 The sensor manufacturer usually provides the calibration curves. If the
sensors are stable with no drift, there is no need to recalibrate.
 However, often the sensor may have to be recalibrated after
integrating it with a signal conditioning system. This essentially
requires that a known input signal is provided to the sensor and its
output recorded to establish a correct output scale. This process
proves the ability to measure reliably and enhances the confidence. If
the sensor is used to measure a time-varying input, dynamic
calibration becomes necessary.
8/28/2019 57
 The output span of the transducer must be matched to the input span
of the ADC to achieve optimum performance.
 There is no reason to expect that the selected transducer's output
voltage span matches the selected ADC's input voltage span.
 When Spans are not equal?
 Span match but there is a offset. – A Level Shifter is required
 Span mismatch but No offset - A amplifier is required.
 Span mismatch and there is offset – A Level Shifter and Amplifier is required.
 If spans are unequal .
 Transducer data is lost and/or ADC dynamic range is not fully utilized .

58
 The output span of the transducer must be matched to the
input span of the ADC to achieve optimum performance.
 When the spans are mismatched
 Either the transducer output voltage does not fit into the ADC
input span thus losing sensor data, or
 The transducer output voltage does not fill the ADC input span
thus losing ADC accuracy. The latter situation requires an
increase in ADC dynamic range (increased cost) because a
higher bit converter must be used to achieve the same
resolution.
 The best analog circuit available for matching the spans is the
op amp because it level shifts and amplifies the input voltage to
make the spans equal. The op amp is so versatile that it shifts
the signal's dc level and amplifies the input signal
simultaneously.

8/28/2019 59
 The I/O subsystem of the Embedded system facilitates the
interaction of the embedded system with the external world.
 The Sensors and actuators connected to the input and
output ports respectively.
 The sensors may not be directly interfaced to the input
ports, instead they may be interfaced through signal
conditioning and translating systems like ADC,
Optocouplers, etc
 Input devices :Push Button Switches, Keyboard.
 Output devices : LED, 7-Segment LED Display, Stepper
motor, Relay, Piezo Buzzer.

28 August 2019 60
28 August 2019 61
 Based on the Coil winding
arrangement , a two-phase stepper
motor is classified into 2 types:
 (1) Unipolar and (2) Bipolar
 (1) Unipolar :
 Contains two windings per phase.
 Direction is controlled by changing
the direction of current.
 Current in one direction flows
through one coil and in the opposite
direction flows through the other
coil.

28 August 2019 62
8/28/2019 63
 (2) Bipolar :
 Contains single winding per
phase.
 For reversing the motor
rotation the current flow
through the windings is
reversed dynamically.
 It requires complex circuitry
for current flow reversal.
 The stator winding details for
two phase Bipolar stepper
motor is shown.

28 August 2019 64
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28 August 2019 68
 Relay is an electro-mechanical device.
 Acts as an dynamic path selectors for signals and power.
 Contains relay coil made up of insulated wire on a metal core and
metal armature with one or more contacts.
 When a voltage is applied to relay coil, current flows through the
coil, which in turn generates a magnetic field, this attracts the
armature core and moves the contact point.

28 August 2019 69
 The Relay is normally
controlled using a Relay
driver circuit connected to
the port pin of the
processor/controller.
 A transistor is used for
building relay circuit.
 A free-wheeling diode is used
for protecting the relay and
transistor.

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 Piezo Buzzer is piezoelectric device for generating audio
indications in embedded applications.
 Contains a piezoelectric diaphragm which produces audible
sound in response to the voltage applied to it.
 They are of 2 types:
 (1) Self driving : contains all necessary components to
generate sound at a predefined tone.
 (2) External driving : supports the generation of different
tones. The tone can be varied by applying a variable pulse
train to buzzer.

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 It is an input device.
 2 Configurations
 (1) Push to Make
 (2) Push to Break

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1. ONBOARD COMMUNICATION
INTERFACES.
These are used for internal
communication of the embedded
system.
i.e: communication between
different components present on
the system.
 Universal Asynchronous Receiver
Transmitter (UART)
 Serial Peripheral Interface (SPI)
 Inter Integrated Circuit (I2C)
 1-Wire Interface
 Parallel Interface
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2. EXTERNAL OR PERIPHERAL
COMMUNICATION INTERFACES.
These are used for external
communication of the embedded
system i.e: communication of
different components present on
the system with external or
peripheral components/devices.
Common examples of external
interfaces are:
 RS-232 C & RS-485
 Universal Serial Bus (USB)
 IEEE 1394 (Fire wire)
 Infrared (IrDA)
 Bluetooth
 Wi-Fi
 Zig Bee
 General Packet Radio Service (GPRS)
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The SPI operation is based upon shift registers. Every device,
whether Master or Slave has an 8-bit shift register inside it. The size of the
shift register could be more than 8-bit as well (like 10-bit, 12-bit, etc), but it
should be the same for both Master and Slave, and the protocol should
support it.
The Master and Slave are connected in such a way that the two shift registers
form an inter-device circular buffer. The following diagram should explains
the hardware setup. Please click on the images to enlarge it and view it in
high resolution.
 Synchronous, bidirectional full
duplex four wire bus.
 Motorola introduced SPI protocol
 It is Single Master – Multiple slave
system./ if multiple master, then
only one master should be active
at a given time.
 Four Signals required are
 MISO - Master In Slave Out
 MOSI - Master Out Slave In
 SCL - Serial Clock
 CS - Chip Select

 If the Slave devices not selected,

their MISO will be disabled

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 Serial Peripheral Control Registers decide
 Whether it should act as Master or Slave.
 Baud rate selection
 Clock signal Control
 The status register hold the
 Various condition of transmission and reception.

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 Keeping synchronization in mind, Master’s role doesn’t end with simply
generating clock pulses at a particular frequency (usually within the range of 10
kHz to 100 MHz). In fact, Master and Slave should agree on a particular
synchronization protocol as well, or else everything will go wrong and data
will get lost. This is where the concept of clock polarity (CPOL) and clock phase
(CPHA) comes in.
 CPOL – Clock Polarity: This determines the base value of the clock i.e. the value
of the clock when SPI bus is idle.
 When CPOL = 0, base value of clock is zero i.e. SCK is LOW when idle.
 When CPOL = 1, base value of clock is one i.e. SCK is HIGH when idle.
 CPHA – Clock Phase: This determines the clock transition at which data will be
sampled/captured.
 The CPHA=0: Data is captured on the first clock edge transition.
 The CPHA =1,data is captured on the second clock edge transition.
 CPOL and CPHA Functionality
 The CLK signal is forced LOW.
 SSEL is forced HIGH.
 The transmit MOSI/MISO pad is in high impedance.
 The SSP is enabled and there is valid data within the transmit
FIFO.
 The start of transmission is signified by the SSEL master
signal being driven LOW. This causes slave data to be enabled
onto the MISO input line of the master. Master’s MOSI is
enabled.
 The data is captured on the rising and propagated on the
falling edges of the SCK signal.
 Continuous back-to-back transmissions, the SSEL signal must
be pulsed HIGH between each data word transfer.
 The CLK signal is forced LOW.
 SEL is forced HIGH.
 The transmit MOSI/MISO pad is in high impedance.
 The SSP is enabled and there is valid data within the transmit FIFO.
 The start of transmission is signified by the SSEL master signal being driven
LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both
master and slave valid data is enabled onto their respective transmission lines. At
the same time, the SCK is enabled with a rising edge transition.
 Data is then captured on the falling edges and propagated on the rising edges of the
SCK signal.
 Single word transfer, after all bits have been transferred, the SSEL line is returned
to its idle HIGH state one SCK period after the last bit has been captured.
 Continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
 During idle periods
 The CLK signal is forced HIGH.
 SSEL is forced HIGH.
 The transmit MOSI/MISO pad is in high impedance.
 The SSP is enabled and there is valid data within the transmit
FIFO, the start of transmission is signified by the SSEL master
signal being driven LOW, which causes slave data to be
immediately transferred onto the MISO line of the master.
Master’s MOSI pin is enabled.
 Data is captured on the falling edges and be propagated on the
rising edges of the SCK signal.
 Single word transmission, after all bits of the data word are
transferred, the SSEL line is returned to its idle HIGH state one
SCK period after the last bit has been captured.
 Continuous back-to-back transmissions, the SSEL signal must
be pulsed HIGH between each data word transfer.
 During idle periods
 The CLK signal is forced HIGH.
 SSEL is forced HIGH.
 The transmit MOSI/MISO pad is in high impedance.
 The SSP is enabled and there is valid data within the transmit
FIFO, the start of transmission is signified by the SSEL master
signal being driven LOW, which causes slave data to be
immediately transferred onto the MISO line of the master.
Master’s MOSI pin is enabled.
 Data is captured on the RISING edges and be propagated on
the FALLING edges of the SCK signal.
 Single word transmission, after all bits of the data word are
transferred, the SSEL line is returned to its idle HIGH state one
SCK period after the last bit has been captured.
 Continuous back-to-back transmissions, the SSEL signal must
be pulsed HIGH between each data word transfer.
 UART based data transmission
is asynchronous form of serial
communication.
 UART does not require clock to
synchronize transmitting end
with receiving end.
 Both ends should have identical
serial communication settings
like
 baudrate,
 number of bits per byte
 Number of start and stop bits
 Parity checking

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 Developed by Phillips semiconductors in 1980.
 Synchronous, Bi-directional, half duplex , two wire serial interface
bus.
 It comprises of two buses :
 Serial clock–SCL & Serial Data– SDA
 All data transfer are byte(8) oriented transfer
 Wide range of bus speed (100kbps, 400kbps, 1Mbps, 3.4Mbps, 5Mbps)
 No need of additional Chip Selection Signal, Addressing is done
through SDA line.
 All devices signal each other by pulling down SDA and SCL ,
Therefore we always need Two external pull up resistors for SDA and
SCL. The value of pull up resistors required varies with speed. (10K
for 100Kbps and 2K for 400Kbps).

89
 Devices connected by I2C can act as
either master or slave
 Master and Slave devices can be a
Transmitter / Receiver and can switch
roles during bus transaction.
 I2C is a shared bus system to which
many devices can be connected.
 The master device is responsible for
 Controlling communication by
initiating/ terminating data transfer.
 Generates all clock pulses.
 Devices acting as slave wait for
commands (address, read/write) from
the master and respond to those
commands.
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 Start and Stop Conditions
 Master Generates both START and STOP signal.
 A HIGH to LOW transition of the (SDA) data line while
the clock line is high is defined as either a start or a stop
condition.
 A low-to-high transition on the SDA line while the SCL is
high defines a STOP
 The bus is considered busy after a start condition, until a
stop condition occurs
 Bit transfer on bus
 In normal data transfer, the data line only changes state
when the clock is low
 I2C Addressing
 Each node has a unique 7 (or 10) bit address

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 Repeated START
 This is useful for when the master wishes to start a new communication, but does not wish to let the bus go idle
with the STOP condition, which has the chance of the master losing control of the bus to another master (in multi-
master environments).
 Data Validity and Byte Format
 One data bit is transferred during each clock pulse of the SCL.
 One byte is comprised of eight bits on the SDA line.
 A byte may either be
▪ a device address,
▪ register address, or
▪ data written to or read from a slave.
 Data is transferred Most Significant Bit (MSB) first.
 Any number of data bytes can be transferred from the master to slave between the START and STOP conditions.
 Data on the SDA line must remain stable during the high phase of the clock period, as changes in the data line
when the SCL is high are interpreted as control commands (START or STOP).

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Integrated Chips With Different Logic Levels( 3.3/5v) can be interconnected
without level shifter as open drain is pulled up using resistors to either 3.3/5v

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 Data is Valid when clock is High
 A repeated start avoids releasing the bus and therefore prevents another master
from taking over the bus

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Master writing to a Slave

Master Reading from a Slave

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•When the bus is in idle state, the open drain will be in floating state and
output lines will switch to high impedance state. For proper operation the
bus lines are pulled up to logic 1 using pull up resistors.
•I2C devices are wire ANDed together.
• If any single node writes a zero, the entire line is zero
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 Bidirectional, Half duplex, Serial
signaling protocol that powers
and operates devices over a
single connection and ground
 Single master connected to
one/more slaves
 Two standard speeds
 15.4 kbps
 125 kbps
 Factory programmed ,unique
unalterable ID(64bits) for every
device
 Master Initiated and Controlled
communication.

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• Open drain Master with 3/5 V
resistive pull up
• Internal Capacitor provides
power to the slave.
• Communication with time slots
define binary 0/1
• One time slot is 60 us
• Write Logic 1=15us high and
45us low in time slot
• Write Logic 0 means pulling the
bus for 1 time slot min and max
it may be 2 slots
• To read bit from slave master-
pulls the low for (1-15)us
• Slave self clocked from master
edges.
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40
 • One Time slot=60us
• Reset Pulse= 8
slots=480u
• Slave should respond
within 60us of reset
release by master with
presence pulse of 60 us

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 RS-232 is wired, asynchronous, serial, full duplex commn.
 RS 232 interface was developed by EIA (Electronic Industries
Associates)
 RS 232 is the extension to UART for external communications.
 RS-232 logic levels use:
 +3 to +25volts to signify a "Space" (Logic 0) and
 -3 to-25 volts to signify a "Mark" (logic 1).
 RS 232 supports two different types of connectors :
 RS 232 interface is a point to point communication interface and
the devices involved are called as Data Terminating Equipment
(DTE) And Data Communications Equipment (DCE)
 Embedded devices contain UART for serial transmission and generate
signal levels as per TTL/CMOS logic.
 A level translator IC (like Max 232) issued for converting the signal
lines from UART to RS 232 signal lines for communication.The
vice versa is performed on the receiving side.

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 Point to point communication interface.
 Device involved in RS232 communication are called DTE “Data
Terminal Equipment” and DCE “Data Communication Equipment”
 If No data flow control required, then only TxD, RxD along with GND
are used.
 If Data Flow Control required ,then various control signal are used like DCD,
DSR, DTR,RTS,CTS.
 Communication Between DTE and
DCE is coordinated Request to Send
( RTS) and Clear To Send (CTS)
 When DTE has data to send it
activates RTS and if DCE is ready to
receive it activates CTS

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 ZC : ZigBee
Coordinator.
 ZR : ZigBee Router
 ZED :ZigBee End
Device

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 GPRS is a communication technique for transmitting data over a
mobile communication network like GSM.
 Data is sent as packets in GPRS communication.
 The transmitting device splits the data into several related
packets.
 GPRS supports a theoretical maximum transfer rate of 171.2kps.
 In GPRS Communication, the radio channel is concurrently shared
between several user instead of dedicating a radio channel to cell
phone user.
 GPRS supports Internet Protocol, Point to Point Protocol (PPP).

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 Refer to the control algorithm (Program instructions) and
the configuration settings that the Embedded system
developer dumps into code memory of the Embedded
system.
 Methods for developing the Embedded Firmware:
 (1) Write the program in High level languages like Embedded
C/C++ using an IDE.
 (2) Write the program in Assembly language using the
instructions supported by our application’s target
processor/controller.

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 (1) Reset Circuit.
 (2) Brown-out Protection Circuit.
 (3)Oscillator Unit.
 (4) Real –Time Clock (RTC)
 (5) Watchdog Timer.

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 It is essential to ensure that device is not operating at a
voltage where the device is not guaranteed to operate,
during system power ON.
 It brings the internal register and the different hardware
systems of the processor/controller to a known state and
starts the firmware execution from the reset
vector(0x0000).
 The reset signal to the processor can be applied at power ON
through an external passive reset circuit.

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 A resistor capacitor based
passive reset circuit for
active high and low
configurations.
 The reset pulse width can
be adjusted by changing
the resistive value R and
capacitive value C

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 BOPC prevents the processor/controller from unexpected
program execution behavior when the supply voltage to the
processor/controller falls below a specified voltage.
 It is essential for the battery powered devices since there are
greater chances to drop below the required threshold.
 A Brown-out protection circuit holds the processor/controller in
the reset state.
 It is implemented using Zener diode and transistor for the
processor/controller with active low Reset logic.

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 It has Zener diode and
Transistor.
 Transistor conducts
when Vcc = Vbe + Vz.
 BOPC holds the
processor in reset state,
when operating voltage
falls below the threshold.

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 RTC is a System component responsible for keeping track of
time.
 RTC holds information like current time(HMS) , date, and
supplies timing reference to the system.
 RTC function even in absence of power.
 RTC can interrupt the OS kernel by asserting the interrupt
line of then processor to which the RTC interrupt line is
corrected.

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 WTC is a hardware timer for monitoring the firmware
execution.
 WTC increments or decrements a free running counter with
each clock pulse and generates an reset signal to reset the
processor.

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