USB Basics

USB Supports simultaneous data transfers b/w host & device. USB Basics

USB 1.0/2.0 Signals Despite having multiple devices connected at one time, only
one device at a time can communicate with a host controller.
Host Connector
Host Hard-ware Responsibilities:

Host Soft-ware Responsibilities:

Device Connectors
Mini and Micro connectors have five pins, rather than four.
The extra pin is the ID pin and identifies the host and the device in OTG applications
Identifies Type A and Type B Plug:
A plug: connected to Signal ground
Monitor activity on the bus
B plug: not connected
• USB is host controlled so only one host can per bus and does not support any form of multi-master arrangement. Up to 127 devices can be attached to USB bus at once. The USB host is
responsible for undertaking all transactions and scheduling bandwidth. Data on the USB bus is transmitted LSb first. The speed of USB bus is known by the applied voltage on the bus using
built in pull-up resistor.
• USB devices consist of one or more device functions, such as a mouse, keyboard, or audio device for example. Each device is given an address by the host, which is used in the data
communication between that device and the host. USB device communication is done through pipes. These pipes are a connection pathway from the host controller to an addressable
buffer called an endpoint. An endpoint stores received data from the host and holds the data that is waiting to transmit to the host. A USB device can have multiple endpoints and each
endpoint has a pipe associated with it. There are two types of pipes in a USB system, control pipes and data pipes. The USB specification defines four different data transfer types.
Data Transfer Latency delivery throughput Priority
USB Transfer Types
Interrupt Gauranteed Gauranteed Low High
- Control
- Bulk Bulk Gauranteed High Low
- Isochronous
Isochronous Gauranteed High
- Interrupt Audio/Video stream

Control Gauranteed Gauranteed Low

USB Packets:
SYNC: All packets must start with a sync field. The sync field is 8 bits long
at low and full speed or 32 bits long for high speed and it may be shorter. It
is used to synchronize the clock of the receiver with that of the transmitter.
The last two bits indicate to the end of the SYNC field and, by inference,
the start of the PID
Four PACKET types:
Token packets - indicate the type of transaction to follow. (3 types)
In - Informs the USB device that the host wishes to read information.
Out - Informs the USB device that the host wishes to send information.
Setup - Used to begin control transfers
Data packets - contain the payload.
Handshake packets - for acknowledging data or reporting errors (3 types)
ACK - Acknowledgment that the packet has been successfully received.
NAK - Reports that the device temporary cannot send/receive data. Also used
during interrupt transactions to inform the host there is no data to send.
STALL - The device finds its in a state that it requires intervention from the host.
Start of frame packets - indicate the start of a new frame.
USB Functions:
USB devices which provide a capability or function such as a
Printer, Zip Drive, Scanner, Modem or other peripheral called
a function.
Most functions will have a series of buffers each buffer will
belong to an endpointEP0 IN,EP0 OUT etc
Example: The host sends a device descriptor request. The USB
hardware will read the setup packet and determine from the
address field and will copy the payload of the following data
packet to the appropriate endpoint buffer dedicated by the
value in the endpoint field of the setup token.
- HW will then send a handshake packet to ack the reception
of the byte and generate an internal interrupt to the CPU for
the appropriate endpoint signifying it has received a packet.
-The software now gets an interrupt, and should read the
contents of the endpoint buffer and parse the device
descriptor request.
• A USB device will enter suspend state when there is no activity on the bus for greater than 3.0 ms. It then has
a further 7 ms to shutdown the device. so USB has a start of frame packet or keep alive sent periodically on
the bus. This prevents an idle bus from entering suspend mode in the absence of data.
• Global Suspend used when the entire USB bus enters suspend mode collectively.
• Selective suspend selected devices can be suspended by sending a command to the hub .
The device will resume operation when it receives any non idle signaling.
If a device has remote wakeup enabled then it may signal to the host to resume from suspend.
 The packet ID toggles between DATA0 and DATA1 for each successful data packet transfer and packet closes with a 16-bit CRC

The SOF gives a way for devices to identify the beginning of a frame and synchronize
with the host. Also used to prevent a device from entering suspend mode (which it
must do if 3 ms pass without an SOF). SOF packets are only seen on full- and high-
speed devices and are sent every millisecond and With a High-Speed device, an SOF is
sent out every 125 us and frame count is only incremented every 1 ms.
 USB Bus
In USB data communication, the USB encodes the data by using the NonReturn-to-Zero Inverted (NRZI) transmission
scheme. In NRZI encoding, a logic 1 is represented by no change in voltage level and a logic 0 is represented by a change
in voltage level. To ensure the presence of sufficient signal transitions for clock recovery, bit stuffing or simply insertion
of non-information bits into data. “0” bit is injected onto the data bus after the occurrence of 6 consecutive “1” bits

USB specification defines six device states. During enumeration, a device moves through four of the states: Powered, Default, Address, and Configured.
(The other states are Attached and Suspend)
After detecting the presence of a device the host will initiate a transfer with the device to
Enumeration: mixture of
determine what it is. The host does this by asking for device descriptors which define the device
(1) hardware techniques for detecting something is present
class and what drivers need to be loaded.
(2) software to identify what has been connected
USB Descriptors: Devices are identified with the help of descriptors. USB descriptors are the data structures that enable the host to learn about a device
(1) Each device (except compound devices) has one and only one Device Descriptor that contains information about
the device and specifies the number of configurations the device supports.
(2) For each configuration all the device has Configuration Descriptor which provides information about the device’s
use of power and the number of interfaces the configuration supports.
(3) For each interface, the device has an Interface Descriptor that specifies the number of endpoints.
(4) Each endpoint has an Endpoint Descriptor that contains information needed to communicate with the endpoint.
SuperSpeed devices must provide a Binary device Object Store (BOS) Descriptor and at least two subordinate Device
Capability Descriptors: a SuperSpeed USB descriptor and a USB 2.0 Extension descriptor.
Every SuperSpeed endpoint descriptor has a subordinate SuperSpeed endpoint companion descriptor.

A string descriptor can store text such as the vendor’s or device’s name or a serial number. On receiving a request for a
configuration descriptor, a device should return the configuration descriptor and all of the configuration’s interface,
endpoint, and other subordinate descriptors up to the requested number of bytes

The VBUS wire gives a constant 4.40 - 5.25 V supply to all attached devices. While USB supplies up to 5.25 V to devices, the data lines (D+ and D-) function at 3.3 V. T
The device responds with NAKs to show that it is not ready to send data when the host makes the request. The host continues to retry and the device responds with a data packet when it is
ready. The host then acknowledges the receipt of the data with an ACK handshake.

host sends the OUT token packet and a DATA0 packet but receives a NAK from the device. The host then retries to send the data. Notice that the data toggle bit has not changed since the
handshake was NAKed. With the next attempt to send data, the device responds with an ACK to indicate that the OUT transaction was successful
USB Endpoints:
During this enumeration sequence, a special set of endpoints are used for communication with the device. These special
endpoints, collectively known as the Control Endpoint or Endpoint 0, are defined as Endpoint 0 IN and Endpoint 0 OUT.
Even though Endpoint 0 IN and Endpoint 0 OUT are two endpoints, they look and act like one endpoint to the developer.
Every USB device must support Endpoint 0. For this reason, Endpoint 0 does not require a separate descriptor.
A simple design such as a mouse may need only one IN endpoint. More complex designs may need several data endpoints.
Low-Speed devices are limited to two endpoints. Endpoints use cyclic redundancy checks (CRCs) to detect errors in transactions.
• ULPI is an interface standard for high-speed USB 2.0 IP systems. It defines an interface between USB IP link controllers (as MUSBHDRC) and the PHYs or transceivers
that drive the actual bus.
- ULPI stands for UTMI+ low pin interface and is designed specifically to reduce the pin count of discrete high-speed USB PHYs. Pin count reductions minimize the cost and
footprint of the PHY chip on the PCB and reduce the number of pins dedicated to USB for the link controller. As a result of these capabilities, ULPI is becoming the new
interface standard in system/chip designers.
- Unlike full- and low-speed USB systems, which utilize serial interfaces, high-speed requires a parallel interface between the controller and PHY in order to run the bus at
480Mbps. This leads to a corresponding increase in complexity and pin count. ULPI keeps this down to only 8 or 12 signals because it combines just three control signals,
plus clock, with a 4- or 8-bit bi-directional data bus. The 4- and 8-bit modes are known as double (DDR) and single data rate (SDR) respectively.
- This bus is also used for USB packet transmission and for accessing register data in the ULPI PHY.

- ULPI is implemented as a wrapper around a UTMI+ PHY to reduce pin count in Hi-Speed USB systems.
UTMI+ and ULPI Standards
- ULPI is an extension of the UTMI+ PHY standard. Both standards are definitions of interfaces between USB link controllers and PHYs, however ULPI is specifically for
discrete PHY chips.
The UTMI standard (USB transceiver macrocell interface) was defined by Intel® for high-speed peripherals (USB v2.0). UTMI allows the peripheral to connect to a host
computer at either high- or full-speed (for compatibility with old PCs).
- The UTMI+ standard is an extension of the original UTMI that adds support for OTG and host controllers at all speeds.
Like UTMI+ for on-chip PHY implementations, the ULPI standard is proving to be a major benefit to USB implementers using discrete PHY chips. Both standards are managed
by the ULPI Working Group. Although ULPI is not a fully open specification, anyone is free to join and become a ULPI adopter. Sign up on the ULPI Working Group web site to
get a free copy of the specification.

•USB devices, such as a flash-drive, require an integrated

Function controller
•USB hosts, such as a PC, require an integrated Host controller
•Data transported at 480Mb/s(max) and compatible with USB
1.1
•USB 2.0 controllers are typical reusable soft digital silicon IP
blocks
•USB 2.0 PHYs are common Hard-IP blocks for on chip
integration
•Controllers require software stacks (host) and drivers (function)
 Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification supporting both
device and embedded host modes. There are two main hardware blocks required to interface with USB: a transceiver, also
known as a PHY (abbreviation for Physical Layer), and a Serial Interface Engine, also known as an SIE.
- The transceiver provides the hardware interface between the USB connector and the chip circuitry that controls USB
communication.
- The SIE is the core of the USB hardware. It performs many functions such as decoding and encoding the USB data, error
correction, bit stuffing, and signaling. SIEs can take many different forms.
SIE not regulated by the USB specification unlike transceivers. Some devices incorporate SIE that are more software based to
reduce cost, while other devices use more of a hardware-centric SIE.
USB Design Fundamentals
(10) Initialization: After the device is attached, the host will request the USB device
descriptor using the default device address zero. On successful transmission, it will
send a USB reset. After that, it sends an address to be configured for the device. All
further transactions will be directed to this device address. This address should be
configured in the Device Address field in the Device Address register (DADD.DADD)
and the Address Enable bit in DADD (DADD.ADDEN) should be written to one to
accept the communications directed to this address

(1) USB device mode supports 8 endpoint addresses.

- All endpoint addresses have one input and one output endpoint, for a total of 16 endpoints.
- Each endpoint is fully configurable in any of the four transfer types:
control, interrupt, bulk or isochronous.
- Internal SRAM is used to keep the configuration and data buffer for each endpoint.

(2) The USB host mode supports up to 8 pipes. The maximum data payload size is selectable up to 1023 bytes

(3) USB module has a built-in Direct Memory Access (DMA) and will read/write data from/to the system RAM when a USB
transaction takes place. No CPU or DMA Controller resources are required.

(4) USB supports double buffered communication. An endpoint can be configured for ping-pong operation.
When this is done the input and output endpoint with the same address are used in the same direction.
The CPU or DMA Controller can then read/write one data buffer while the USB module writes/reads from the other buffer

(5) For low power operation the USB module can put the microcontroller in any sleep mode when the USB bus is idle and a
suspend condition is given. Upon bus resume the USB module can wake the microcontroller from any sleep mode.

(6) Supports Link Power Management (LPM-L1) protocol.

On-chip transceivers with built-in pull-ups and pull-downs
On-Chip USB serial resistors
1kHz SOF clock available on external pin
(7) USB 2.0 Transceiver Macro-cell Interface (UTMI) requires an external 12MHz clock as a reference to its internal 480MHz phase
locked loop (PLL). The PLL is used to clock an internal digital locked loop (DLL) module to retrieve USB differential data at
480Mbit/s.

(8) The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow the USB data
rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8MHz

(9) Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter specifications
 USB Device USB Design USB Host USB PHY

USB OTG

USB Device
There is a built-in oscillator that generates a 12 MHz reference clock for the internal PLL of the USB 2.0 subsystem.
The USB2.0 subsystem peripheral bus clock is sourced from the system clock (SYSCLK
 USB 3.0 5 contacts instead of 4.
- Compatible with USB 2.0/1.0 and 10X faster
- USB 3.0 is full duplex Vs USB 2.0 is half-duplex
- 2 uni-directional data-paths (Rx & Tx)
- Power efficiency:
- Async notifications instead of continuous device poling.
- Link power management state b/w host & device. (IDLE, etc)
- Transition to low power states can be initiated by host or device.
- Suspend capabilities for portions of circuitry of functions not in use.
A 848MB file transferred in USB 2.0 takes 32.4 sec, same file takes only 12.97 sec using USB3.0

USB 3.0 cables have two additional shielded differential pairs (SDP) of wires for a total of 8 signal wires.
3.0 cables have to be shielded to prevent electromagnetic interference and maximize signal integrity. This
means the cables are thicker, heavier, less flexible and more expensive than 2.0 cables
1.High Speed bus protocols/Peripherals:

•Serial RapidIO
•PCI Express

•Ethernet, CAN
•SERCOM-
•RS485 and LIN-interfaces to SERCOM

Most of the high speed standard specifications provide several features for improving throughput, power optimization,
efficiency, and coherency.

1.Security features/modes:
ARM Basics