Real-Time Scheduling
Frank Drews
drews@ohio.edu
preemption
• Preemptive / non-preemptive
• Tick scheduling / event-driven scheduling
• Static (at design time) / dynamic (at run-time)
• Off-line (pre-computed schedule), on-line (scheduling
decision at runtime)
• Handle transient overloads
• Support Fault tolerance
Frank Drews Real-Time Systems
Task Assignment and Scheduling
• Cyclic executive scheduling (-> later)
• Cooperative scheduling
– scheduler relies on the current process to give up the CPU
before it can start the execution of another process
• A static priority-driven scheduler can preempt the
current process to start a new process. Priorities are
set pre-execution
– E.g., Rate-monotonic scheduling (RMS), Deadline
Monotonic scheduling (DM)
• A dynamic priority-driven scheduler can assign, and
possibly also redefine, process priorities at run-time.
– E.g., Earliest Deadline First (EDF), Least Laxity First (LLF)
Frank Drews Real-Time Systems
Simple Process Model
• Fixed set of processes (tasks)
• Processes are periodic, with known periods
• Processes are independent of each other
• System overheads, context switches etc, are
ignored (zero cost)
• Processes have a deadline equal to their period
– i.e., each process must complete before its next
release
• Processes have fixed worst-case execution time
(WCET)
Frank Drews Real-Time Systems
Terminology: Temporal Scope of a
Task
• C - Worst-case execution time of the task
• D - Deadline of tasks, latest time by which the task
should be complete
• R - Release time
• n - Number of tasks in the system
• - Priority of the task
• P - Minimum inter-arrival time (period) of the task
– Periodic: inter-arrival time is fixed
– Sporadic: minimum inter-arrival time
– Aperiodic: random distribution of inter-arrival times
• J - Release jitter of a process
E 100 2
T1 (4,1)
T2 (5,2)
T3 (7,2)
0 5 10 15
response time of job J 3,1
Frank Drews Real-Time Systems
Utilization
Ci
Ui Utilizatio n of task Ti
Pi
2
Example : U 2 0.4
5
T1 (4,1)
T2 (5,2)
T3 (7,2)
0 5 10 15
I1
• Two tasks Ti , T j are in phase if I i I j
Tn
T1
Tn
In
T1
Frank Drews Ii Real-Time Systems
Proof of Lemma
• Observation: Increasing the phase of task Ti may decrease the
response time of task Tn (but will never increase it).
Tn
In
T1
Ii
Tn
T1
t t
• w2 (t ) C2 e1 2 1
p1 4
t t t t
• w3 (t ) C3 e1 e2 2 1 2
p1 p2 4 5
k 1 pk
2. Check whether the inequality wi (t ) t is satisfied for
values of t that are equal to
t j pk ; k 1,2,, i; j 1,2,, pi pk
T2 (5,2)
T3 (7,2)
0 5 10 15
Frank Drews Real-Time Systems
EDF: Schedulability Test
Theorem (Utilization-based Schedulability Test):
A task set T1 , T2 ,, Tn with Di Pi is schedulable by the
earliest deadline first (EDF) scheduling algorithm if
n
Ci
1
i 1 Di
Ti J i ,c
Ri ,c Ci
…
Ii Ri ,c
Tk
…
Ik
Tn
0 In 5 10 15
t
J i ,c misses its deadline at t any current job with deadline after t is not given any CPU time to
execute before t . The total CPU time to complete all the jobs with deadlines at or before t exceeds
the total time : t
(t I i ) Ci t Ik
t Ck
pi k i pk
Ti J i ,c
Ri ,c Ci
…
Ii Ri ,c
Tk
…
Ik
Tn
0 In 5 10 15
t
(t I i ) Ci t Ik Ci Ck n n
t Ck t t t U k U k 1
pi k i pk Pi k i Pk i 1` i 1`
Ti J i ,c
Ri ,c I i' Ri ,c Ci
…
Ii
Tk
…
Ik I k'
Tn
0 In 5 10 t 1 15
t
Let T be the set of all tasks and T' the subset of tasks containing all the tasks with release time before Ri ,c and
deadline after t . Some processor time might have been given to these tasks before t . Let t 1 be the end of the
latest time interval that is used to execute some tasks in T'. We now look at the segment starting from t 1. In this
'
segment none of the tasks with deadlines after t is given any CPU time. Let I k denote the release time of the
first job of task Tk in T T' in this segment. Because J i ,c misses its deadline at t , we must have
(t t 1 I i' ) Ci t t 1 I k' Ci Ck n
C
t t 1
k C (t t )
1 i 1
pi Tk T T' pk Pi Tk T T'
Pk i 1 Pi
2 possible solutions:
• Cycle stealing
– The DMA steals a CPU memory cycle to execute a data transfer
– The CPU waits until the transfer is completed
– Source of non-determinism!
• Time-slice method
– Each memory cycle is split in two adjacent time slots
• One for the CPU
• One for the DMA
– More costly, but more predictable!
Frank Drews Real-Time Systems
Achieving Predictability: Cache
To obtain a high predictability it is better to
have processors without cache
Source of non-determinism
• cache miss vs. cache hit
• writing vs. reading
Deadlocks
RM
For Us=0, reduces to U
• Comparing PS and DS