Basic Compensation Principle of D-

STATCOM

• 1. The converter (power circuit)

• 2. The D-STATCOM controller

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 INDIAN INSTITUTE OF TECHNOLOGY ROORKEE

Perform Investigation of Multilevel Inverter based STATCOM for

Reactive Power control
By
MUTTAVARAPU SIDDHARDHA
17527010

Under the guidance of

Dr. Pramod Agarwal

Department of Electrical Engineering

IIT Roorkee
INTRODUCTION

 What is STATCOM?
 STATCOM is a GTO(Gate turn off) based
compensator .

 What is need of Compensator

 Power System Model

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Active Power

𝑽𝒔 𝑽𝑳
𝑷= 𝒔𝒊𝒏 𝜹
𝑿
 Active power Flow From Leading Voltage to Lagging Voltage

Reactive Power

𝑽𝑳 (𝑽𝒔 − 𝑽𝑳 )
𝑸=
𝑿

 Reactive flow depends on difference of voltage magnitude i.e.,

Higher voltage to lower voltage

𝑸𝑿
𝑽𝑳 ≈ 𝑽𝒔 −
𝑽𝒔

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STATCOM in Distribution Systems

 Unity power factor.

 Suppression of harmonics in loads
 Voltage regulation
 Cancellation of the effect of unbalance loads

 All of these objectives are not necessarily met by a typical

STATCOM. The required STATCOM should be designed in view
of the needs of compensation parameters.

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BENEFITS OF POWER FACTOR CORRECTION

• INCREASED LOAD CARRYING CAPABILITIES IN

EXISTING CIRCUITS
• REDUCED DEMAND CHARGES
• IMPROVED VOLTAGE
• REDUCED POWER SYSTEM LOSSES

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Basic Compensation Principle of D-
STATCOM

• 1. The converter (power circuit)

• 2. The D-STATCOM controller

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D-STATCOM connected to the 3P3W distribution system for reactive
power compensation

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Cascaded H-Bridge Topology for D-
STATCOM
• Almost sinusoidal waveform voltage
• Expand to higher number of levels with easy construction,
flexibility in converter design.
• Line-frequency transformer.

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Cascaded H-Bridge Topology for D-STATCOM

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SPWM Technique for VSC

sinusoidal waves are called reference signal

120𝑜 phase difference with each other
carrier triangular wave is usually a high frequency (10KHz)
wave

• 1. The converter (power circuit)

• 2. The D-STATCOM controller

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PWM Technique for CHB

• multilevel converter with m voltage levels, requires (m-1)

triangular carrier signals
• phase shift (𝜑𝑐𝑟 ) between any two adjacent carrier signals,
given by
3600
𝜑𝑐𝑟 =
𝑚−1
• When the modulating signal is more than the carrier signal,
the upper switch is on and when it is less than carrier signal,
the lower switch is on.

• maintains a uniform power distribution among H-bridge cells

which naturally balances the capacitor voltages

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3phase Five level CHB Multilevel converter

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Gate Signals for Phase A Branch of CHB

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Comparing THD of VSC vs CHB

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Design of 3-phase 415V 12 KVA D-STATCOM
for VSC and five level CHB
• Selection of interface inductor and DC capacitance

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A.Design of VSC

1) dc Capacitor Voltage:
greater than twice of the peak of the phase voltage of the system .\
2.Vll
• Vdc =
3m
• Thus,Vdc is selected as 700 V for a Vll of 415 V.
• 2) dc Bus Capacitor:
• depends on the instantaneous energy available to the DSTATCOM
during transients.The principle of energy conservation is applied as
1 2 2
• C Vdc − Vdc1 = 3V aI t
2 dc
• Considering the minimum voltage level of dc bus,Vdc1 =690V,
Vdc =700V, V =239.6V, I=27.82A, t =350us,a=1.2.the Calculated
value of Cdc is approximately 3000 µF.

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3) ac Inductor
Lf = ( 3mVdc )
ൗ(12afsicr(p−p) )
Considering icr,p−p = 5%,fs =10kHz, m=1, Vdc = 700 and a=1.2,
the Lf value is approximately 2.5 mH.

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1) dc Capacitor Voltage:
greater than twice of the peak of the phase voltage of the system .\
𝑘Vll
• Vdc =
3𝑁
• Thus,Vdc is selected as 240V for a Vll of 415 V
• 2) dc Bus Capacitor:
• depends on the instantaneous energy available to the DSTATCOM
during transients.The principle of energy conservation is applied as
1 2 2
• C Vdc − Vdc1 = V aI t
2 dc
• Considering the minimum voltage level of dc bus, Vdc,min
=230V, Vdc =240V, V =119.8, I=16.69A, t =350us,a=1.2.the
Calculated value of Cdc is approximately 373.23µF.
•
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3) ac Inductor
(mVc )
Lf = ൘(12af i )
c cr(p−p)
Considering 5% peak-to-peak current ripple, the switching frequency
of the converter (2Nfcr) = 2.2. 2 kHz = 8 kHz, amplitude modulation
index (m) = 1, phase-to neutral cluster voltage of the converter (Vc) =
N´ Vref,i = 480Vand overload factor (a) = 1.2,the value is calculated
to be 1.8 mH.

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 Equivalent circuit of STATCOM system

• According to equivalent circuit shown

𝑑𝐼𝑠
• 𝐿𝑓 + 𝑅𝑓 𝐼𝑠 = 𝑉𝑔 − 𝑉𝑠
𝑑𝑡
• In d-q synchronous reference frame , the mathematical expression
of the STATCOM is shown as follows:
𝑑 𝑖𝑠𝑑 𝑖𝑠𝑑 𝑉𝑔𝑑 𝑉𝑠𝑑 𝑖𝑠𝑞
• 𝐿𝑓 + 𝑅𝑓 = − 𝑉𝑠𝑞
+ 𝑤𝐿𝑓
𝑑𝑡 𝑖𝑠𝑞 𝑖𝑠𝑞 𝑉𝑔𝑞 −𝑖𝑠𝑑

𝑉𝑔𝑑 1
• 𝑉𝑔𝑞
= 𝑉𝑔 0
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• Decoupled currents control Strategy:
𝑅𝑓
𝑑 𝑖𝑠𝑑 − 0 𝑖𝑠𝑑 1 𝑉𝑠𝑑 −𝑉𝑔+𝑤𝐿𝑓 𝑖𝑠𝑞
• = 𝐿𝑓
𝑅𝑓 + (3.11)
𝑑𝑡 𝑖𝑠𝑞 0 −𝐿 𝑖𝑠𝑞 𝐿𝑓 𝑉𝑠𝑞 −𝑤𝐿𝑓 𝑖𝑠𝑑
𝑓

• After introducing two intermediate variables 𝑥1 , 𝑥2

• 𝑥1 = 𝑉𝑠𝑑 − 𝑉𝑔 + 𝑤𝐿𝑓 𝑖𝑠𝑞 (3.12)
• 𝑥2 = 𝑉𝑠𝑞 − 𝑤𝐿𝑓 𝑖𝑠𝑑 (3.13)
𝑅𝑓
𝑑 𝑖𝑠𝑑 − 0 𝑖𝑠𝑑 1 𝑥1
• = 𝐿𝑓
𝑅𝑓 + (3.14
𝑑𝑡 𝑖𝑠𝑞 0 −𝐿 𝑖𝑠𝑞 𝐿𝑓 𝑥2
𝑓

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• Variables 𝑥1 , 𝑥2 can be obtained
∗ ∗
• 𝑥1 = 𝑘𝑝 𝑖𝑠𝑑 − 𝑖𝑠𝑑 + ‫𝑑𝑠𝑖 ׬‬ − 𝑖𝑠𝑑
• ∗ −𝑖
𝑥2 = 𝑘𝑝 𝑖𝑠𝑞 + 𝑘 𝑖 ∗ −𝑖
𝑠𝑞 𝑖 ‫׬‬ 𝑠𝑞 𝑠𝑞
• The d-axis and q-axis reference voltage equations of the
STATCOM are
∗
• 𝑉𝑠𝑑 = 𝑥1 +𝑉𝑔 − 𝑤𝐿𝑓 𝑖𝑠𝑞
∗
• 𝑉𝑠𝑞 = 𝑥2 + 𝑤𝐿𝑓 𝑖𝑠𝑑 Obtain d-q
reference voltages are transformed into abc frame and act as a
modulation signal for VSC and CHB

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Controller for VSC

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Controller for CHB

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current loop
1
𝐺𝑐 (𝑠)∗𝑅 +𝐿 𝑠
𝐼(𝑠) 𝑓 𝑓
• = 𝐺 (𝑠)
𝐼 ∗ (𝑠) 1+𝑅 𝑐+𝐿 𝑠
𝑓 𝑓

• closed-loop transfer function of the current loop would appear to

be a 1st-order system (i.e)
𝐼(𝑠) 1
• =
𝐼 ∗ (𝑠) 1+𝑠𝑇
𝐼(𝑠) 1/𝑠𝑇
• =
𝐼 ∗ (𝑠) 1+1/𝑠𝑇

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• Where T is determined according to the time-domain objective.
𝐺𝑐 (𝑠) 1
=
𝑅𝑓 +𝐿𝑓 𝑠 𝑠𝑇
𝐿𝑓 𝑅𝑓/𝑇
𝐺𝑐 𝑠 = +
𝑇 𝑠
• For VSC ,by considering 𝑅𝑓 = 0.1, 𝐿𝑓 = 2.5mH and T=0.0001sec,
the value of Kp and Ki are 75 and 1000 repectively.
• For CHB ,by considering 𝑅𝑓 = 0.1, 𝐿𝑓 = 1.8mH and
T=0.0001sec, the value of Kp and Ki are 40 and 1000 repectively

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• The dynamics of DC-capacitor is expressed as :
1
• 𝑉𝑑𝑐 = ‫𝑡𝑑 𝑐𝑑𝑖 ׬‬ (3.26)
𝑐
• Appling Laplace on both sides on equation(3.16)
𝐼𝑑𝑐 (𝑠)
• 𝑉𝑑𝑐 (𝑠) =
𝐶𝑠
• Power balance equation :
• 𝑉𝑑𝑐 𝐼𝑑𝑐 =3 𝑉𝑟𝑚𝑠 * 𝐼𝑟𝑚𝑠
2
• 𝐼𝑟𝑚𝑠 = 𝐼
3 𝑑

𝐼𝑑𝑐 𝑉𝑙𝑙 2
• 𝑘= = ∗
𝐼𝑑 𝑉𝑑𝑐 3

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• closed-loop transfer function can be written as
𝐾
𝑉𝑑𝑐 (𝑠) 𝐺𝑐𝑣 (𝑠)∗ 𝑠1
• =
𝑉𝑑𝑐 ∗ (𝑠) 𝐾
1+𝐺𝑐𝑣 (𝑠)∗ 1
𝑠
𝑉𝑑𝑐 (𝑠) 1
• =
𝑉𝑑𝑐 ∗ (𝑠) 1+𝑠𝑇
Where T is determined according to the time-domain objective.
𝐾1 1
• 𝐺𝑐𝑣 (𝑠) ∗ =
𝑠 𝑠𝑇
1
• 𝐺𝑐𝑣 𝑠 =
𝑇𝐾1
For VSC ,by considering 𝑉𝑙𝑙 = 415𝑉, 𝑉𝑑𝑐 = 700𝑉 𝑎𝑛𝑑 𝐶 = 3000𝑢𝐹
and T=0.01sec, the value of Kp and Ki are 0.8 and 0 respectively.
For CHB,by considering 𝑉𝑙𝑙 = 415𝑉, 𝑉𝑑𝑐 = 240𝑉 𝑎𝑛𝑑 𝐶 = 500𝑢𝐹
and T=0.01sec, the value of Kp and Ki are 0.01 and 0 respectively
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Simulation result of source voltage and source current operating at UPF after 0.5sec and
STATCOM Current

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Conclusion :

• With the increase of switching frequency of CHB multi level

inverter , we can reduce the size of coupling inductor to a
greater extent as Lf is inversely proportional to the switching
frequency The value of capacitance used and operating
voltage is very less when compare to VSC topology an.
Voltage THD at the load bus can be maintained below the
standards using CBH and faster response can be achieved.
• In the next semester,performance analysis of two topologies
for non linear load will be studied and a prototype of three
level cascaded multilevel inverter will be developed by
adopting current decoupling scheme using OPAL-RT.

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