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ADC Design and Custom Layout

Jaeduk Han
2017. 3. 9

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I am from the other side

High performance,
Wired,
Low power means 100mW
• But we are on the same page
– Power/datarate/noise/link budget
– Taping out soon & behind schedule

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I’m an (1-bit) ADC expert!

• Sorry it’s my first time to build a ‘real’ ADC

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Agenda
• My ADC story
• Layout in <28nm

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Message from your advisor

ADC generator is
your last phd
project!

• What’s the spec?

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Think about major spec items
• Signal range (Vin) : How large your input signal is?
• Sampling rate (Fs) : How many samples per second?
• Bandwidth (Fb) : What’s your frequency range of interest?
– Fb < Fs/2 because you can’t go higher than Nyquist
• Number of bits (Nbit) : How many output bits?
• Effect number of bits (ENOB) : Nbit corresponding to the ideal
ADC (only quantization noise exists)
– ENOB < Nbit because you always got some distortions and noise
– Some ‘fraction’ of bit loss from sampling noise, comparator noise,
comparator kickback, timing mismatches, nonlinear distortions, bandwidth
limitations and ‘redundancy’ and so on..

• VDD, area/power budget, corner specs …

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Get numbers
• Signal range (Vin) = 300mV
• Sampling rate (Fs) = 40GS/s
• Bandwidth (Fb) ~= 20GHz
• Number of bits (Nbit) = 8
• Effect number of bits (ENOB) ~= 6

• The first thing you should do after getting the spec item is

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Negotiate
• Signal range (Vin) = 300mV
• Sampling rate (Fs) = 40GS/s 10GS/s
• Bandwidth (Fb) ~= 20GHz 10GHz
• Number of bits (Nbit) = 8 6
• Effect number of bits (ENOB) ~= 8 4

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They’ll do the same thing
• Signal range (Vin) = 300mV
• Sampling rate (Fs) = 40GS/s 10GS/s
• Bandwidth (Fb) ~= 20GHz 10GHz
• Number of bits (Nbit) = 8 6 8 9
• Effect number of bits (ENOB) ~= 8 4 6

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Architect
• System-level decisions
– Differential vs. single ended
– Flash, pipeline, SAR, oversampling
• SAR is very popular these days.. (for 10MS/s~40GS/s, 8bit to 12bits)
– Calibration

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Keep architecting
• Time interleaving, pipelining, oversampling
– Many combinations of these stuff; find a new one and write a paper

• Synchronous SAR/asynchronous SAR


– External clocked vs. self-timed
– Very debatable issue
– For synchronous, how many cycles will be assigned to the actual sampling?

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Draw high level picture
• Incorporates all system level decision we’ve made

8-way, 9bit, 9bit to 8bit


9:36 DES
Frontend 9.6GS/s digital
x8
TISAR ADC calibration

• SubADC level picture

Sample and Async clock


Comparator
hold gen.

Output
Cap DAC Cap Drv SAR FSM
retimer

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Move to circuit level
• Sampling frontend, capdac, comparator, cap drivers are main
concerns
• Other blocks are mostly custom-digital

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Sampling frontend
• Capacitor
– KT/C noise, input noise
– Depends on how many ‘bits’ you assigned for noise
• Switch
– Simple NMOS switch is good for small Vin (may lead
to higher C)
– Higher VDD / bootstrapping / bottom plate sampling
are used for >8bits
• Check BW, noise, nonlinearity
Signal
– BW: AC (actually should run tran sim) buffer
– Noise: noise or PSS
– Nonlinearity: measure DC resistance, run tran sim Clock
with sine waves and do FFT buffer
– Pick C for noise, pick R for BW/lin., pick buffer sizes
for driving ‘R’ (Trf matters)

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CapDAC
• MOM capacitor (high density, low variation)
• Do not use M1/M2/M3 (high ground parasitic)
– Maybe okay if you can calibrate gain
• Dummy block layer need
Top plate or
• Parasitic extraction is a must bottom plate?
• >2fF is pretty reliable

Do you have a
‘reference’
with current
driving
capability?

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Cap driver
• Basically inverter or transmission gate or single mos gate
– You need to think about the reference stuff
• Make sure settling time is small enough (otherwise nonlinear
distortion)

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Comparator
• StrongArm – high max. freq
• Double tail – low noise (may lead to low power)
• Differences are not ‘very’ significant
• Check clock-q, input-referred noise
– Clock-q: put a very small input (less than LSB/2) and run tran-sim
• Hysteresis effect
– Input-referred noise: Run transim with input voltage sweep. Check error-
rate
• Most comparators have
a limited input range!!

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SAR Logic
• Asynchronous SAR requires internal clock generator
• Your fT is very high (>> 100GHz), so shouldn’t be a big problem
• Stitching standard cells is actually a good idea
– Don’t forget to add tap cells

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Verify
• INL/DNL
– Sweep Vin @ DC, measure the output code, calculate INL/DNL

• ENOB
– Coherent sampling or windowing
– Run many cycles (>2^n_bits) to get a good quantization noise distributions
– Use MATLAB to do FFT
– Sweep freq to low freq to fs/2
• It will take a long time

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Agenda
• My ADC story
• Layout in <28nm

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Layout in 28nm
• Unidirectional poly
– you can’t rotate your layout
– No poly routing
• More restricted routing rules
– Better to stick with some constant routing grids
– Strict minimum area rules, allow some metal traces per layer
– Bending metal is hard
• My suggestion is M1 for vertical, M2 for horizontal, M3 for vertical, and so on
• Taps are not integrated in standard cells
• Electromigration and IR drop
– One suggestion: avoid the use of very large width per finger (~400nm is
okay) to limit current density/finger
– Maybe it’s not a big problem for low power circuits?

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Layout in 28nm FDSOI
• I have zero experience on SOI process

• I’ve heard those things,


– Digital cells are very fast
– For analog devices, you may want to do body biasing, which slows down
your device and is associated complex design rules
– Still some hysteresis effects on VT? Need to double check

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Template and grid based layout
• Adopted to Berkeley Analog Generator for 16nm layout
generation to abstract extremely complex design rules

Place(‘nmos’, [0,0])
Route(M2, ‘pmos0’, D[0,0],
‘pmos1’, D[0,0])

*freePDK45 used
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Template and grid based layout
• Then the layout generation becomes place and route of cells
• If you are interested, we can work together in summer
• We can play a similar trick in manual flow

Serializer generation ucb-art.github.io/laygo/


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1. Define placement and route grid
• Half of contacted-poly-pitch and/or minimum route pitch of
mid-layer metals (eg. M4) is a good number for grid resolution
• Make sizes of your primitive cells (MOS, TAP, RES) to be
multiples of the grid resolution
• Then the layout becomes placement and route of devices on
grid

Inverter layout in 2 mins

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2. Make your custom palette
• Make a layout view called ‘PALETTE’, put all your devices, vias,
routes on grid
• When you make a new layout, copy the view and start from it

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3. Load helper functions
• Copy ~jdhan/jdskill to your cadence directory
• In virtuoso window, type load “jdskill/skillload.il”
• This gives bunch of magic functions and maps them to shortcuts

– Shift +  : move selected obj by ‘rw’


– Ctrl + c : copy the select obj at the same location
– Ctrl +  (rect) : increase size in specified direction by ‘rw’
– Alt +  (rect) : decrease size in specified direction by ‘rw’
– Ctrl +  (mosaic) : increase/decrease row/col by 1
– Ctrl + v, type rw=XX, press enter : set rw

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4. Use helper functions
• If you use helper functions properly with a proper value of rw,
you don’t need to be bothered by DRC and fine physical grids
– You can do a similar thing by setting snap spacing in Options->Display
• The helper functions are documented well
– In Korean, sorry! (made in 2009)
– Run jdskill/showlist and use google translate

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Demo) differential input stage
• This really helped me to finish stuff on time…

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