DESIGN FOR 4-BIT VEDIC MULTIPLIER USING

VHDL MODULE
SREYAS INSTITUTE OF ENGINEERING & TECHNOLOGY
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DESIGN OF 4-BIT VEDIC MULTIPLIER USING VHDL MODULE

Under the Guidance of

Mr.SK.Aqeel

Presented by
P.Shashank(16VE1A04L2)
B.Avinash(16VE1A04H0)
A.Karthik Goud(16VE1A04N4)
 INTRODUCTION
• Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC)
by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex
semiconductor and communication technologies were being developed. The microprocessor is a
VLSI device.
• The use of Vedic mathematics lies in the fact that it reduces the typical calculations
in conventional mathematics to very simple ones. This is so because the Vedic formulae are
claimed to be based on the natural principles on which the human mind works. Vedic
Mathematics is a methodology of arithmetic rules that allow more efficient speed
implementation.
• Behavioral description is then created to analyze the design in terms of functionality,
performance, compliance to given standards, and other specifications.
• Vedic mathematics is based on 16 Sutras (or aphorisms) dealing with various
branches of mathematics like arithmetic, algebra, geometry etc.These sutras are meant for faster
mental calculation .These Sutras along with their brief meanings are enlisted below alphabetically.
 VLSI DESIGN FLOW
• Behavioral description is then created to analyze the
design in terms of functionality, performance, compliance to given
standards, and other specifications.
• RTL description is done using HDLs. This RTL description
is simulated to test functionality. From here onwards we need the
help of EDA tools.
• RTL description is then converted to a gate-level netlist
using logic synthesis tools. A gatelevel netlist is a description of the
circuit in terms of gates and connections between them, which are
made in such a way that they meet the timing, power and area
specifications.
 SYSTEM ANALYSIS
Multipliers
• In microprocessors multiplication operation is performed in a variety of
forms in hardware and software depending on the cost and transistor budget allocated
for this particular operation. In the beginning stages of computer development of any
complex operation was usually programmed in software or coded in the micro-code of
the machine. Design developed for a multiplier which generates the product of two
numbers using purely combinational logic Today it is more likely to find full hardware
implementation of the multiplication in order to satisfy growing demand for speed and
due to the decreasing cost of hardware. The execution time of most DSP algorithms is
dependent on its multipliers, and hence need for high speed multiplier arises.
• Array multiplier is an efficient layout of a combinational multiplier. The
two's complement multiplication is converted to an equivalent parallel array addition
problem in which each partial product bit is the AND of a multiplier bit and a
multiplicand bit, and the signs of all the partial product bits are positive.In array
multiplier, consider two binary numbers A and B, of m and n bits.
BLOCK DIAGRAM FOR 4-BIT VEDIC MULTIPLIER
4-BIT RIPPLE
CARRY ADDER

• Ripple Carry Adder adds 2 n-bit number plus

carry input and gives n-bit sum and a carry output. The Main
operation of Ripple Carry Adder is it ripple the each carry
output to carry input of next single bit addition. Each single
bit addition is performed with full Adder operation (A, B, Cin)
input and (Sum, Cout) output
RTL SCHEMATIC FOR 4-BIT VEDIC MULTIPLIER
 APPLICATIONS
• Multiplier based on Vedic Mathematics is one of the fast
and low power multiplier. Employing this technique in the
computation algorithms will reduce the complexity, execution time,
power etc. This vedic based multiplier is compared with
binary multiplier(partial products method).
• A High Speed And Low Area Vedic Multiplier for
Efficient Implementation of Faster Realtime Hardware Image
Processing.
• Implementation of Vedic Multiplier in Image
Compression , Using Discrete Cosine Algorithm.
TIMING DIAGRAM
 CONCLUSION
• In this paper, an attempt is made to explore the
design space for optimal implementation of Vedic multiplier using
• VHDL. The time taken for multiplication operation is
reduced by employing the Vedic algorithms. Here integrated Vedic
multiplier architecture is proposed for further reduction in time.
Depending on the inputs, the better sutra is selected by the
architecture itself. Future work includes the integration of the divider
block, multiply and accumulate (MAC) unit, thereby making it into a
Vedic Arithmetic and Logical unit (ALU).
 REFERENCES
• J. S. S. B. K. T. Maharaja, Vedic mathematics, Delhi: Motilal
Banarsidass Publishers Pvt Ltd,(2010).
• Pavan Kumar,A.Radhika, “FPGA Implementation of high speed 8-bit
Vedic multiplier using barrel shifter”, 2013 IEEE Paper
• M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar “High Speed ASIC
Design of Complex Multiplier using Vedic
• Mathematics”International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 Vol. 3, Issue 1, January
• -February 2013, pp.1079-1084