VHDL

Exercise
• Lets examine how the event time simulation
proceeds for the previous example of an SR
latch. The following is a schematic version of
the SR latch.
 Exercise
• We might build an entity like the one that follows.

entity latch is
port (s,r : in bit;
q,nq : out bit
);
end latch;
architecture dataflow of latch is
begin
q<=r nor nq;
nq<=s nor q;
end dataflow;
 SR Latch
• The entity describes the interface to the
design
• There are four signals s,r,q, and nq that are
accessible externally to the design
• VHDL data type bit, which can represent two
level logic values.
• The architecture part describes the internal
operation of the design
 SR Latch
• In the data flow approach we indicated how
data flows from the inputs to the outputs.
• In VHDL this is accomplished with the signal
assignment statement.
• The example architecture consists of two
signal assignment statements.
 SR Latch
• A signal assignment statement describes how data
flows from the signals on the right side of the <=
operator to the signal on the left side.
• The first signal assignment in the example tells us that
the data coming from signals r and nq flow through a
nor gate to determine the value of the signal q.
• The nor represents a built-in component called an
operator, because it operates on some data to produce
new data.
• The second signal assignment, similar to the first,
indicates that the signal nq is produced from data (s
and q) flowing through (or processed by) the nor
operator.
 SR Latch
• The right side of the <= operator is called an
expression.
• The value of the expression is determined by
evaluating the expression.
• Evaluating the expression is performed by
substituting the values of the signals in the
expression and computing the result of each
operator in the expression.
 SR Latch
• The internal operation of the latch was
essentially captured using the following two
statements.
q<=r nor nq;
nq<=s nor q;
 SR Latch
• The internal operation of the latch was
essentially captured using the following two
statements.
q<=r nor nq;
nq<=s nor q;
 SR Latch
• Since data flows from r and nq to q, we say
that q depends on r and nq. In general, given
any signal assignment statement, the signal on
the left side of the <= operator depends on all
the signals appearing on the right side.
• If a signal depends on another signal that an
event has occurred on, then the expression in
the signal assignment is re-evaluated.
 SR Latch
• If the result of the evaluation is different than
the current value of the signal, an event will
be scheduled (added to the list of events to be
processed) to update the signal with the new
value.
• Thus, if an event occurs on r or nq, then the
nor operator is evaluated, and if the result is
different than the current value of q, then an
event will be scheduled to update q.
 SR Latch
• Suppose at a particular moment during a
simulation of the SR latch example, the values of
the signals are s='0',r='0', q='1', and nq='0'.
• Now suppose the value of the signal r changes
(due to some event external to the design) to the
value '1'.
• Since q depends on r, we must re-evaluate the
expression r nor nq, which now evaluates to '0'.
Since the value of q must be changed to '0', a
new event will be scheduled on the signal q.
 SR Latch
• During the next round the event scheduled for q is
processed and q's value is updated to be '0'. Also, since
nq depends on q, the expression s nor q must be re-
evaluated. The result of the expression is '1', so an
event is scheduled to update the value of nq.
• During the next round, when the event on nq is
processed, the expression for q will be evaluated again
because it depends on nq.
• However, the result of the expression will be '0' and no
new event will be scheduled because q is already '0'.
Since, no new events were scheduled, there are no
more events that will occur internally to the latch.
 SR Latch
• Now, suppose an external event causes r to
return to the value '0'. Since q depends on r, r nor
nq is evaluated again.
• The result of this expression is '0' and q is already
'0', so no events are scheduled. As you can see,
this correctly models the SR latch as we would
expect.
• When the signal r became active ('1') the output
of the latch was reset, and when r became
inactive ('0') the output remained unchanged.
 SR Latch
• The simulation rounds can be summarized as follows.

start : r='0',s='0',q='1',nq='0'
round 1 : r='1',s='0',q='1',nq='0',
-- The value '0' is scheduled on q.
round 2 : r='1',s='0',q='0',nq='0',
--The value '1' is scheduled on nq.
round 3 : r='1',s='0',q='0',nq='1',
--No new events are scheduled.
round 4 : r='0',s='0',q='0',nq='1',
--No new events are scheduled.