Department of Electrical and computer Engineering

College of Engineering and Technology

Jimma University
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 Microprocessor is useless or cannot do anything
without peripherals
 It needs peripherals (Input or output devices )
 Input devices
 Keyboard
 Mouse
 Switch etc.
 Output devices
 Monitor
 Printer
 Motor
 LED etc

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 Butthe microprocessor and the peripherals
are mostly incompatible
 Have different speed
 Peripherals are slower
 Different data format
 Microprocessor work on digital data
 Peripherals mostly work on analogue data
 Serial vss. Parallel
 Electrical value incompatibility
 So
there is a need for making them
compatible in
 Speed or
 Data format
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 I/O can be either:
- Isolated, or
- Memory mapped
 Isolated I/O: uses the dedicated I/O instructions (IN,
OUT) and has its own address space for I/O ports
(0000H-FFFFH)- isolated from the memory address
space
 Memory mapped I/O:
 uses memory reference instructions , e.g. MOV, and
 It address space is shared between memory and I/O
 Isolated I/O
 I/O locations are separate from memory locations
 Special I/O instructions are used
 The most common technique for Intel microprocessors
 Advantage: More space for memory
 Disadvantage: Additional control signals (IO/M) and instructions
increase complexity
 Memory-mapped I/O
 I/O devices are treated as memory locations in the memory map
 Any memory transfer instruction can be used (MOV, LDR, STR etc)
 Advantages: Simpler decoding circuitry, no special instructions
required
 Disadvantage: A portion of the memory system is used as the I/O
map, reducing the memory available to applications

ACOE255 7
Memory and I/O address
Maps for the 8086/8088
Memory: I/O Port specified
MOV in DX, either explicitly or imp

a. Isolated I/O I/O:

Using dedicated I/O IN 64 K
instructions e.g. IN, OUT I/O bytes
00FF

Port specified immediat

as a byte in the I/O inst

MOV
Range of memory addresses
b. Memory-mapped I/O assigned for I/O transfers
Using ordinary memory
transfer instructions Memory
e.g. MOV
 The basic output port writes data from the mP data bus
to an output port whenever the mP executes the correct
OUT instruction with the correct I/O port address
 Must latch the processor data put on the bus during the
I/O instruction to make it available indefinitely for the
port
 8-LED’s
 Loses the data if not latched
 Solution?
 Use a register chip and an address decoder such
that the LED’s will not only respond to the
command out and a specific address (let’s
assume that the address is F000) but will also
latch the data
 Just as you can write to a memory chip using the
command mov [bx],al
 You can output to output device using the
command out dx,al
 Basic 8-bit Output Interface:
Controls 8 LEDs (1: OFF, 0: ON)

From mP
Edge-triggered
latch

No HiZ. OE
Data is latched and remains here until the next OUT
O/P always
enabled instruction to this port is executed
The SEL is generated (for + ive edge triggering) by decoding:
- The address for the I/O port
- The I/O WRITE operation
 The basic input port connects an external set of bits to
the mP data bus whenever the mP executes the correct
IN instruction with the correct I/O port address
 External device puts data on the mP data bus
 Must include a 3-state (Tri-State) buffer to limit
access to the processor data bus to the duration of
executing the I/O instruction only
 Basic 8-bit Input Interface:
Reads the status of 8 toggle
Switches (a byte read)
Pull-up
Resistors To mP
Gate

0 1
Toggle switches
3-state buffer
The SEL signal is generated (active low)
By decoding:
- The address for the I/O port
- The I/O READ operation
 likea memory chip, you can read from an
input device
 Youcan read from a memory chip using the
command mov al, [bx]
 Youcan read from an input device using the
command in al, dx
 The 82C55 is a popular interfacing
component, that can interface any
TTL-compatible I/O device to a
microprocessor.
 It is used to interface to the
keyboard and a parallel printer port
in PCs
 PPI has 24 pins for I/O that are
programmable in groups of 12 pins
and has three distinct modes of
operation.
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 Mode 0
 Basic I/O
 Mode 1
 Strobe I/O
 Mode 2
 Bi-Dir Bus
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This functional configuration
provides simple input and
output operations for each of
the three ports.
No “handshaking” is
required, data is simply
written to or read from a
specified port.
This functional configuration
provides a means for transferring
I/O data to or from a specified port
in conjunction with strobes or
“handshaking” signals.
In mode 1, Port A and Port B use the
lines on Port C to generate or
accept these “handshaking”
signals
 Two Groups (Group A and Group B).
 Each group contains one 8-bit data port
and one 4-bit control/data port.
 The 8-bit data port can be either input or
output
 Both inputs and outputs are latched.
 The 4-bit port C is used for control and
status of the 8-bit data port.
Signal definitions for Mode 1 Strobe Input
 ~STB : The strobe input loads data into the port
latch on a 0-to-1 transition.
 IBF : Input buffer full is an output indicating that
the input latch contain information.
 INTR : Interrupt request is an output that
requests an interrupts.
 INTE : The interrupt enable signal is neither an
input nor an output; it is an internal bit
programmed via the PC4 (port A) or PC2 (port B)
bits.
 PC7,PC6 : The port C pins 7 and 6 are general
purpose I/O pings that are available for any
purpose.
 ~OBF : Output buffer full is an output that goes
low when data is latched in either port A or port
B. Goes low on ~ACK.
 ~ACK : The acknowledge signal causes the ~OBF
pin return to 0. This is a response from an
external device.
 INTR : Interrupt request is an output that
requests an interrupt.
 INTE : The interrupt enable signal is neither an
input nor an output; it is an internal bit
programmed via the PC6(Port A) or PC2(port B)
bits.
 PC5,PC4 : The port C pins 5 and 4 are general-
purpose I/O pins that are available for any
purpose.
 Used for both transmitting and receiving
data (bidirectional bus I/O).
 “Handshaking” signals are provided to
maintain proper bus flow discipline in a
similar manner to MODE 1.
 Interrupt generation and enable/disable
functions are also available.
•Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1
Strobed Output Timing diagrams.
 Used in Group A only.
 One 8-bit, bi-directional bus port (Port A)
and a 5-bit control port (Port C).
 Both inputs and outputs are latched.
 The 5-bit control port (Port C) is used for
control and status for the 8-bit, bi-
directional bus port (Port A).
 INTR : Interrupt request is an output that
requests an interrupt.
 ~OBF : Output Buffer Full is an output
indicating that that output buffer
contains data for the bi-directional bus.
 ~ACK : Acknowledge is an input that
enables tri-state buffers which are
otherwise in their high-impedance state.
 ~STB : The strobe input loads data into
the port A latch.
 IBF : Input buffer full is an output
indicating that the input latch contains
information for the external bi-directional
bus.
 INTE : Interrupt enable are internal bits
that enable the INTR pin. BIT PC6(INTE1)
and PC4(INTE2).
 PC2,PC1,PC0 : These port C pins are
general-purpose I/O pins that are
available for any purpose.
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