Chapter 3
Addressing Modes
C54x
C55x
Procedure
Allocate sections (code, constants, vars)
Setup addressing modes
Add the values (x1 + x0 + x2)
Store the result (y)
Named
sections, name .sect .usect
given by user
Unnamed
sections, .text .data .bss
default name
System Diagram
Short value
3, 5, 8, 9 bits constant
Example:
1 word, 1 cycle
LD #6, DP
To initialize short
length registers or bit Load DP with the value 6.
fields:
DP, ASM …
Not always available
Copyright © 2003 Texas In
SIEE, Slide 16
Example: MMR (Memory Mapped Registers)
and Immediate Addressing
.sect ”init" STM (STore to Memory-mapped
tbl .int 1,2,3 register) stores an immediate
value to the specified MMR or
x .usect "vars",3 Scratch address.
y .usect "result",1
.sect “code”
start: STM #tbl,AR1 #tbl is the 16-bit address of the
STM #x,AR2
first element of the array tbl.
0000
h MMR = Memory Mapped Registers
MMRs
0060
h Scratch Scratch memory
007F
128 0080
Page 1 128 words
256 0100
Page 2 128 words
512 Pages
DP register 9-bit DP
SP relative, CPL = 1
SP Register 16-bit Stack Pointer
+ 7-bit dma
Page 3 to 510
x .usect "vars",3
y .usect "result",1
.sect “code”
start: STM #tbl,AR1
STM #x,AR2
ARi
End_address =
xxxxxxxxxxx11111
x .usect "vars",3
y .usect "result",1
.sect “code”
start: STM #tbl,AR1
STM #x,AR2 Initialization of AR1 and AR2.
LD *AR1+,A
Copy the values from table in DROM
STL A,*AR2+ ;... to RAM (via A). Indirect addressing
allows sequential access to data.
LD #x,DP System Diagram
LD @x+1,A
ADD @x,A DROM RAM
ADD @x+2,A
tbl[3] x[3]
.text
LD *(x),A
Acc A 0 0 0 0 0 0 1 0 0 0
ADD *(y),A 0 0 0 0 0 0 1 5 0 0
LD @x+1,A
ADD @x,A
ADD @x+2,A
0000h
MMRs Tip: use the .mmregs directive
to allow MMR names to be
interpreted as addresses
0060h
Scratch
007Fh
Copyright © 2003 Texas In
SIEE, Slide 38
MMR Memory Mapped Registers
Addr. Addr.
Name(Hex) Description Name(Hex) Description
IMR 0000 Interrupt Mask Register AR0 0010 Address Register 0
IFR 0001 Interrupt Flag Register AR1 0011 Address Register 1
----- 2 - 5 Reserved AR2 0012 Address Register 2
ST0 0006 Status 0 Register AR3 0013 Address Register 3
ST1 0007 Status 1 Register AR4 0014 Address Register 4
AL 0008 A accumulator low (A[15:00]) AR5 0015 Address Register 5
AH 0009 A accumulator high (A[31:16]) AR6 0016 Address Register 6
AG 000A A accumulator guard (A[39:32]) AR7 0017 Address Register 7
BL 000B B accumulator low (B[15:00]) SP 0018 Stack Pointer Register
BH 000C B accumulator high (B[31:16]) BK 0019 Circular Size Register
BG 000D B accumulator guard (B[39:32]) BRC 001A Block Repeat Counter
T 000E Temporary Register RSA 001B Block Repeat Start Address
TRN 000F Transition Register REA 001C Block Repeat End Address
PMST 001D PMST Register
------- 01E-01F Reserved
+ 7-bit @x
= 23-bit address
= 23-bit address
AADD #const,AR1
ASUB AR1,T0
AMOV #k23,XAR2
.dp x
indir: AMOV #x,XAR0
AMOV #tbl,XAR6
COPY: MOV +
*AR6+, +
AR0+
MOV *AR6+,*AR0+
MOV *AR6 ,*AR0
ROM RAM 55xx
dir: AMOV #x,XDP tbl[4] x[4] CPU
ADD: MOV @(x+0),AC0 I P
y = x0 + x1 + RAM
ADD @(x+1),AC0 D A
ADD @(x+2),AC0 x1 y
.dp x
indir: AMOV #x,XAR0
AMOV #tbl,XAR6
BSET/BCLR bit_name
BCLR ARMS ;clear ARMS
BSET CPL ;set CPL
BCLR C54CM ;clear C54CM