Graduate Institute of Electronics Engineering, NTU

FFT VLSI Implementation

VLSI Signal Processing
台灣大學電機系
吳安宇

1. Shousheng He and Mats Torkelson, A new approach to pipeline FFT

processor. IEEE Proc. Of IPPS, P766-770, 1996.
2. E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, A fast single-chip
implementation of 8192 complex point FFT. IEEE J. Solid-State Circuits,
P300-305, March 1995

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FFT Review
N 1
X (k )    (n)W
n 0
nk
N for k  0,1,..., N - 1

 with WN  e  j ( 2 / N ) 
[0] X [0]

W N0
[4] X [1]
1

W N0
[2] X [2]
1

W N0 W N2
[6] X [ 3]
1 1

W N0
 [1] X [4]
1

W N0 W N1
 [ 5] X [ 5]
1 1

W N0 W N2
 [ 3] X [6]
1 1

W N0 W N2 W N3
 [ 7] X [7]
1 1 1
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Implementation
--- Two Extreme Method
Fully Spread
Reuse Single Butterfly [0] X [0]

W N0
[4] X [1]
1

W N0
[2] X [2]
1

W N0 W N2
[6] X [ 3]
1 1

W N0
 [1] X [4]
1

W N0 W N1
 [ 5] X [ 5]
1 1

W N0 W N2
 [ 3] X [6]
1 1

W N0 W N2 W N3
 [ 7] X [ 7]
1 1 1

Slow  ----------------- Speed ----------------- Fast

Small  ------------------Area------------------- Large
Complicated  ------------ Control --------------- Simple
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Design Consideration
System Requirement
e.g., speed, area,power …
Trade-off in these two cases, we need
More Processing Elements (PE’s)
Better Processing Element Utilization
Rate
Better Control Scheme
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FFT Processor
--- Block Diagram

COEF
ROM

DATA IN Processing DATA OUT

INPUT FFT
Element
BUFFER RAM
(Butterfly)

CONTROL
SIGNAL
CONTROL
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Some Current Themes

Radix-2 Multi-path Delay Commutator. ( N = 16 )

8 4 2 1

BF2 BF2 BF2 BF2

Ｘ Ｘ j

Radix-2 Single-path Delay Feedback. ( N = 16 )

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Some Current Themes (cont.)

8 4 2 1

BF4 BF4 BF4 BF4

Ｘ Ｘ j

Radix-4 Single-path Delay Feedback. ( N = 256 )

192 48 12 3
128 Ｘ 16 32 Ｘ 4 8 Ｘ 1 2
C4 BF4 Ｘ 32 C4 BF4 Ｘ 8 C4 BF4 Ｘ 2 C4 1 BF4
64 16 4
Ｘ 48 Ｘ 12 Ｘ 3
Radix-4 Multi-path Delay Commutator. ( N = 256 )

DC6x64 BF4 Ｘ DC6x16 BF4 Ｘ DC6x4 BF4 Ｘ DC6x1 BF4

Radix-4 Single-path Delay Commutator. ( N = 256 )

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Distinctive merit of the above

The delay-feedback are more efficient
than delay-commutator in terms of
memory utilization
Radix-4 has higher multiplier utilization
,however,Radix-2 has simpler BF which
are better utilized
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Comparison
Radix / Speed
Low  ----------------------------------- High
Control Theme
Simple  ----------------------------------- Complex

Processing Ability / Unit

Low  ----------------------------------- High

Combine the advantages

 Further decompose high radix PE
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Decompose Method (1)

Simply ‘‘reuse’’ the repeated micro unit

Reuse 4
times

A radix-4 PE
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Decompose Method (2)

From algorithm level
Applying 3 index:
n=<n1*N/2 + n2*N/4 + n3>N where n1,n2={0,1} ;n3={0~N/4-1}
k=<k1 + 2k2 + 4k3>N

Summation of n1
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Decompose Method (2) cont.

Summation of n2

Only real-imaginary swapping & sign inversion

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Graphical Explanation (N=16)

Trivial multiplication
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Graphical Explanation (cont.)

The Eqs are equivalent to the operations
below

BF4 BF2 I BF2 II

Control Control
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Circuit of BF2I
First N/2 cycles

Xr(n) Zr(n+N/2)

Xi(n) Zi(n+N/2)

Xr(n+N/2) Zr(n)

Xi(n+N/2) Zi(n)

Second N/2 cycles

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Circuit of BF2II
Xr(n) Zr(n+N/2)
Xi(n) Zi(n+N/2)

Xr(n+N/2) Zr(n)

Xi(n+N/2) Zi(n)

Swap Re&Im and sign inversion

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Radix-22 Single-path Delay Feedback

128 64 32 16 8 4 2 1

x(n) BF2i BF2ii BF2i BF2ii BF2i BF2ii BF2i BF2ii X(k)
Ｘ Ｘ Ｘ

W1(n) W2(n) W3(n)

clk
7 6 5 4 3 2 1 0

FFT architecture using the above technique, for N=256

Compare with original architecture, for N=256

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Structural advantage
Radix-22 has the same complexity as
radix-4,but still retain radix-2 BF
structure
The stage has non-trivial multiplication
Control is simple;
synchronization controller
n
address counter for W
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Conclusions
1. FFT Applications: Radar Signal Processing, Fast
convolution, Spectrum Estimation, OFDM-based
Modulation/demodulations
2. Efficient VLSI architectures (parallel processing) are
required for real-time processing.
3. However, most systems still employ DSP processors (e.g.,
TI C3x/C5x) for computations (fast algorithms like DIT and
DIF FFT).
4. VLIW (Very Long-length Instruction Word)-based processors
(TI C6x) need new programming skills to utilize the two
parallel MAC units.