n f nπ τ / T )τ / T)sinc(ω τ / 2( |)sinc(ω τ / 2|
1.200
1.000
0.800
0.600
0.400
0.200
0.000
-0.200
00
00
00
00
0
0
10
20
30
40
-0.400
-4
-3
-2
-1
Frequency in Hz
pi 3.141593
with ωo = Δ ω and ω = n ωo
for a single square pulse of amplitude “A” we have F(ω) = -τ/2 ∫ τ/2 A e -jωt dt
= 01111011.011100112 + 0.0007813
(a 16 bit representation)
10 A 1010 1111
11 B 1011 1110
12 C 1100 1010
Negative binary, Max & Min and
Rules of addition and subtraction
N
+ - = 2n
–N
maximum positive number is (2n-1 – 1)
and a minimum negative number is (-2n-1 )
For n = 8 bits
–128 ≦ N ≧127
3 MSBs 000 001 010 011 100 101 110 111 +4 LSB
0 NUL DLE SP 0 @ P ` p 0000
1 SOH DC1 ! 1 A Q a q 0001
2 STX DC2 " 2 B R b r 0010
3 ETX DC3 # 3 C S c s 0011
4 EOT DC4 $ 4 D T d t 0100
5 ENQ NAK % 5 E U e u 0101
6 ACK SYN & 6 F V f v 0110
7 BEL ETB ' 7 G W g w 0111
8 BS CAN ( 8 H X h x 1000
9 HT EM ) 9 I Y i y 1001
10 LF SUB * : J Z j z 1010
11 VT ESC + ; K [ k { 1011
12 FF FS , < L \ l | 1100
13 CR GS - = M ] m } 1101
14 SO RS . > N ^ n ~ 1110
15 SI US / ? O _ o DEL 1111
Analog to Digital conversion Rules
The number of used bits determines the resolution of the
A/D converter.
The number of digitized levels N = 2n
Then
v = v1 RR2 / (RR1+RR2+R1R2)
+ v2 RR1 / (RR1+RR2+R1R2)
=(v1R2+v2R1)R/(RR1+RR2+R1R2)
When R1=R2=Ro
v=(v +v )R /(2R+R )
Performance of
the Differential Amplifier
Vout / V1 = - Rf / R1
Difference Op-Amp Circuit
V+ = V2 [ Rf / (R1+ Rf) ]
i1= [V1-V+] / R1
if = - [ Vout - V+ ] / Rf
if = - i1
vc = K e st
K = Vi
RCK s e st + K e st = 0
RC s + 1 = 0 s = - 1/RC
vc = Vi e –t/RC
Charging of a Capacitor
RC d vc / d t + vc = Vs
vc = K1 + K2 e st
RC s) K2 e st + K1 = Vs + 1)
RC s)= 0 + 1) s = - 1/ RC K1 = Vs
t
iin =C d vin / dt
⌠ −Vin iin = vin / R
Vo := dt
R ⋅C vo = - RC d vin / dt
⌡
0
Reactance of Capacitor and
Inductor with Alternating Voltage
For the Capacitor v(t)
)v(t)== V
Vmm sin (ωt) and
sin (ωt for the Inductor
)i(t) = C dv / dt = ωC Vm cos (ωt
= Vm cos (ωt) / (1 / ωC)
= - j Vm sin (ωt) / (1 / ωC).
L d2 Q / d t2 + R dQ / d t + (1/C) Q = Vs
m d x / d t + K d x / d t + Cm x = F
2 2
Qc = D + A e s1t + B e s2t
X=D+Ae s1 t
+Be s2t
The solution for this second order circuit is for the mechanical:
1 1
1 0.9 1 0.9
0.8 0.8
0.7 0.7
Voii 0.6 Vobi 0.6
0.5 0.5
V1oii 0.4 Vosi 0.4
0.3 0.3
0.2 0.2
−4
0.1 − 3 0.1
10× 10 1×10 0
0 0 1 2 3 4 5 6 7 8 9 10
0 1 2 3 4 5 6 7 8 9 10
−3 ωi 9.901 1×10
−3 ωi 9.901
1× 10
The Frequency Bandwidth of Filters
1
−( ωi) ⋅ C ⋅ L
2
v03i :=
1− ( ωi) 2 ⋅ L ⋅ C + j ⋅ ωi ⋅ C ⋅ R v04i :=
1− ( ωi) 2 ⋅ L ⋅ C + j ⋅ ωi ⋅ C ⋅ R
ωi ⋅ L 100
Qi :=
R
Q503 = 3.16 100
80 80
60 60
ωo
= 159.247 40 40
Q503 ⋅ 2 ⋅ π R 4
α := φ1i
3 .2 0 3
20 3.6 φ1i 20
f2 − f1 = 159.155 2⋅ L 0 3.2
φ2i
0
φ2i v0 3i 2 . 8
20 2 . 4 20
1 v0 5i 2 40
ωo : = 40
v0 4i 1 . 6
L⋅ C 60 1 . 2 60
0.8 80
80 0.4
−6
× 0
3 .9 100
4 81 0 100
0 0 100
1 00 200
2 0 0 300
3 0 0 4400 6 00
00 50 0500 7 00100
0 600 80 0 200
700 0 0 1300
9800 900 41
0 00
1 i 3
Combinational Logic Networks
A B A٨B (AB) (A+B) A B A٧B
0 0 0 0 0 0
0 1 0 AND OR NOT (Invert) 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
1 00 1 00
01 1 NAND NOR 01 0
10 1 10 0
11 0 11 0
An XOR Gate
A B A .B A B A ӨB A+B C S
0 0 0 0 0 0 0 +0=0 0
0 1 0 0 1 1 0 +1=0 1
1 0 0 1 0 1 1 +0=0 1
1 1 1 1 1 0 1 +1=1 0
S = AB + AB
C = A.B
The Full Adder
C = AB + AC + BC
S =A B C +A B C +A B C +A B C
Encoder and Decoder
for the Gray Code
Binary Gray Code Gray Code Binary
Current in mA / or R in Ohm
0.5 0.1 5.000
12
0.53 0.2 2.650 0.3
10
0.547 0.3 1.823 0.17 8
62
65
7
96
7
0.
5
54
58
0.
0.
0.
5
0.
0.
0.
0.59 0.8 0.738 0.03
V oltage (V o lts )
0.596 0.9 0.662 0.06
1.5
0
1.76 1.8 1.87 1.9
1.8 1 1.800 0.0513
D io d e V o lta g e
+
Vo
b3 2R O U T 2R is replaced by KΩ 10
- O P A MP 4R ie replaced by KΩ 22
b2 4R R
8R is replaced by KΩ 47
b1 8R
R is replaced by 16 KΩ 100
b0 16R
Vi
ConclusionResistor values and its tolerances are important for building this kind of D/A converter
Digital to Analog Experiment
Vo/Vi = - (R/Ro)bo - (R/R1)b1 - (R/R2)b2 - (R/R3)b3
f = 1 / π R1 C