The 8086 Architecture

The 8086
Microprocessor Family
• Characteristics
– 16 bit microprocessor
– 16 bit data bus
• it can read from or write to memory
and I/O ports either 8 or 16 bits at a
time
– 20 bit address bus
• it can address 220 memory locations
– each location is 1 byte (8 bits) wide,
thus 16 bit words will require
consecutive memory locations

8086 Architecture 2
 Members of this family

• 8088
– same as 8086 but has an 8 bit data bus
• 80186/80188
– enhanced instruction set…but still
backwards compatible
• 80286
– designed for a multi-user, multi-tasking
microcomputer
– users a virtual address mode to prevent
collision of users’ programs
• 80386/80486
– first Intel 32 bit processor
– can directly address up to 4 GB of
memory

8086 Architecture 3
 Internal Architecture

• Bus Interface Unit (BIU)

– handles all transfers of data and
addresses on the buses for the
execution unit
• Execution Unit (EU)
– where stuff really happens
– tells BIU where to fetch an
instruction, decodes it, and then
executes it

8086 Architecture 4
 Execution Unit (EU)

• contains control circuitry for

internal operations
• a decoder for translating
instructions
• a 16-bit ALU
• registers

8086 Architecture 5
 The Flag Register

• a 16 bit register containing nine

active flags
– 6 conditional flags: carry, parity,
aux carry, zero, sign, and
overflow
– 3 control flags: trap, interrupt, and
direction
• a flag is a flip-flop which
indicates some condition
produced by executing an
instruction, or controls certain
operations
8086 Architecture 6
 General Purpose
Registers
• there are 8 8-bit general purpose
registers:
– AH, AL
• Accumulator
– BH, BL
• Base
– CH, CL
• Count
– DH, DL
• Data

• can pair these together to store

16-bit words...AX, BX, CX, DX

8086 Architecture 7
 The BIU Queue

– if the BIU is not busy...the EU is

decoding or executing without the
need of any buses...it can pre-
fetch up to 6 instruction bytes
• these instructions are stored in a
FIFO register set called a queue
• an example of pipelining
• doesn’t provide an advantage when
the instruction being executed is
JMP or CALL

8086 Architecture 8
 Segment Registers
• the 220 bytes of addresses are divided in to
4 64KB segments
– code segment - CS register stores upper 16 bits of
its starting address
• where instructions are coming from
– stack segment - SS register stores upper 16 bits of
its starting address
• stores addresses and data while a subprogram is
executed
– data segment - DS register stores upper 16 bits of
its starting address
• holds data
– extra segment - ES register stores upper 16 bits of
its starting address
• holds more data
• the lower 4 bits are always zero! why?
– example: if, the starting address of the code
segment is 348A0, then CS contains the value
348AH...this is called the segment base
• the segments can overlap in the case of
small program

8086 Architecture 9
 Instruction Pointer
Register (IP)
• contains the 16-bit address of the
next code byte in the code segment
– this is called an offset…it must be
added to the address contained in the
CS register, which is called the base
• example:
– CS contains the value 348AH
– IP contains the value 4214H
– what’s the physical address of the next
code byte?
• you can represent an address in
segment base:offset form…
348A:4214

8086 Architecture 10
 Stack Pointer Register
(SP)

• Holds the 16-bit offset from the

start of the stack segment where
a word was most recently stored
– the top of the stack
– add this offset to the contents of
the SS register to get the physical
address…sound familiar?
– you can use SS:SP notation to
represent physical address

8086 Architecture 11
 Accessing Immediate and
Register Data
• addressing modes
– specify the different ways the processor can
access data
• immediate addressing mode
MOV CX, 437BH
• puts the specified value, 437BH directly
into CX
• can you do this in 2 instructions?
• register addressing mode
MOV CX, AX
• a register is the source of the operand
MOV CX, BL ...legal?
• direct addressing mode
MOV CX, [437AH]
MOV [437AH], CX
• an effective address (offset) is the source of
the operand

8086 Architecture 12
 Why Use Segmented
Model?
• Easier to manipulate 16 bit
numbers than 20 bit numbers…
one less byte to deal with
• Easier to timeshare and
multitask
– each users process can get its own
logical segments for its code and
data
• these values are stored in the
Process Control Block (PCB) for a
process when it is swapped out.

8086 Architecture 13
 Review of Registers
• In EU
– General purpose registers
• AX, BX, CX, DX
– Others
• SP - Stack Pointer (top of the stack)
• ST - Status flag
• BP - Base Pointer, SI - Source
Index, DI - Destination Index
– these usually hold the 16 bit offset of a
data word in one of the segments

8086 Architecture 14
• In BIU
– Segments registers
• CS, DS, SS, ES
– Others
• IP - Instruction Pointer (next
instruction in the CS)
• Queue - a set of registers

8086 Architecture 15
 Review of Addressing
Modes
• Immediate - operand is a
constant value contained in the
instruction
MOV AX, 0100H
• Register - operand is an 8-bit or
a 16-bit register
MOV SP, BX
• Direct - operand is a fixed
location in memory
MOV CL, [48H]
MOV [48H], CL

8086 Architecture 16
 Another Addressing
Mode
• Indirect - operand is a memory
location determined at run-time
by using the address stored in
one or two registers
MOV AX, [BX][SI]

8086 Architecture 17