Hardware/Software Introduction
Chapter 3 General-Purpose
Processors: Software
– Datapath is general
– Control unit doesn’t PC IR
store the algorithm –
the algorithm is
“programmed” into the I/O
Memory
memory
I/O
...
Memory
10
11
...
– Get next
Control unit Datapath
ALU
instruction into IR Controller Control
/Status
– PC: program
Registers
counter, always
points to next
instruction PC 100 IR
load R0, M[500]
R0 R1
means Registers
PC 100 IR R0 R1
load R0, M[500]
I/O
...
100 load R0, M[500] Memory
500 10
101 inc R1, R0
102 store M[501], R1
501 ...
datapath Registers
register
10
PC 100 IR R0 R1
load R0, M[500]
I/O
...
100 load R0, M[500] Memory
500 10
101 inc R1, R0
102 store M[501], R1
501 ...
instruction does
nothing during PC IR
10
100 R0 R1
load R0, M[500]
this sub-
operation I/O
...
100 load R0, M[500] Memory
500 10
101 inc R1, R0
102 store M[501], R1
501 ...
memory Registers
– This particular
instruction does PC IR
10
100 R0 R1
load R0, M[500]
nothing during
this sub- I/O
...
operation 100 load R0, M[500] Memory
500 10
101 inc R1, R0
102 store M[501], R1
501 ...
Registers
10
PC 100 IR R0 R1
load R0, M[500]
I/O
...
100 load R0, M[500] Memory
500 10
101 inc R1, R0
102 store M[501], R1
501 ...
PC=101
Registers
Fetch Decode Fetch Exec. Store
ops result
clk s 10 11
PC 101 IR R0 R1
inc R1, R0
I/O
...
100 load R0, M[500] Memory
500 10
101 inc R1, R0
102 store M[501], R1
501 ...
PC=101
Registers
Fetch Decode Fetch Exec. Store
ops result
clk s 10 11
PC 102 IR R0 R1
store M[501], R1
PC=102
Fetch Decode Fetch Exec. Store I/O
ops result ...
100 load R0, M[500] Memory
clk s 500 10
101 inc R1, R0 501 11
102 store M[501], R1
...
– Desktop/servers: Memory
32-bit, even 64
• PC size Jurusan Teknik Informatika Untag Surabaya 14
Architectural Considerations
• Clock frequency Processor
Control unit Datapath
– Inverse of clock ALU
than longest
register to PC IR
register delay in
entire processor I/O
Fetch-instr. 1 2 3 4 5 6 7 8
Decode 1 2 3 4 5 6 7 8
Execute 1 2 3 4 5 6 7 8
Instruction 1
Store res. 1 2 3 4 5 6 7 8
Time
pipelined instruction execution
Processor Processor
• Princeton
– Fewer memory
wires
• Harvard
– Simultaneous Program
memory
Data memory Memory
(program and data)
program and data
memory access
Harvard Princeton
slow
Processor
processor
– Holds copy of part of
Memory
memory
– Hits and misses Slower/cheaper technology, usually on
a different chip
...
• Instruction Set
– Defines the legal set of instructions for that
processor
• Data transfer: memory/register, register/register, I/O,
etc.
• Arithmetic/logical: move register through ALU and back21
Jurusan Teknik Informatika Untag Surabaya
A Simple (Trivial) Instruction Set
Assembly instruct. First byte Second byte Operation
Immediate Data
Register-direct
Register address Data
Register
Register address Memory address Data
indirect
Data
L2:
from one program
– Program makes system calls
to the OS Jurusan Teknik Informatika Untag Surabaya 29
Development Environment
• Development processor
– The processor on which we write and debug our
programs
• Usually a PC
• Target processor
– The processor that the program will run on in our
embedded system
• Often different from the development processor
Sources: Intel, Motorola, MIPS, ARM, TI, and IBM Website/Datasheet; Embedded Systems Programming, Nov. 1998
down 0001
Mov2 M[dir] = RF[rn]
to Fetch
corresponding to the
Ms
operations required by the 3x1 mux Mre Mwe
FSM
• Unique identifiers created for A Memory D