Scaling Continues

Intel® Core™ Duo SRAM test-chip

65nm process 45nm process
90.3 mm2 die size 119 mm2 die size
151.6 million transistors >1 billion transistors

Estimate
45 nm SRAM CPU Ramp

65 nm SRAM CPU Ramp

90 nm SRAM CPU Ramp

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010

Source: Intel Future options subject to change – Images not to scale

 Through the Next Decade and Beyond

10µm 1µm 100nm 10nm

1013 Bipolar PMOS NMOS Voltage Energy Eff New Nano-
CMOS
1012 Scaling Scaling structures

1011
1965 Data (Moore)
1010
Memory
109 Microprocessor
Tri-Gate Carbon
Transistors/Die

108 Nanotube FET

107
106 S D S
105
III-V
104 G

103
102
Kilo Mega Giga Tera
101 Xtor Xtor Xtor Xtor
100
1960 1970 1980 1990 2000 2010 2020 2030

Source: Intel Future options subject to change

 But Power Becomes a
Dominant Design Factor

1400
SiO2 Lkg
1200 SD Lkg
Power Density (W/cm2)

1000 Active

800

600

400

200

0
90nm 65nm 45nm 32nm 22nm 16nm

Source: Intel Future options subject to change

 And Device Variations Increase

1.4

Frequency
Normalized Frequency

1.3 30%
~30%
1.2

1.1 Leakage
Power
1.0
5X ~5-10X
0.9
1 2 3 4 5
Normalized Leakage (Isb)

Source: Intel
 Shifting Design Paradigms for
“DEEP” VLSI Designs

Energy-Efficiency

Device Variability

Layout Complexity
 Constrained Power Through Technology,
Circuits and Architecture Innovations

1400
SiO2 Lkg
1200 SD Lkg
Power Density (W/cm2)

1000 Active

800

600

400

200

0
90nm 65nm 45nm 32nm 22nm 16nm

Source: Intel
 Leakage Control
Body Bias Stack Effect Sleep Transistor
Vbp
Vdd
+Ve

Equal Loading Logic Block

-Ve Vbn

2-10X 5-10X 2-1000X

Reduction Reduction Reduction
 Active Power Reduction

High Supply
Low Supply

Voltage
Voltage

Slow Fast Slow Multiple Vdd

• Vdd scaling will slow down

• Mimic Vdd scaling with multiple Vdd

• Challenges:
• Interface between low & high Vdd
• Delivery and distribution
 Dual-Supply Last-Level Cache
1.2V
Supply 1
Variable 0.7V
standby
Supply 2
Fixed = 1.2V
~35%
Less
Microprocessor Core
(logic, L0 -L2 cache) Power

Equivalent
LLC
Performance

Dual Vcc Processor

 Platform Power Delivery

Desktop Server
Up to
30%
Board
Area
Mobile Handheld
Power delivery
components
 Fast CMOS Voltage Regulator

~97% CMOS-compatible
Efficient inductors

Inductor Magnetic
wires material

Source: Intel
 Probabilistic Behavior

Due to variations

Probability
in:
Vdd, Vt, and Temp

Path Delay
Delay

Deterministic

Frequency
# of Paths
# of Paths

Deterministic Probabilistic
Probabilistic
10X variation
~50% total power

Delay Target Delay Target Leakage Power

 Move to Statistical Design

• Multi-variable design optimization for:

• Yield and bin splits
• Parameter variations
• Active and leakage power
• Performance
 Yesterday’s Freelance
Layout and Routing

Vdd
Vdd

Ip Op Op

Vss
Vss
 Tomorrow’s Orientation and
Metal Restrictions

Vdd
Vdd

Ip Op Op

Vss
Vss
 The New Playbook

Today: Tommorrw:
• Local optimization, • Global optimization,
single variable multi-variate
• Deterministic tools • Probabilistic tools
and designs and designs
• Transistor density • Energy-balanced
• Freelance layout • Sea-of-transistors