THE MICROPROCESSOR & ITs

ARCHITECTURE

BY ENGR: SHAH REHAN ALI

THE PROGRAMMING MODEL
What is programming model…?
The register , which are directly accessible by an application
program are specified by the instruction ,are called program
visible registers.
Beyond program visible there are some other registers called
program invisible register, which is not directly accessed by the
user …but through some other register.
Invisible register were introduce with Intel 80286, with the
introduction of PMMAd
Multi-Purpose Register
General Purpose Register
 EAX,EBX, ECX etc can be used as 32-bit register, also 16-bit
register , or as either of two 8 bit register. If a 8 bit register is
addressed only that portion of the register is changed and
without effecting the remaining bit.
Accumulator is often involved in instruction like multiplication,
Division. It is consider as a multipurpose register, b/c in 80386
Acc: sometimes used to hold offset Instruction.
Base Index register holds the offset addresses in all versions of
Intel Microprocessor.
 Count Reg: register holds the count for various Instruction.

Data Reg: Holds the data such as a part of the data from the
multiplication or part of dividend before division.

Instruction Pointer: register addresses the next instruction in the

program to be executed, from the code segment.
Stack pointer : addresses an area of memory called stack. The
stack memory store data through this pointer.
Segment Register: SR generate memory addresses when
combined to other registers. A SR function different in RMAd…
and PMMAd..
The EFLAG
C (carry): Holds the carry after addition or borrow after
subtraction Also indicates error conditions.
P (Parity ): P = 0 for odd parity and logic 1 for even parity
Parity is used as a data integrity check (in comm).
 A (aux-carry) :Used to hold half carry (or borrow) between bit
positions 3 & 4.
Z (zero): Indicates that the result of an arithmetic or logic
expression is zero (Z = 1)
S (sign) :Contains arithmetic sign of result after an arithmetic or
logic instruction (S = 1 for positive).
T (trap) : Used for debugging, if T=1 the μP interrupts the
program flow depending on the contents of debug and control
registers .
I (interrupt): Controls the operation of INTR input pin.
D (direction): Selects either an increment or decrement for the
DI/SI register during string operations D=1 for decrements. With
STD & CLD.
O (overflow) : Indicates arithmetic overflow in signed arithmetic
O=1, indicates an overflow condition.
NT (nested task): Indicates that the currently executed task
is nested within another task in protected mode .
IOPL (I/O privilege level): Used in protected mode to select
privilege level of I/O devices ,If IOPL is higher than current priv.
level, an interrupt occurs .
IOPL = 00 (highest), 11 (lowest) .
RF (resume): Used for debugging to resume regular execution
after the next instruction.
VM (virtual mode): VM=1 selects virtual mode of operation, i.e.,
allows for multiple 1M byte memory partitions to exist for several
DOS programs to execute simultaneously.
The Segment Register
CS Code Segment: Defines starting address of the memory
page containing code In real mode, it defines start of a 64K
bytes section of memory, In protected mode (x386 +) it selects a
descriptor that defines the starting point and length of code
segment (upto 4G bytes).
DS Data Segment: Data segment contains most data used by a
program. Individual data addressed using DS + offset address,
Length is 64 K (x86-x286) and 4G (x386+) .
SS & ES .
The Real Mode Memory addressing
The microprocessor below 80286 operate in real mode. While
80286 to Pentium 4 can operate either in real mode or protected
mode.
In real mode MP can address up to 1MB of memory even if it is
Pentium 4 processor. The DOS operating system require MP to
operate in real mode.
The real mode uses Segment and Offset scheme for
Addressing, the combination of segment and offset addresses
accesses a memory location in the real mode.
The segment address contained in any of the segment
register defines the beginning of a 64k segment and
the offset selects the location within 64k segment.
Offset (Displacement).
In the real mode the content of a segment register are internally
append by placing a 0H at the right most end , this form a 20bit
address to access 1M-byte of memory.
Example:- if the segment address is 2000H and the displacement
is of 1000H, what is the effective or physical address ?
E.A=?? .
The segment register contain the segment address and the offset
is contained with some other register for example the code
segment define the start of code segment and offset is contained
with instruction pointer.
The major advantage of Real memory is relocation of program
and data without any change. Relocation means the program can
be shifted to any segment area in the memory and can be
execute without any difference.
In real mode, using an offset larger than 16 bit width will cause a
PC to hang.
Success without a positive attitude is called luck

But
Success with a positive attitude is called achievement

So be an achiever…..
The protected Mode Memory Addressing
From an application point of view, protected mode and real
mode are not that different. Both use memory segmentation,
Interrupts, and device driver to handle the hardware.
The MP 80286 and above can operate in real and protected
mode, that they can access the data and program not only in the
first 1 MB of memory but above the 1MB of memory.
The segment Address is not present in protected mode, instead
of segment address the register contains a selector the selects a
descriptor from a descriptor table.
The Descriptor describe the…
* Memory Segment Location
* Length
* Access rights .

Indirectly the segment register here also has a segment address

that ‘s why the program written for real mode can also operate
for protected mode without any change.
The following diagram shows the content of a selector that is
content of a segment register when MP operate in protected mode.
 The segment register contain a 13 bit selector field a table
selector bit and a request privilege level field.

The selector field chooses one the 8192 descriptor from the
descriptor table.
The T1 field decides whether the global Descriptor table (TI=0)
or the Local Descriptor (TI=1).
The request privilege level request the access privilege of a
memory segment. The highest privilege level is 00 and lowest
11.if the access right byte of the descriptor has set as 10 that is
request PL and RPL contain 11 then access granted b/c 10 is
higher in priority than 11.
Two types of Descriptor .
1- Global Descriptor : contain segment definition and that apply to All
Application . (SD).
2- Local Descriptor : are unique to an Application . (AD).

 There are total 8192 (global) + 8192 (local) = 16,384 descriptor , which are
avilable to an application at any time.
The Descriptor format
The base address describe the starting location of the memory
segment . For 80286 MP the base address is of 24 bits so
segment begins at any location in 16M-bytes of memory.
The 80386 and above use 32 bit wide addresses so a segment
can start at any location in 4Gbytes of memory.
The segment limit contain the last offset address of a segment .
For example if a segment at F000ooH and ends at F000FFH, for
the 80286 the base address is F00000H and the limit is FFH.

If we see the 80386 and above the base is 00F00000H and the
limit is 000FFH.

Why there is difference…?

0.2.
The 80286 has a 16 bit limit and 80386 has a 20bit limit. Thus
80286 can access segment that are B/w 1 and 64k bytes and
80386 and above can access the segment that are between 1
and 1M byte 0r 4k and 4G Byte.
The granularity bit is found in 80386 and above processor. If
G=0 the limit specifies a segment limit of 00000H to FFFFFH
and if G=1 the value of the limit is multiplied by 4k bytes
(appended with xxxh) so as to access up to 4 G bytes of
memory.
The AV bit, is used by some operating system to indicate
whether the descriptor is available AV=1 or it is not available
Av=0.
The D bit decides the access of register and memory data in the
real mode or protected mode.

If D=0 , the instruction are 16 bit instructions , so compatible

with 8086-80286 instruction. If D=1 the instruction are 32 bit
instructions.
 Program Invisible register
The invisible register ?
When a new value is placed into a segment register , so
assuming it a selector, it loads the invisible portion with the base,
limit and access rights byte.
The MP does not refer to segment register each time but it takes
the base limit and Access right byte from cache.
The addresses of GDT and LDT and their limit (up to 64k bytes)
are loaded in special register .
The other register enclosed by the dotted line are the part of
descriptor cache.
The cache is used to reduce the number of actual memory
references needed to construct the physical address.

There is one cache register for each of the 6 segment

registers,..? LDTR and TR are selector

The base address, limit and access right of the descriptor are
loaded from every time the corresponding selector changes.
The LDTR and TR refer to special system descriptor in GDT
These registers provide hardware acceleration support for task
register.
The LDTR selector indexes a GDT system describing the
segment containing the LDT while the cache stores the actual
LDT descriptor.
The LDTR selector can be loaded with a new value when
another task is in run.
 Descriptor Tables
The descriptor tables define all of the segments which are used
in intel486 chip.

 Global Descriptor table.

 Local Descriptor table.
 Interrupt descriptor table.
Paging Mechanism
The mapping of linear address(?) to a physical address is called
paging.
Linear address is generated by a program.
This mechanism function in both real mode and protected mode.
 The PG bit in control register selects the paging mechanism for
certain application. If pg=o the linear address generated by a
program becomes the physical address and if pg=1 the linear
address become the physical address through the page
mechanism.
CR3 contain the page directory base address, which locates
the page directory in the memory system.
The page directory contain 1024 page directory entries of 4
bytes each.
 The linear address consists of three parts
1- Bits 0-11 offset
2- Bits 12-21 LD1 used to locate page frame.
3- Bits 22-31 LD2 used as for top level page table ( page
directory).
The leftmost 10bits are addressing an entry in the page
director , for the linear address 00000000H – 003fffffH, the first
entry of the page directory is accessed.
Each page directory represent a 4MB section of memory space.
 Page directory and page table
The page directory contains 1024 double word addresses up to
1024 page tables.

The page directory and page table are 4k bytes in length.