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Objectives
Describe and compare the basic CPU architecture of the C54x and the C55x Discuss pipeline phases List the key features of the C54x and C55x memory map and peripherals Give a detailed presentation of CPU registers
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C5000
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Complex Algorithms:
Specialised instructions (Viterbi, LMS) Bit reverse adressing (FFT) Circular buffers (FIR filters)
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Multiple Buses
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Program Bus
Data Bus
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C54X version.
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User-configurable IDLE Domains Variable length instructions and efficient block repeat operations Dual MAC operations in a single cycle Performs high precision arithmetic and logical operations Shift a 40-bit result up to 31 bits to the left,or 32 bits to the right Performs arithmetic in a simpler ALU of 16 bits. Hold results of computations and reduce the required memory traffic (4 Accumulators)
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x4
x3 x2 x1 x0
Time
ALU
y0 = anxn
n=0 MAC *AR2+, *AR3+, A
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x4
x3 x2 x1 x0
Time
ALU
y0 = anxn
n=0 MAC *AR2+, *AR3+, A
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Data
Coeffs a0 a1 a2 a3
2 taps/cycle
x4 x3 x2 x1 x0
Results
Time
MAC
AC0 A AC1
C55x: MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1 C54x: MAC *AR2+, *AR3+, A
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C54x Architecture
Program A/D Bus (P) PC XPC DP Decode @x2
Addr Gen
Data Read A/D Bus (C) Data Read A/D Bus (D)
MAC AR0-7 A B
ALU
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C55x Architecture
Program A/D Bus Data Read Buses (D, B, C) Instr Buffer Queue
A d d r Gen
PC
ARn
CDP
MAC
MAC
Decode
AC0 AC1
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PC RETA Prog Addr Gen Status Registers Program Flow PPU Interrupts PU
Internal
PDB[32]
External
FF_FFFF
IU Instruction Buffer 64 x 8
48
4-byte packet fetched every cycle Variable-length instruction set (8, 16, 24, 32, 40, 48-bit)
Decoder
PU
AU
DU
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ARAU A d d r G e n
X X X
AR0-7 CDP DP
23/16-bit
CB[16] FF_FFFF
Last 64KW Pg 127
ALU/Shft T0 T1 T2 T3
16-bit
DB[16]
A-Unit handles all data addressing Xreg: 23 bits, reg: 16 bits Where else could the data go?...
AU
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External
FF_FFFF
DB[16]
D-Unit executes most mathematical operations Now, what happens to the result?...
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AU
Internal
FAB[24]
DU External
FF_FFFF
EB[16] FB[16]
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JTAG Test/ JTAG Test/ Emulation Emulation Control Control Muxed GP I/O Muxed GP I/O
Saturation and Rounding Hardware Two 40-bit ACCs 40-bit ALU 40-bit Barrel Shifter Temporary Register Exponent Encoder Program and Data Address Generation Units Compare, Select and Store Unit 4 Internal Bus Pairs External Interface
DMA
Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5
Timer Timer 8/16-bit Host Port 8/16-bit Host Port Interface (HPI) Interface (HPI)
Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP)
Addressing Unit 8 Auxiliary Registers 2 Addressing Units Power Management Power Management
PLL Clock PLL Clock Generator Generator S/W Waitstate S/W Waitstate Generator Generator
C5416 example
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JTAG Test/ JTAG Test/ Emulation Emulation Control Control Muxed GP I/O Muxed GP I/O
Saturation and Rounding Hardware Two 40-bit ACCs 40-bit ALU 40-bit Barrel Shifter Temporary Register Exponent Encoder Program and Data Address Generation Units Compare, Select and Store Unit 4 Internal Bus Pairs External Interface
DMA
Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5
Timer Timer 8/16-bit Host Port 8/16-bit Host Port Interface (HPI) Interface (HPI)
Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP) Multichannel Buffered Multichannel Buffered Serial Port (McBSP) Serial Port (McBSP)
Addressing Unit 8 Auxiliary Registers 2 Addressing Units Power Management Power Management
PLL Clock PLL Clock Generator Generator S/W Waitstate S/W Waitstate Generator Generator
C5416 example
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C54x Pipeline
Program A/D Bus (P)
Internal Memory
Data Read A/D Bus (D) Data Read A/D Bus (C) Data Write A/D Bus (E)
A D
External Memory
Internal: Up to 4 accesses / cycle Pipeline Phases P - generate program address F - get opcode D - decode instruction A - generate read address R - read operands X - execute
P F D A P F D P F P
X R X A R X D A R X
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Full Pipeline
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Internal Memory
Data Read A/D Bus (D) Data Read A/D Bus (C) Data Write A/D Bus (E)
A D
External Memory
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Pipeline Phases P - generate program address F - get opcode D - decode instruction A - generate read address R - read operands X - execute P F D A P F D P F P R A D F P X R A D F P X R A D F
X R X A R X D A R X
Full Pipeline
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PA PD DA/CA DD/CD EA ED
PC Program mem Decoder ARs, ARAU Data mem ARs, ARAU MAC, ALU Data mem
When storing results back to memory, the write is broken into two phases: - generating the write address - writing the result Overlaid onto R & X phases
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Pipeline Implications 1 of 3
What if all data and program are external?
P1 F1 P2 D1 F2 P3 A1 D2 F3 P4 R1 A2 D3 --X1 R2 A3 ---
54x
D
X2 R3 ---X3 F4 P5 -D4 F5 P6 A4 D5 F6 R4 A5 D6 X4 R5 A6 X5 R6
External read conflicts with external fetch Can reduce performance by at least 50%
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Pipeline Implications 2 of 3
When either Program or Data is located internally... fetch and read can occur simultaneously
P1 F1 P2 D1 F2 P3 A1 D2 F3 P4 R1 A2 D3 F4 P5
54x D
or
54x P
X1 R2 A3 D4 F5 P6 X2 R3 A4 D5 F6 X3 R4 A5 D6 X4 R5 A6 X5 R6 X6
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Pipeline Implications 3 of 3
Program ROM Data ROM SARAM DARAM
A D
There are no conflicts as long as you follow these rules: ROM/SARAM - 1 access per block per cycle DARAM - 2 accesses per block per cycle
Size and number of blocks vary based upon device - refer to memory map
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External memory C000 DROM bit FFFF External memory or Internal ROM
Maps most of on-chip DARAM into Program space Maps most of on-chip Program ROM into Data space
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DARAM External memory External memory 7FFF External memory C000 Internal 16K x 16 ROM Vectors C000 External memory or Internal ROM Vectors
FF80 FFFF
Vectors
FF80 FFFF
FF80 FFFF
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The OVLY bit selects between two different program memory maps:
OVLY = 0 00 0000 00 0000 OVLY = 1 32K DARAM Upper 32K Page 0 External Mem
. . .
SAME
7F 0000
7F 0000
32K DARAM
7F FFFF
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C5409
3 Multi-Channel BSPs: Each offers up to 128-channel rcv/xmt 6-channels: facilitates data/program transfers w/o CPU intervention Host Port Interface: 8-bit interface to host processor Boot Loader: Multiple ways to load program to volatile memory One 20-bit timer: Can generate timer-based interrupts General Purpose I/O: External lines dedicated to I/O Phase Locked Loop: software programmable Idle Modes: Power saving modes and features
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C54x Review
Name
How
large are the accumulators? many adders are on the part? are the Memory Mapped Registers located? is the Reset Vector located?
How
Where
Where
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large are the accumulators? many adders are on the part? are the Memory Mapped Registers located? is the Reset Vector located?
40 bits
How
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Pipeline execution breaks an operation into smaller pieces that can be executed independently. The fetch pipeline is done inside the Instruction Buffer Unit and fills IBQ The execute pipeline fetches instructions from IBQ and executes them
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IBQ
64x8
Fetch-packet pipeline fetches 4-byte packets from program memory INTO the IBQ every cycle (unless IBQ is full) Fetch packet pipeline operates independently from execute pipeline
Program Bus
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D - decode opcode AD - compute address AC1 - gen read address AC2 - memory wait R - read operands X - execute W - write to memory
IBQ
64x8
1-6 bytes
Execute pipeline fetches instructions FROM the IBQ, then executes them IU performs fetch/decode from IBQ AU generates operand addresses AU/DU execute instructions X: result to register W: result to memory
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AD
Read/modify registers involved in data address generation. Perform operations that use the A-unit ALU. Decrement ARx for the conditional branch instruction Evaluate the condition of the XCC instruction
AC1
Memory read operations, send addresses on the appropriate CPU address buses.
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R
Read data from memory, I/O space, and MMR-addressed registers. Read A-unit registers Evaluate the conditions of conditional instructions.
X
Read/modify registers that are not MMR-addressed. Read/modify individual register bits. Set conditions. Evaluate the condition of the RPTCC instruction. W Write data to MMR-addressed registers or to I/O space (peripheral registers). Write data to memory.
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Program
00_0000 01_0000 05_0000
Internal
Program and data share the same map 2 ways to view the map:
Prog Data
23 23 0 1 0
SARAM (128KW)
External
FF_FFFF
A(24) A(24) D(32) D(32)
1. Program - (Bytes) 7F_FFFF - 16M x 8-bit, linear 24-bit addresses - Used by fetch/decode logic 2. Data (Words) - 8M x 16-bit, segmented into 64K pages, 23-bit address - Most code written by a user will access data
C55xx core
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Memory Access
16M bytes of memory are addressable as program space or data space When the CPU uses program space to read program code from memory, it uses 24-bit addresses to reference bytes. When program accesses data space, it uses 23-bit addresses to reference 16-bit words. In both cases, the address buses carry 24-bit values, but during a data-space access, the least significant bit on the address bus is forced to 0.
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Data Memory
Data space is divided into 128 main data pages (0 through 127) of 64K addresses each. An instruction that references a main data page concatenates a 7-bit main data page value with a 16-bit offset. On data page 0, the first 96 addresses (00 0000h00 005Fh) are reserved for the memory-mapped registers (MMRs).
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I/O Memory
I/O space is separate from data/program space and is available only for accessing registers of the peripherals on the DSP. The word addresses in I/O space are 16 bits wide, enabling access to 64K locations The CPU uses the data-read address bus DAB for reads and data-write address bus EAB for writes. When the CPU reads from or writes to I/O space, the 16-bit address is concatenated with leading 0s.
Example, suppose an instruction reads a word at the 16-bit address 0102h. DAB carries the 24-bit value 00 0102h.
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EHPI - 16-bit host access to memory DMA - 6 Channels (rotating priority) EMIF - Access to EPROM, SRAM, SBSRAM, SDRAM BOOT Loader - From external memory, Host, McBSP
3 Multi-Channel Buffered SPs - High speed sync serial comm General Purpose I/O - 8-bit i/o port Timer/Counters - Two 20-bit timer/counters Power-Down Modes Instruction Cache (24K bytes)
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The study of CPU registers gives a very good understanding on the processor architecture. The C54x DSP is code compatible with the C55x, therefore registers have the same functionally in both DSPs. Registers in the C55x are more complex so we will see their role and give equivalents for the C54x. The following table summarizes the differences.
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16 bits 7 bits
none none
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Block-repeat start address registers 0 and 24 bits 1 Data stack pointer High part of XSP and XSSP System stack pointer Status registers 0 through 3 Temporary registers 0 to 3 Transition registers 0 and 1 Extended auxiliary registers 0 through 7 Extended coefficient data pointer Extended data page register Extended data stack pointer Extended system stack pointer Extended program counter 16 bits 7 bits 16 bits 16 bits 16 bits 16 bits 23 bits 23 bits 23 bits 23 bits 23 bits 7 bits
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Accumulators (AC0AC3)
In the TMS320C54x-compatible mode (C54CM = 1), accumulators AC0 and AC1 correspond to TMS320C54x accumulators A and B, respectively.
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When performing two 16-bit extremum selections update TRN0 and TRN1 based on the comparison of two accumulators high words and low words. TRN0 is updated based on the comparison of the accumulators high words; TRN1 is updated based on the comparison of the low words. When performing a single 40-bit extremum selection the selected transition register (TRN0 or TRN1) is updated based on the comparison of two accumulators throughout their 40 bits.
TRN0 and TRN1 can hold transition decisions for the path to new metrics in Viterbi algorithm implementations.
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Hold one of the memory multiplicands for multiply, multiply-and-accumulate, and multiplyand-subtract instructions Hold the shift count used in addition, subtraction, and load instructions performed in the D unit Keep track of more pointer values by swapping the contents of the auxiliary registers (AR0AR7) and the temporary registers (using a swap instruction) Hold the transition metric of a Viterbi butterfly for dual 16-bit operations performed in the D-unit ALU
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The CPU includes eight extended auxiliary registers XAR0XAR7 Each high part ( ARnH) is used to specify the 7bit main data page for accesses to data space.
A 16-bit offset to the 7-bit main data page (to form a 23-bit address) A bit address (in instructions that access individual bits or bit pairs) A general-purpose register or counter
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ARn Auxiliary register n and XARn Extended auxiliary register n are accessible via dedicated instructions .
ARn is mapped to memory XARn is not mapped to memory.
XAR0XAR7 or AR0AR7 are used in the AR indirect addressing mode and the dual AR indirect addressing mode. Basic arithmetical, logical and shift operations can be performed on AR0AR7 in the A-unit arithmetic logic unit (ALU).
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CDP is a coefficient data pointer, and CDPH an associated extension register, concatenate the two form the extended CDP that is called XCDP CDPH is used to specify the 7-bit main data page for accesses to data space. The low 16 bits part (CDP) can be used as: A 16-bit offset to the 7-bit main data page (to form a 23-bit address) A bit address (in instructions that access individual bits or bit pairs) A general-purpose register or counter
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XCDP Extended coefficient data pointer is accessible via dedicated instructions only. XCDP is not a register mapped to memory. CDP Coefficient data pointer is accessible via dedicated instructions and as a memorymapped register CDPH High part of extended coefficient data pointer is accessible via dedicated instructions and as a memory-mapped register
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Circular Buffer Start Address Registers (BSA01, BSA23, BSA45, BSA67, BSAC)
The CPU includes five 16-bit circular buffer start address registers Each buffer start address register is associated with a particular pointer A buffer start address is added to the pointer only when the pointer is configured for circular addressing in status register ST2_55.
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Three 16-bit circular buffer size registers specify the number of words (up to 65535) in a circular buffer. Each buffer size register is associated with particular pointers In the TMS320C54x-compatible mode (C54CM = 1), BK03 is used for all the auxiliary registers, and BK47 is not used.
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Data page register, DP, and associated extension register DPH can be concatenated to form an extended DP that is called XDP The high part (DPH) is used to specify the 7bit main data page for accesses to data space. The low part specifies a 16-bit offset (local data page) that is concatenated with the main data page to form a 23-bit address. In the DP direct addressing mode, XDP specifies a 23-bit address, and in the k16 absolute addressing mode, DPH is concatenated with a 16-bit immediate value to form a 23-bit address.
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XDP Extended data page register Accessible via dedicated instruction only. XDP is not a register mapped to memory. DP Data page register accessible via dedicated instructions and as a memory-mapped register DPH High part of extended data page Register is accessible via dedicated instructions and as a memory-mapped register
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The 9-bit peripheral data page register (PDP) selects a 128-word page within the 64K-word I/O space.
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The data stack pointer (SP), a system stack pointer (SSP), and an associated extension register (SPH) are the CPU stack registers When accessing the data stack, the CPU concatenates SPH with SP to form an extended SP that is called XSP. XSP contains the address of the value last pushed onto the data stack. SPH holds the 7-bit main data page of memory, and SP points to the specific word on that page.
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XSP Extended data stack pointer is accessible via dedicated instructions only. XSP is not a register mapped to memory. SP Data stack pointer is accessible via dedicated instructions and as a memorymapped register XSSP Extended system stack pointer is accessible via dedicated instructions only. XSSP is not a register mapped to memory. SSP System stack pointer is accessible via dedicated instructions and as a memorymapped register SPH High part of XSP and XSSP is accessible via dedicated instructions and as a memorymapped register.
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PC Program counter is a 24-bit register holds the address of the 1 to 6 bytes of code being decoded in the I unit. When the CPU performs an interrupt or call, the current PC value (the return address) is stored on the stack, and then PC is loaded with a new address. When the CPU returns from an interrupt service routine or a called subroutine, the return address is restored to PC.
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RETA Return Address Register CFCT Control-flow Context Register If the selected stack configuration uses the fast-return process
RETA is a temporary holding place for the return address and CFCT is a temporary holding place for the 8-bit loop context while a subroutine is being executed CFCT, along with RETA, enables the efficient execution of multiple layers of subroutines You can read from or write to RETA and CFCT as a pair with dedicated, 32-bit load and store instructions. The Loop context is stored into CFCT, when an interrupt or a subroutine call occur the loop context is stored in CFCT and restored on return.
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IVPD Point to the DSP interrupt vectors (IV0IV15 and IV24IV31) IVPH Point to the host interrupt vectors (IV16IV23) IFR0, IFR1 Indicate which maskable interrupts have been requested IER0, IER1 Enable or disable maskable interrupts DBIER0, DBIER1 Configure select maskable interrupts as time-critical interrupts
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The DSP interrupt vector pointer (IVPD) points to the 256-byte program page that contains the DSP interrupt vectors (IV0IV15 and IV24IV31). These vectors can be mapped to memory that is allocated to the DSP only. The host interrupt vector pointer (IVPH) points to the 256-byte program page that contains the host interrupt vectors (IV16IV23). These vectors can be mapped to memory shared by the DSP and the host processor, so that the host processor can define the associated interrupt service routines. If IVPD and IVPH have the same value, all of the interrupt vectors will be in the same 256-byte program page.
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When a maskable interrupt request reaches the CPU, the corresponding flag is set to 1 in one of the IFRs. This indicates that the interrupt is pending, or waiting for acknowledgement from the CPU. One can read IFRs to identify pending interrupts, and write to the IFRs to clear pending interrupts. To clear an interrupt request write a 1 to the corresponding IFR bit. All pending interrupts can be cleared by writing the current contents of the IFR back into the IFR. Acknowledgement of a hardware interrupt request also clears the corresponding IFR bit. A device reset clears all IFR bits.
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RTOSINTF bit 10 in IFR1 is an interrupt flag bit for the real-time operating system interrupt, RTOSINT
To clear this flag bit to 0 (and clear its corresponding interrupt request), write a 1 to the bit.
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DLOGINTF is the bit 9 of IFR1 for the datalog interrupt, If DLOGINTF bit is: 0 then DLOGINT is not pending. 1 then DLOGINT is pending. BERRINTF is the 8th Bit in IFR1 is an Interrupt flag the bus error interrupt, BERRINT If BERRINTF bit is: 0 then BERRINT is not pending. 1 then BERRINT is pending. To clear these flags to 0 (and clear the corresponding interrupt request), write a 1 to the bit.
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These are flag bits in IFR1 or IFR0 If Interrupt flag IFx is:
0 then the interrupt associated with interrupt vector x is not pending. 1 then the interrupt associated with interrupt vector x is pending.
To clear a flag bit to 0 (and clear its corresponding interrupt request), write a 1 to the bit.
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To enable a maskable interrupt, set its corresponding bit in IER0 or IER1 to 1. To disable a maskable interrupt, clear its corresponding enable bit to 0. At reset, all the IER bits are cleared to 0, disabling all the maskable interrupts. IER1 and IER0 are not affected by a software reset instruction or by a DSP hardware reset. Initialize these registers before you globally enable (INTM = 0) the maskable interrupts.
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RTOSINTE, DLOGINTE, BERRINTE and IE16IE23 Bits in IER1 & IE2IE15 Bits in IER0 RTOSINTE is the Enable bit for the real-time operating system interrupt,RTOSINT DLOGINTE is the Enable bit for the data log interrupt, DLOGINT BERRINTE is the Enable bit for the bus error interrupt, BERRINT IE16IE23 bits are enable flags interrupt associated with interrupt vector x. IE2IE15 bits are enable flags interrupt associated with interrupt vector x.
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DBIER1 and DBIER0 are used only when the CPU is halted in the real-time emulation mode of the debugger. A maskable interrupt enabled in a DBIER is defined as a time-critical interrupt. When the CPU is halted in the real-time mode, the only interrupts that are serviced are timecritical interrupts that are also enabled in an interrupt enable register (IER1 or IER0). Write the DBIERs to enable or disable timecritical interrupts. To enable an interrupt, set its corresponding bit.
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The four 16-bit registers (ST0_55, ST1_55, ST2_55 and ST3_55) contain control bits and flag bits Control bits affect the operation of the C55x DSP Flag bits reflect the current status of the DSP or indicate the results of operations. ST0_55, ST1_55, and ST3_55 are each accessible at two addresses
At one address, all the TMS320C55x bits are available. At the other address (the protected address), some of the bits cannot be modified. The protected address is provided to support TMS320C54x code that was written to access ST0, ST1, and PMST (the C54x counterpart of ST3_55).
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ST0_55 Contents
ACOV0, ACOV1, ACOV2, and ACOV3 bits give for each of the four accumulators its own overflow flag CARRY: this bit is the Carry/borrow detection and depends on the M40 bit in ST1_55:
M40 = 0: Carry/borrow is detected with respect to bit position 31. M40 = 1: Carry/borrow is detected with respect to bit position 39.
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DP is a copy in ST0_55 of the 9 most significant bits of the data page register (DP) This 9-bit field is provided for compatibility with the TMS320C54x DSPs. TMS320C55x DSPs have a data page pointer independent of ST0_55.
Any change to bits 157 of the data page register DP(157) is reflected in the DP status bits. Any change to the DP status bits is reflected in DP(157).
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TC1 and TC2 are Test/Control flag The main function of a test/control bits is to hold the result of a test performed by specific instructions. All the instructions that affect a test/control flag allow you to choose whether TC1 or TC2 is affected. TCx (where x = 1 or 2) or a Boolean expression of TCx can be used as a trigger in any conditional instruction. You can clear and set TC1 and TC2 with the following instructions:
o o o o
BCLR TC1 ; Clear TC1 BSET TC1 ; Set TC1 BCLR TC2 ; Clear TC2 BSET TC2 ; Set TC2
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ASM is the Accumulator shift mode bit In the TMS320C54x-compatible mode , ASM supplies a shift value in the range 16 through 15 (5 bits in 2s complement). If C54CM=1: C54x code running on the C55x DSP, and ASM contains the shift count for instructions that specify a shift of an accumulator value. If C54CM = 0: ASM is ignored and the shift count for an accumulator shift operation comes from the temporary register (T0, T1, T2, or T3) specified in the C55x instruction or from a constant embedded in the C55x instruction.
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BRAF: Block-repeat active flag is used in the TMS320C54x-compatible mode (C54CM = 1). BRAF indicates/controls the status of a block-repeat operation. If C54CM = 1 (C54x mode): BRAF is saved and restored with ST1_55 during context switches caused by calls, interrupts, and returns. BRAF is automatically cleared when a far branch (FB) or far call (FCALL) instruction is executed. If C54CM = 0: BRAF is not used. The status of repeat operations is maintained automatically by the CPU (see CFCT ) To stop or set an active block-repeat operation in the C54x-compatible mode, you can use the following instruction:
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C16 is the Dual 16-bit arithmetic mode bit used in the C54x-compatible mode (C54CM = 1), execution of some instructions is affected by C16. The arithmetic performed in the D-unit ALU depends on C16:
If C16 =0 then for an instruction that is affected by C16, the D-unit ALU performs one 32-bit operation (double-precision arithmetic) . If C16=1 then an instruction that is affected by C16, the D-unit ALU performs two 16-bit operations in parallel (dual 16-bit arithmetic).
If C54CM = 0: The CPU ignores C16. The instruction alone determines whether dual 16-bit arithmetic or 32-bit arithmetic is used.
You can clear and set C16 with the following instructions:
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C54CM is the TMS320C54x-compatible mode bit The C54CM bit determines whether the CPU will support code that was developed for a TMS320C54x DSP: If C54CM=0 then the CPU supports code written for a TMS320C55x (C55x) DSP. If C54CM=1 then you can use code that was originally developed for a TMS320C54x (C54x) DSP. In C54 mode all the C55x CPU resources remain available; the additional features on the C55x can be used for code optimization. Change modes with the following instructions and assembler directives:
BCLR C54CM ; Clear C54CM (happens at run time) BSET C54CM ; Set C54CM (happens at run time)
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CPL is the Compiler mode bit and determines which of two direct addressing modes is active: CPL=0 then Direct accesses to data space are made relative to the data page register (DP). CPL=1 then Direct accesses to data space are made relative to the data stack pointer (SP). The DSP is said to be in compiler mode. Change modes with the following instructions and assembler directives: BCLR CPL ; Clear CPL (happens at run time) BSET CPL ; Set CPL (happens at run time)
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FRCT is the Fractional mode bit that sets the fractional mode on or off: FRCT=0 then results of multiply operations are not shifted. FRCT=1 then results of multiply operations are shifted left by 1 bit for decimal point adjustment.
This is required when you multiply two signedQ15 values and you need a Q31 result.
BCLR FRCT ; Clear FRCT BSET FRCT ; Set FRCT
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HM Bit of ST1_55
HM is the Hold mode bit used when the DSP acknowledges an active HOLD signal. It places its external interface in the highimpedance state. Depending on HM, the DSP may also stop internal program execution: HM=0 then the DSP continues executing instructions from internal program memory. HM=1 then the DSP stops executing instructions from internal program memory. To clear and set HM:
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INTM is the Interrupt mode bit, it globally enables or disables the maskable interrupts. If INTM =0 All unmasked interrupts are enabled. If INTM=1 All maskable interrupts are disabled. Software interrupt instruction and software reset instruction, set INTM before branching to the interrupt service routine. Before executing an interrupt service routine (ISR), the CPU automatically sets the INTM bit to globally disable the maskable interrupts. The ISR can reenable the maskable interrupts by clearing the INTM bit. BCLR INTM ; Clear INTM BSET INTM ; Set INTM A return-from-interrupt instruction restores the INTM bit from the data stack.
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M40 is the computation mode bit for the D unit M40 bit selects one of two computation modes for the D unit: If M40=0 then the sign bit is extracted from bit position 31:
During arithmetic, the carry is determined with respect to bit position 31. Overflows are detected at bit position 31. During saturation, the saturation value is 00 7FFF FFFFh (positive overflow) or FF 8000 0000h (negative overflow). Accumulator comparisons versus 0 are done using bits 310. Shift or rotate operations are performed on 32-bit values.
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M40 Bit
An accumulators sign bit is extracted from bit position 39. Accumulator comparisons versus 0 are done using bits 390. Signed shifts are performed as if M40 = 1.
M= 40-bit mode. In this mode the sign bit is extracted from bit position 39, the same as before on 40 bits. To clear and set M40 :
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SATD is the Saturation mode bit, it determines whether the CPU saturates overflow results in the D unit: SATD =0 No saturation is performed. SATD=1 If an operation result gives an overflow, the result is saturated. The saturation depends on the value of the M40 bit:
M40 = 0 The CPU saturates the result to 00 7FFF FFFFh (positive overflow) or FF 8000 0000h (negative overflow). M40 = 1 The CPU saturates the result to 7F FFFF FFFFh (positive overflow) or 80 0000 0000h (negative overflow). BCLR SATD ; Clear SATD BSET SATD ; Set SATD
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SXMD is the Sign-extension mode bit. It sets and resets the sign-extension mode, which affects accumulator operations that are performed in the D unit: If SXMD=0 then sign-extension mode is off: For 40-bit operations, 16-bit or smaller operands are zero extended to 40 bits. For the conditional subtract instruction, any 16-bit divisor produces the expected result. When the D-unit arithmetic logic unit (ALU) is locally configured in its dual 16-bit mode, 16-bit values used in the higher part of the Dunit ALU are zero extended to 24 bits.
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SXMD
If SXMD=1 then 40-bit operations, 16-bit or smaller operands are sign extended to 40 bits. When the D-unit ALU is locally configured in its dual 16-bit mode, 16-bit values used in the higher part of the D-unit ALU are sign extended to 24 bits. 16-bit accumulator halves are sign extended if they are shifted right. During a signed shift of an accumulator, if it is a 32bit operation (M40 = 0), bit 31 is copied into the accumulators guard bits (3932). Set and reset SXMD by:
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XF Bit of ST1_55
The XF bit is a general-purpose output bit that can be manipulated by software and exported to XF pin of the DSP To clear and set XF:
BCLR XF ; Clear XF BSET XF ; Set XF
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AR0LCAR7LC Bits are the linear/circular configuration bits of the eight auxiliary registers, AR0AR7.
If ARnLC= 0 ARn is used for linear addressing If ARnLC=1 ARn is used for circular addressing
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ARMS AR mode switch bit determines the CPU mode used for the AR indirect addressing mode: ARMS=0 DSP mode operands , provides efficient execution of DSP intensive applications. Among these operands are those that use reverse carry propagation when adding to or subtracting from a pointer. Short-offset operands are not available. ARMS=1 Control mode operands , enables optimized code size for control system applications. The short-offset operand *ARn(short(#k3)) is available.
BCLR ARMS ; Clear ARMS (happens at run time) .ARMS_off ; Tell assembler ARMS = 0 BSET ARMS ; Set ARMS (happens at run time) .ARMS_on ; Tell assembler ARMS = 1
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CDPLC is the CDP linear/circular configuration bit. It determines whether the coefficient data pointer (CDP) is used for linear addressing or circular addressing:
CDPLC=0 Linear addressing CDPLC=1 Circular addressing
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DBGM: Debug mode bit gives the ability to block debug events during time-critical portions of a program: If DBGM=0 Debug is enable If DBGM=1 Debug is disable, emulator cannot access memory or registers. Software breakpoints still cause the CPU to halt, but hardware breakpoints or halt requests are ignored. Before interrupt service routine CPU sets the DBGM bit to disable. Return-from-interrupt instruction restores the DBGM bit from the data stack.
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EALLOW is the Emulation access enable bit. It enables or disables write access to non-CPU emulation registers:
RDM, Rounding mode bit, defines the type of rounding performed by the CPU:
If RDM =0 the mode is Round to the infinite. CPU adds 8000h (215 ) to the operand then clears bits 15 through 0 to generate a rounded result in a 24- or 16-bit representation.
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CACLR, Cache clear bit, enables to check when the process for clearing the program cache is complete:
CACLR=0 Complete. The cache hardware clears the CACLR bit when the process is complete. CACLR=1 Not complete. All cache blocks are invalid. The number of cycles needed to clear the cache depends on the memory architecture.
If cache is cleared, the content of the prefetch queue in the instruction buffer unit is automatically flushed. CACLR bit can be changed (pipeline protect):
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CAEN is the Cache enable bit that enables or disables the program cache: CAEN =0 then cache is disabled. All program requests are handled either by the internal memory or the external memory, depending on the address decoded. CAEN=1 Cache is enabled. Program code is fetched from the cache, from the internal memory, or from the external memory, depending on the address decoded.
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CAFRZ is Cache freeze bit that freezes the program cache. IF CAFRZ =0, the cache is in its default operating mode (updated) If CAFRZ=1, the cache is frozen (the cache content is locked). To change CAFRZ bit use:
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CBERR is the CPU bus error flag The CBERR bit is set when an internal bus error is detected. An error causes the CPU to set the bus error interrupt flag (BERRINTF) in IFR1. The interrupt service routine for the bus error interrupt (BERRINT) must clear the CBERR bit before it returns control to the interrupted program using: BCLR CBERR ; Clear CBERR If CBERR =0 The flag has been cleared by program or by a reset. CBERR=1 An internal bus error has been detected.
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CLKOFF bit disables CLKOUT If CLKOFF = 1, the output of the CLKOUT pin is disabled and remains at a high level. Set and clear by:
BCLR CLKOFF ; Clear CLKOFF BSET CLKOFF ; Set CLKOFF
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HINT: Host interrupt bit is used to send an interrupt request to a host processor by the way of the host port interface. To produce an active-low interrupt pulse clear and then set the HINT bit: BCLR HINT ; Clear HINT BSET HINT ; Set HINT
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MPNMC defines the Microprocessor / Microcomputer mode MPNMC reflects the logic level on the MP/MC pin when the pin is sampled at reset
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SATA is the Saturation mode bit for the A unit SATA bit determines whether the CPU saturates overflow results of the A-unit arithmetic logic unit (A-unit ALU): If SATA=0 No saturation is performed. If SATA=1 On. If result is in overflow, result is saturated to 7FFFh or 8000h (for positive or negative overflow respectively). Can be cleared and set by:
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SMUL is the Saturation-on-multiplication mode bit: If SMUL =0 Off If SMUL =1 On. SMUL=1 forces the product of the two negative numbers to be a positive number. For multiply-and-accumulate/subtract instructions, the saturation is performed after the multiplication and before the addition/subtraction.
Clear and set SMUL with :
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SST is the Saturate-on-store mode bit used in the C54-compatible mode (C54CM=1) If C54CM=0 SST is ignored by the C55x. If C54CM = 1: SST turns the saturation-onstore mode on or off. SST= 0 no saturation SST=1 CPU saturates a shifted or unshifted accumulator value before storing it. The saturation depends on the value of the signextension mode bit (SXMD)
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