Microprocessors & Microcomputers (Intel 8085)

KL3193

SERIAL I/O
BASIC
CONCEPTS
1 Iskandar Yahya
iskandar@vlsi.eng.ukm.my
03-89216591
EXTRA LECTURE…….

Day Time Venue

Tuesday 2-3 pm DK2
3-4 pm DK1
Wednesday 10-11 pm DK1
1-2pm DK2
4-5pm DK1
Thursday 10-11pm DK1
1-5pm DK1
2-5pm DK2
2
Friday 3-5pm DK1
INTRODUCTION
We've discussed parallel I/O mode (eight bits
transferred on eight data lines at the same time).

 Not always practical and sometimes impossible

 Can be expansive over long distances
 CRT terminal, cassette players, other analogue
peripherals do not support parallel data transfer
 Need to use serial I/O mode

 Serial mode: One bit at time transferred on the same

(one) data line at a rate called Baud

 Processes: parallel-to-serial conversion, serial-to-

3
parallel conversion, and error checking
INTRODUCTION
Objectives:

 How serial data transfer work and the differences

 Explain the terms synchronous and asynchronous
transmission, simplex, half and full duplex
transmission, ASCII code, Baud rate and parity check.
 Understanding how data bits are transferred and the
requirements
 Write instruction to transmit and receive data using
serial lines (SID and SOD)

4
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

This section:

 Interfacing requirements
 Alphanumeric codes

 Transmission format

 Error checks in data communication

 Data communication over telephone lines

 Standards in serial I/O

 Software vs. programmable hardware

approaches
5
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Interfacing Requirements:
 The interfacing requirements for serial I/O is more or
less the same as parallel I/O.
 MPU identifies the device through the port address
and use Read and Write control signal to control it
accordingly.
 But instead of using the entire data bus, serial I/O
uses only one data line
 MPU select I/O device through Chip Select
 Address decoding can either be Peripheral I/O or
Memory Mapped I/O

6
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Alphanumeric Codes
 Binary representation of alphabets and numbers as on
your keyboard
 Coding used: ASCII (American Standard Code for
Information Interchange)
 7-bit code with 128(27) combinations, each
combination from 00H to 7FH is assigned to a letter, a
decimal number, a symbol or a machine command
 Refer Appendix E page 735 of Gaonkar book
 Devices that use ASCII: Printers, teletype machines,
keyboards

7
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Transmission Format
Synchronous Vs. Asynchronous Transmission

 Synchronous
 Transmitter and receiver are synchronized
 A block of characters is transmitted along with the
synchronization information

Clock

Tx S
ync
S
ync
Rx
Data
Start Time
8
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Transmission Format
Synchronous Vs. Asynchronous Transmission

 Asynchronous
 Character oriented, one character is sent at a time
 Each character carries the Start and Stop
information
 Framing - A low Start bit followed by eight
character bits and ends with two Stop bits
Marking
Start

Stop
Tx D0 D1 D2 D3 D4 D5 D6 D7
Bits Rx
CLK ASCII CLK
Character

Time 9
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Format Synchronous Asynchronous

Data Group of characters Once character at a
Format
Speed High (20 k bits/s or time
20 k bits/s or lower
higher)
Framing Sync characters are Start and Stop bits are
Information sent with each group sent with each
Implement Hardware character
Hardware or Software
ation
Data Simplex, Half and Simplex, Half and Full
Direction Full Duplex Duplex

10
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Simplex and Duplex Transmission

 Simplex transmission - Data transmitted in

one direction. E.g. Computer to printer

 Duplex transmission - Data flow in both

direction. In duplex, there is Half-Duplex
where data goes one way at a time and Full
Duplex, data goes both ways simultaneously.
Communication between 2 computers are full
duplex.
11
SERIAL I/O
BASIC CONCEPTS OF SERIAL I/O

Rate of Transmission (BAUD)

 In parallel I/O, data transfer takes place in three T-
cycles
 But for Serial I/O, the time a bit stays on or off is
determined by the speed at which the speed it
transmitted
 BAUD is defined as signal change/second.

 Transmitter and receiver must work at the same BAUD

rate
 Take the asynchronous transmission as an example:

 Need to transmit 11 bits including the start and

stop bits at 1200 baud
 So effectively, 1200 bits are sent every 1 second
12
 The delay between two successive bits are 1/1200
= 0.0008 s or 0.83 ms.
SERIAL I/O
ERROR CHECK IN DATA COMMUNICATION

Parity Check
 An ACSII code contains 8-bit character data. The
number of 1's can either be an odd number or even
number
 D7 bit (MSB) is used to flag whether there is an odd or
even number of 1's.
 In Even parity system:

 The total number of 1's must be even, including the

D7 bit.
 If the code has even number of 1's, D7 remains 0.
Otherwise it will become 1.
 E.g. Character I is 49H (01001001) with three 1's.
So before transmission, D7 will be set to 1 so that
there's even number of 1's (i.e. 11001001) 13
SERIAL I/O
ERROR CHECK IN DATA COMMUNICATION

 For even parity system, if the total number of 1's

received at the receiver is an odd number, then it
knows that error has occurred, therefore it will ask
the transmitter to retransmit the data.

 In Odd parity system:

 The same principles as the even parity
system, but with the number of 1's for
every transmission should be odd.

14
SERIAL I/O
ERROR CHECK IN DATA COMMUNICATION

Checksum

 Used when blocks of data are sent - useful for simple

synchronous transmission
 Involves adding all the bytes in a block without
carries.
 The 2's compliment of the sum (negative of the sum)
is transmitted as the last byte.
 The receiver adds all the bytes and the result should
be zero if there is no error in the block

15
SERIAL I/O
ERROR CHECK IN DATA COMMUNICATION

Cyclic Redundancy Check (CRC)

 Usually used in data transfer from and to a floppy disk

- synchronous data communication
 Based on mathematical relationship of polynomials
 A stream of data is represented as a polynomial that is
divided by a constant polynomial
 The remainder, unique to that set of bits is generated
 This remainder is sent out as a check for errors.
 The receiver use the remainder to detect errors in
transmission
 Complex mathematical algorithm
16
SERIAL I/O
COMMUNICATION USING TELEPHONE LINE

Data Communication over Telephone Lines

 Data can be sent over long distances through
telephone lines
 But, telephone lines are for voice transmission
(bandwidth 300 Hz to 3300Hz)
 Digital signals requires bandwidth of several
megahertz
 Data bits need to be converted into audio tones - use
Modem
 A modem (Modulator/Demodulator) translate between
audio tones and digital signals
 Two types of modulation techniques are used:

 Frequency Shift Keying - FSK (low speed modems)

17
 Phase Shift Keying - PSK (high speed modems)
SERIAL I/O
STANDARDS IN SERIAL I/O

 A standard may include such items as assignment of

pins positions for signals, voltage levels, speed of data
transfer etc.
 Serial I/O, data transmitted as current or voltage
 20mA (or 60mA) current loops are used in teletype
equipment:
 When the signal is 1 (mark), current flow, when
signal is 0 (space) current flow is interrupted
 Current loop method is noise-free and can be used
for long distance
 Data as voltage:
 Standard called RS232C - max 20 kBaud and a
distance of 50 ft
 Primary focus is to have a compatibility between a 18

terminal and a modem

 For higher speed data transmission, use RS422A
 SERIAL I/O
STANDARDS IN SERIAL I/O

Specification RS-232C RS-422A RS-423A

Speed 20 kBaud 10 Mbaud at 40 100 kBaud at
ft 30 ft
    100 kBaud at 1 kBaud at
4000 ft 4000 ft
Distance 50 ft 4000 ft 4000 ft
Logic 0 > +3 to B > A* +4 to +6 V
+25 V
Logic 1 < -3 to -25 B < A -4 to -6 V
Receiver Input V
+- 15 V +- 7 V +- 12 V
Voltage
* B and A are differential input to the Op amp.
19
SERIAL I/O
REVIEW OF IMPORTANT CONCEPTS

 Serial data transmission can either be implemented

through Hardware (programmable I/O devices) or
software
 Both are conceptually the same.

 In asynchronous data transmission:

 Inform the receiver of the beginning and the end of
the transmission and the parity check
 Convert a parallel word into a stream of serial bits
 Transmit one bit at a time with appropriate time
delay, using one data line of an output port. The
time delay is determined by the speed of the
transmission 20
SERIAL I/O
REVIEW OF IMPORTANT CONCEPTS

 In data reception, the above steps are

reversed:
 Recognize the beginning of the
transmission
 Receive serial bits, one at a time, and
convert them into parallel byte
 Check for errors and recognize the end of
the transmission

21
SERIAL I/O
REVIEW OF IMPORTANT CONCEPTS

Software approach:
 Speed of transmission is set up by using an
appropriate delay between the transmission
consecutive bits, set up by the software
 The entire word is converted into a serial stream by
rotating the byte and outputting one bit at a time,
including the framing bits and the parity bits.
 Suitable for slow-speed asynchronous data
communication where timing requirements are not
critical
 Simple and inexpensive
 Useful in understanding the concepts of serial I/O

22
SERIAL I/O
REVIEW OF IMPORTANT CONCEPTS

Hardware approach:
 Use peripherals to (PPD) for data transfer
 The device contain parallel-to-serial register and 1-
bit output port for transmission
 For reception, use serial-to-parallel register and 11-
bit input port
 Rate of transmission and reception is determined
by the clock
 Data framing and adding error checking
information can be programmed on a control
register
 MPU only transfer data in parallel data bus, the
programmable device/block does the serial I/O
functions 23
 Flexible and reprogrammable
 Widely used in industrial and commercial products
SERIAL I/O
SOFTWARE-CONTROLLED ASYNCHRONOUS SERIAL I/O

The program written must be able to do the

following:

 Output a Start bit

 Convert the character to be sent in a stream
of serial bits with appropriate delay
 Add parity information if necessary

 Output one or two Stop bits

24
SERIAL I/O
SOFTWARE-CONTROLLED ASYNCHRONOUS SERIAL I/O

Serial Data Transmission

 When no transmission, the transmit line of the output port
stays high - Mark position
 Transmission begins with Start bit - Active Low

 Initialization block includes setting up counter to count eight

character bits (D0 - D7) - Start and Stop bits are sent out
separately
 Program waits for bit time delay - 0.833 ms for 1200 Baud -
then send one character at a time over data line D0
 Rotates to the next bit - D1 into D0
 Repeat sending all 8 bits, and then sends out the two Stop
bits
 If output is a printer, then it waits until it receives the Stop
25
bits before printing
 Stop bits - To allow time for printer to print or process data ,
SERIAL I/O
SOFTWARE-CONTROLLED ASYNCHRONOUS SERIAL I/O

Serial Data Reception

 Read input port, if no data received, input line stays high

 Stays in the loop and continue to read the port until

receives Start bit (active low)
 When received Start bit, wait for half the bit time and
samples the character bits in the middle of the pulse to
avoid error
 Initialize counter to count 8 bits and clears the register to
save the partial reading
 Continue reading the input port every interval of bit time
until all 8 bit characters are read
 Receives the D bit first
0

 D7 is used as the reception data line 26

 Transm Receiv
it e

•Set up
Character Bit Read Output
Counter Port
•Send Start Bit
NO Is It
Wait Bit Time Start
Bit?
YES Return
Get Character
in Accumulator Wait For Half
Bit Time
•Check Parity if
Output Bit Necessary
NO Is Bit •Wait for Two
Using D0 Still
Stop Bits
Low
Return
YES
Wait Bit Time YES
•Set up Bit Is It
NO
Counter Last
•Rotate Next •Add Parity if •Clear Register to Bit?
Bit in D0 Necessary Save Bits
• Decrement •Send Two Stop
Bit Counter Bits •Get Ready To
• Wait Bit Time
Receive Next
• Read Input
Bit
Port
Is It •Decrement
NO • Save Bit
Last Counter
Bit?

(a) Transmission (b) Reception

SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES

SOD and SID Lines

 The 8085 has two pins specially designed for

software-controlled serial I/O. One is called SOD
(Serial Output Data), and the other is called SID
(Serial Input Data).

 Data transfer is controlled through two

instruction: SIM and RIM. These instructions are
used for interrupt and serial I/O. We will look at
the serial I/O uses.
28
 SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES

Serial Output Data (SOD)

 The instruction SIM is necessary to output data serially
from the SOD line
 Example Instruction :

MVI A,80H ;Set D7 in the accumulator = 1

RAR ;Set D6 = 1 and bring Carry into
SIM D7
;Output D7

In the above set of D7 D6 D5 D4 D3 D2 D1 D0

instructions, the serial SOD SDE
output line is enabled by
rotating 1 into bit position For Interrupts
D6; the instruction SIM Serial
1 = Enable SOD
Output
outputs the Carry bit Data 0 = Disable SOD
29
through bit position D7
SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES

Serial Input Data (SID)

 The Instruction RIM is used to input serial data through
the SID line.
 Similar to instruction IN, except that RIM reads only one
bit and places it in the accumulator at D7.
 The SID and SOD lines in 8085 eliminate the need to an
input port and an output port in the software-controlled
serial I/O
 Essentially, SID is a 1-bit input port and SOD is a 1-bit
D7 D6 D5 D4 D3 D2 D1 D0
output port
SID

Interrupt Status : Read the SID line and

place the bit in the 30
Serial Input Data accumulator at D7
SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES

Example Illustration: Data Transmission Using the

SOD Line
 
Problem:
 Write a subroutine to transmit an ASCII character, stored
in register B, using the SOD line as a 1-bit output port
 
Solution
 Subroutine:
 The subroutine can follow the flowchart given on slide #

 Set the counter for 11 bits and repeat the loop 11 times.
The Start and Stop bits are included with the character.
For Stop bits, the 2 1's are set up by instruction STC (set
31
carry)
 Example in transmitting the ASCII letter G stored in
register B:
 SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES
*Content of register B: 47H (01000111)

SODATA: MVI C,0BH ;Set the counter C to count eleven bits

  XRA A ;Reset Carry 0
NXTBIT: MVI A,80H ;Set D7 = 1 in the accumulator
  RAR ;Bring Carry in D7 and set D6 = 1 (shift)
  SIM ;Output D7
  CALL BITTIME ;Wait for 9.1 ms
  STC ;Set Carry = 1
  MOV A,B ;Place ASCII character in the accumulator
  RAR ;Place ASCII bit D0 into the Carry, Shift 1 in D7,
    ; and continue shifting for each loop
  MOV B,A ; Save current content of accumulator
  DCR C ;One bit transmitted, decrement counter
  JNZ NXTBIT ;If all the bits are not transmitted, go back to NXTBIT
32
  RET  
Description: 0 1 0 0 0 1 1 1 --> ASCII of
letter G

CY D7 D6 D5 D4 D3 D2 D1 D0 (A)
XRA 0 0 0 0 0 0 0 0 0
MVI A,80H 0 1 0 0 0 0 0 0 0
RAR 0 0 1 0 0 0 0 0 0
SIM 0 ----> sent out (SOD) Start Bit
STC
MOV A,B 1 0 1 0 0 0 1 1 1
RAR 1 1 0 1 0 0 0 1 1
MOV B,A 1 1 0 1 0 0 0 1 1 (B)
2nd iteration:
MVI A,80H 1 1 0 0 0 0 0 0 0
RAR 0 1 1 0 0 0 0 0 0
SIM 1 ----> sent out (SOD) bit D0 of ASCII
STC
MOV A,B 1 1 0 1 0 0 0 1 1
RAR 1 1 1 0 1 0 0 0 1 33

MOV B,A 1 1 1 0 1 0 0 0 1 (B)

 
SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES

What about for Data Reception using SID line?

 Can use the same principle as the flowchart in slide #

 The difference is in the procedure of saving a bit and

forming a parallel word.
 After the D is read, it is stored in CY using RAL
0

 Problem:
 Receive an ASCII character from an input port

34
 SERIAL I/O LINES
SOD AND SID SERIAL I/O LINES
 Solution Subroutine:

SIDATA: RIM ;Read SID line

  RAL ;Place D7 into CY
  JC SIDATA ;If D7 = 1, this is not a Start bit, go back and read
again
  CALL HAFBIT ;If D7 = 0, this is Start bit; wait for half bit period
  MVI C,09H ;Counter for nine bits
NXTBIT: CALL BITTIME ;Wait for one bit period
  RIM ;Read SID line
  RAL ;Save bit in CY
  DCR C ;One bit is read, decrement counter
  JZ RETURN ; If all bits are read, return to main program
  MOV A,B ;Save the bits saved so far in A
  RAR ;Place the bits saved in CY into position D7 and
    ;shift all other bits by one position 35
  JMP NXTBIT ;Get the next bit in the next iteration
SERIAL I/O
HARDWARE CONTROLLED SERIAL I/O

 The hardware approach has the same principle as discussed

previously
 All the software-controlled functions and requirements are
combined in one chip. These are:
 Input and output ports are required for interfacing
 In data transmission, MPU converts parallel data into
stream of serial bits
 In data reception, the MPU converts serial bits into a
parallel word
 Data transfer is synchronized between the MPU and slow-
responding peripherals through time delays

 An IC called USART (Universal Synchronous/Asynchronous

Receiver/Transmitter) includes all the requirements above in36
one chip
 Intel 8251A USART is a device widely used in serial I/O.
 SERIAL I/O
HARDWARE CONTROLLED SERIAL I/O

8251A Programmable Communication Interface

Programmable chip designed for synchronous and asynchronous

serial data communication. With this device, all the software-
controlled instructions are carried out within the chip and also
some other peripheral chips such as logic gates, decoders etc.

 This device includes 5 sections:

 Read/Write Control Logic
 Transmitter
 Receiver
 Data Bus Buffer
 Modem Control
37
 SERIAL I/O
HARDWARE CONTROLLED SERIAL I/O

Read/Write Control Logic:

 R/W control logic

 Six input signals

 Control logic

 And three buffer registers; data register, status register and

control register

Transmitter:
 Accepts parallel data from 8085 and converts it to serial data
stream
 Two registers; a buffer register to hold the 8-bit data and an
output register to converts the data into serial stream
 MPU writes on the buffer, and if the output register is
38
available, the contents of buffer is transferred to the output
register.
 SERIAL I/O
HARDWARE CONTROLLED SERIAL I/O

Receiver:
 Accepts serial data and converts them into parallel data.

 Two registers; the receiver input register and the buffer

register
 When the input line goes low, it assumes it is a start bit, wait
for half a bit and then samples the line again
 Accepts the following bits, and loads it into the buffer register

 Transfers the parallel byte to the MPU when requested

39
 SERIAL I/O
HARDWARE CONTROLLED SERIAL I/O

Initializing the 8251A:

 MPU must inform 8251A of all details such as mode, baud,
Stop bits, parity etc.
 A set of control words must be loaded into the 16-bit control
register of the 8251A
 MPU must check the readiness of the device by reading the
status register
 Control Words:

 Mode words - Specifies the general characteristics of

operation (Baud, parity, Stop bits)
 Command words - enables data transmission and/or
reception
40