Introduction to the Thumb Instruction Set

History
The 4th generation of ARM cores came out in 1996. The main innovation in this version of the architecture was support for Thumb 16-bit compressed instruction set. Thumb code takes 40% less space compared to regular 32-bit ARM code but is slightly less efficient. In 1999, the 5th generation of the ARM architecture introduced digital signal processing and Java byte code extensions to the ARM instruction set. The most popular implementation of this architecture is the Intel XScale processor. It is used in a variety of high-end embedded devices, including network processors, smart-phones. The 6th generation of the ARM architecture was released in 2001 introducing SIMD instruction set extension, improved Thumb instruction set and multiprocessor support.

What is Thumb?
Thumb is a compressed, 16-bit representation of a subset of the ARM instruction set primarily to increase code density also increases performance in some cases It is not a complete architecture all Thumb-aware cores also support the ARM instruction set therefore the Thumb

The Thumb bit

Thumb provides a subset of the most commonly used 32-bit ARM instructions which have been compressed into 16-bit wide opcodes. On execution, these 16- bit instructions can be either decompressed to full 32bit ARM instructions or executed directly using a dedicated Thumb decoding unit Although Thumb code uses 40% more instructions than equivalent 32-bit ARM code, it typically requires 30% less space. Thumb code is 40% slower than ARM code; therefore Thumb is usually used

Example

Instruction set summary

Mnemonics ADC carry ADD AND bit values ASR B THUMB ISA v1 v1 v1 v1 v1 Description add two 32-bit values and add two 32-bit values logical bitwise AND of two 32arithmetic shift right branch relative logical bit clear (AND NOT) of breakpoint instructions

BIC v1 two 32- bit values BKPT v2

 BLX exchange BX CMN 32-bit values CMP integers EOR two 32-bit LDM words from

v2 v1 v1 v1 v1

branch with link and branch with exchange compare negative two compare two 32-bit logical exclusive OR of values

v1

load multiple 32-bit memory to ARM

 LDR v1 virtual address LSL v1 LSR v1 MOV v1 register MUL v1 MVN v1 bit value into NEG ORR v1 v1

load a single value from a in memory logical shift left logical shift right move a 32-bit value into a multiply two 32-bit values move the logical NOT of 32a register negate a 32-bit value logical bitwise OR of two 32-

 PUSH to the ROR SBC bit

v1 v1 v1

pushes multiple registers stack rotate right a 32-bit value subtract with carry a 32value store multiple 32-bit memory store register to a virtual memory subtract two 32-bit values

STM v1 registers to STR v1 address in SUB v1

ARM-Thumb Interworking ARM-Thumb interworking is the name given to

the method of linking ARM and Thumb code together for both assembly and C/C++. It handles the transition between the two states. Extra code, called a veneer, is sometimes needed to carry out the transition. ATPCS defines the ARM and Thumb procedure call standards. To call a Thumb routine from an ARM routine, the core has to change state. This state change is shown in the T bit of the cpsr. The BX and BLX branch instructions cause a switch between ARM and Thumb state while branching to a routine. The BX lr instruction returns from a routine, also with a state switch if necessary.

 There are two versions of the BX or BLX instructions: an ARM instruction and a Thumb equivalent. The ARM BX instruction enters Thumb state only if bit 0 of the address in Rn is set to binary 1; otherwise it enters ARM state. The Thumb BX instruction does the same. Syntax: BX Rm BLX Rm | label

Syntax: <ADC|ADD|AND|BIC|EOR|MOV|MUL|MVN|NEG|ORR|SBC|SUB> Rd, Rm <ADD|ASR|LSL|LSR|ROR|SUB> Rd, Rn #immediate <ADD|MOV|SUB> Rd,#immediate <ADD|SUB> Rd,Rn,Rm ADD Rd,pc,#immediate ADD Rd,sp,#immediate <ADD|SUB> sp, #immediate <ASR|LSL|LSR|ROR> Rd,Rs <CMN|CMP|TST> Rn,Rm CMP Rn,#immediate MOV Rd,Rn

Data Processing Instructions

Single-Register Load-Store Instructions

Syntax: <LDR|STR>{<B|H>} Rd, [Rn,#immediate]
LDR{<H|SB|SH>} Rd,[Rn,Rm] STR{<B|H>} Rd,[Rn,Rm] LDR Rd,[pc,#immediate] <LDR|STR> Rd,[sp,#immediate]

Multiple-Register Load-store Instructions

Stack Instructions

Software Interrupt Instruction

Thumb Decoding