Timing Variations

IBM Thomas J.
Watson Research Center, Yorktown Heights, NY DAC 2003
Death, Taxes and Failing Chips Chandu Visweswariah
Courtesy C. Visweswariah
2/13/2003
Liang-Teck Pang
Outline
Why do we need Statistical Design? What is a Statistical Timer? Methodologies Wish-list of a statistical timer Synthesis Modeling and characterization Conclusion
2/13/2003
Liang-Teck Pang
Breakdown of Static Timer

Increase in significance and independence of the sources of variation.
Critical dimensions scaling faster than our control of them, eg L/L increasing Within-chip variations are significant, eg Across-the-Chip Linewidth Variation (ACLV), temperature and voltage gradients across chip
Case analysis overly pessimistic & number of sign-off timing runs too large
Pessimistic and Risky!

2/13/2003 Liang-Teck Pang 3
Improvement with Statistics

Reduce inaccuracies in modeling
eg same gate used in a data path and the corresponding clock path that latches it, inaccuracy in modeling cancels out
Treat coupling noise and other noise in probabilistic manner instead of assuming worst case scenario Reduction in number of sign-off timing runs
2/13/2003
Liang-Teck Pang
Statistical Timer
2/13/2003
Liang-Teck Pang
Approaches and Methods

Block Based vs Path Based Performance-space methods vs Parameter-space methods 4-Pronged Effort
Modeling Analysis Methodology Synthesis
2/13/2003
Liang-Teck Pang
Performance-space vs Parameter-space
JPDF of underlying sources of variation
Circuit performance constraints
2/13/2003
Liang-Teck Pang
Methodology
ASIC vs Microprocessor
Risk management with PSROs (Performance-Sensitive Ring Oscillators) and appropriate sign-off criteria Environmental vs. manufacturing variations
2/13/2003
Liang-Teck Pang
Wish List of a Statistical Timer

Correlations Bounded vs statistical analysis Slew and load dependance Within-die variation Accuracy Flexibility
2/13/2003
Liang-Teck Pang
Correlation
Importance of correlations
consider a circuit with 50K latches, each with a setup and hold test, each of which has a 99.99% probability of being met if all tests are perfectly correlated, yield=99.99% if all tests are perfectly independent, yield is 0.005% the truth is closer to the perfectly correlated case!
2/13/2003
Liang-Teck Pang
10
Examples of Correlations
Reconvergent Fanout (path sharing) Clock correlation (commonality between data and clock path) Dependence on global parameters (chip-to-chip, wafer-to-wafer, lot-to-lot) Dependence on proximity (temperature, voltage, ACLV, withindie)
2/13/2003
Liang-Teck Pang
11
Bounded vs Statistical Analysis

Treat each source of variation in either a bounded or statistical manner
Certain variables should be bounded (environmental parameters) Random variables with small variation should be bounded to reduce number of random variables Reduce computation complexity and allows fast initial analysis
2/13/2003
Liang-Teck Pang
12
Slew and Load Dependence

Delay depends on input slew and output load Both vary with process and environment
2/13/2003
Liang-Teck Pang
13
Flexibility
Flexibility
fit well with rest of existing methodology reduce number of timing runs required provide diagnostics
2/13/2003
Liang-Teck Pang
14
Other Attributes
Ability to handle within-die variation Accurate prediction of the tail of the slack distribution
Avoid pessimism Capture correlations
2/13/2003
Liang-Teck Pang
15
Statistical Synthesis
Use statistical timer to determine impact of changes Maximise sharing between launching and capturing paths to minimize effects of variability Error correction and dynamic body bias control Use regular layouts when performance loss is acceptable Tradeoff between catastrophic yield improvement and parametric yield improvement
2/13/2003
Liang-Teck Pang
16
Modeling and Characterization

Statistical model of transistors, gates and wires are required Challenging and difficult task!
2/13/2003
Liang-Teck Pang
17
Conclusion

Outlines importance of statistical timer Describes the desired attributes of a statistical timer
2/13/2003
Liang-Teck Pang
18
Paper Review II
Statistical Delay Computation Considering Spatial Correlation Aseem Agarwal et al, ASP-DAC 2003
2/13/2003
Liang-Teck Pang
19
Outline
Path-Based Statistical Timing Analysis Model Inter and intra-die analysis method Model and analysis of spatial correlations Experimental results Conclusion
2/13/2003
Liang-Teck Pang
20
Path-Based Statistical Timing Analysis

Full-chip analysis reconvergence problem Path-based spatial correlation Goal:
perform statistical analysis on top-k critical paths of a design include all paths that have possibility of being critical formulation of gate length, but extensible to other variations accurate analysis inter- and intra-die variation spatial correlation of intra-die gate length variations slope propagation capacitance variation
Consider in the analysis:

2/13/2003
Liang-Teck Pang
21
Gate Length Model

Considers variation due to inter- and intra-die variations
extend later to spatial correlations
Simplifying assumption Inter-die analysis ( )
all gate delays share a single random variable computed through enumeration of Linter distribution
Intra-die analysis (
multiple independent random variables with identical distribution

Delay Computation Using Sensitivities

Use linear approximation to model functional dependence of delay, slope and capacitance on the dependent parameters
Collect gate delay coefficients w.r.t each intra-die device length
Given mean and sigma for the normal distribution of Lintra,i
2/13/2003
Liang-Teck Pang
23
Spatial Correlation Model
Courtesy A. Agarwal
2/13/2003
Liang-Teck Pang
24
Spatial Correlation Example

The path delay due to spatially correlated device length variation
Delay variation for these gates can be expressed as
Compute analytical solution for the delay distribution
2/13/2003
Liang-Teck Pang
25
Experimental Results
comparison with monte carlo for combined inter- and intra-die variability
Comparison of
traditional approach lumping intra-die variation with inter-die variation proposed approach modeling separate inter- and intra-die gate length variation
2/13/2003
Liang-Teck Pang
27
Results w/ and w/o intra-die variation

Results w/ and w/o intra-die variation

Conclusion
Path-based analysis
A method for computing delay distribution of critical paths Combining inter- and intra-die variations Model for spatial correlations Combined analysis using the above model
2/13/2003
Liang-Teck Pang
30
END
2/13/2003
Liang-Teck Pang
31

Timing Variations

Diunggah oleh

Informasi Dokumen

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Timing Variations

Diunggah oleh

Hak Cipta:

Format Tersedia

IBM Thomas J.

Watson Research Center, Yorktown Heights, NY DAC 2003

Death, Taxes and Failing Chips Chandu Visweswariah

Breakdown of Static Timer

Pessimistic and Risky!

Improvement with Statistics

Approaches and Methods

JPDF of underlying sources of variation

Circuit performance constraints

Wish List of a Statistical Timer

Bounded vs Statistical Analysis

Slew and Load Dependence

Modeling and Characterization

Path-Based Statistical Timing Analysis

Consider in the analysis:

Gate Length Model

Simplifying assumption Inter-die analysis ( )

multiple independent random variables with identical distribution

Delay Computation Using Sensitivities

Collect gate delay coefficients w.r.t each intra-die device length

Given mean and sigma for the normal distribution of Lintra,i

Spatial Correlation Model

Spatial Correlation Example

Delay variation for these gates can be expressed as

Compute analytical solution for the delay distribution

Results w/ and w/o intra-die variation

Results w/ and w/o intra-die variation

Anda mungkin juga menyukai