UNIT IV

Combinational Circuits

Combinational Circuits
A combinational circuit consists of Input variables Logic gates Output variables

Contd.

Adder

Half Adder

Implementation of Half Adder

Full Adder

Contd
S=xyz+xyz+xyz+xyz combining 1 with 4 and 2 with 3 =z(xy+xy)+z(xy+xy) =z (x + y) + z(x + y) = (x + y ) + z The output sum can be expressed as a combination of two half adders,one with in the brackets and the other the whole of the expression as shown in figure

Contd
Carry C=xyz+xyz+xyz+xyz combining 1 with 2 and 3 with 4 = z(xy+xy)+xy(z+z) =z (x + y) +xy Where 1st term is the carry of second half adder and 2nd term is the carry of first half adder.

Implementation of Full Adder

Half Adders Half Adder S=(X + Y) + Z

C= z (x + y) +xy

Parallel Adder

Contd
The A and B variables represent 2 binary numbers to be added. The C variables are the carries. The S variables are the sum bits. C3 C2 C1 C0 A3 A2 A1 A0 = A B3 B2 B1 B0 = B C4 S3 S2 S1 S0 = S

4-bit Adder Example

Half Subtractor
Binary Subtraction Difference for pairs of binary numbers 0-0=0 0 - 1 = 1 with a borrow of 1 1-0=1 1-1=0 Also known as the Half Subtractor Table

Full Subtractor
Binary Subtraction with Borrow All the possible differences for binary numbers with borrows minuend subtrahend borrow difference 0-0-0=0 0 - 0 - 1 = 1 with a borrow of 1 0 - 1 - 0 = 1 with a borrow of 1 0 - 1 - 1 = 0 with a borrow of 1 1-0-0=1 1-0-1=0 1-1-0=0 1 - 1 - 1 = 1 with a borrow of 1 Also known as the Full Subtractor Table

Binary Subtractor
The subtrcation A B can also be done by taking the 2s complement of B and adding it to A because A- B = A + (-B) It means if we use the inverters to make 1s complement of B (connecting each Bi to an inverter) and then add 1 to the least significant bit (by setting carry C0 to 1) of binary adder, then we can make a binary subtractor.

4 bit 2s complement Subtractor

C0=1

Adder-Subtractor Circuit

Decoder

Binary Decoder
Black box with n input lines and 2n output lines Only one output is a 1 for any given input

Logical Symbol
n inputs

Binary Decoder

2n outputs

2-to-4 Binary Decoder

Truth Table:
X 0 0 1 1 Y 0 1 0 1 F0 1 0 0 0 F1 0 1 0 0 F2 0 0 1 0 F3 0 0 0 1

Logical Circuit
From truth table, circuit for 2x4 decoder is:Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)

F0 = X'Y' F1 = X'Y F2 = XY'

Logical Symbol
X Y F0

F3 = XY

2-to-4 Decoder

F1 F2 F3

3-to-8 Binary Decoder

x 0 0 0 0 1 1 1 1

Truth Table: y z F F F F
0 1 2

Logical Circuit
F4 F5 F6 F7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0

F0 = x'y'z' F1 = x'y'z F2 = x'yz' F3 = x'yz F4 = xy'z' F5 = xy'z F6 = xyz'

Logical Symbol
F0 X Y Z F1 F2 F3 F4 F5 F6 F7

3-to-8 Decoder

F7 = xyz

Encoders
If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2n-to-n . The simplest encoder is a 2n-to-n binary encoder One of 2n inputs = 1 Output is an n-bit binary number
Binary encoder

2n inputs

. . .

. . .

n outputs

8-to-3 Binary Encoder

Inputs Outputs

I0 1 At any one time, only 0 one input line has a value of 1. 0 0 0 0 0 0 I

0

I1 0 1 0 0 0 0 0 0

I2 0 0 1 0 0 0 0 0

I3 0 0 0 1 0 0 0 0

I4 0 0 0 0 1 0 0 0

I5 0 0 0 0 0 1 0 0

I6 0 0 0 0 0 0 1 0

I7 0 0 0 0 0 0 0 1

y2 0 0 0 0 1 1 1 1

y1 0 0 1 1 0 0 1 1

y0 0 1 0 1 0 1 0 1

I1 I2 I3

y 2 = I4 + I 5 + I 6 + I7 y 1 = I2 + I 3 + I 6 + I7

I4
I5 I6 I7 y 0 = I1 + I 3 + I 5 + I7

Multiplexer

4 to 1 line Multiplexer

Demultiplexer

Sequential Circuits

Set-Reset Flip-Flop
Consider the following circuit
R
Q R R Q Q

S S Circuit R 0 0 A flip-flop holds 1 "bit". 1 1 S 0 1 0 1 Q

"Bit" ::= "binary digit."

Qn+1 Qn n represents current 1 output. 0 ?(Race Condition)

Symbol n+1 represents output at some future time

Function Table

SR Flip-Flop operation
Assume R and S are initially inactive
R=0 Indicates a stable state at some future time (n+ = now plus)

Q=1

S=0

Q=0 Circuit

R 0 0 1 1

S 0 1 0 1

Qn+1 Qn 1 0 ?

~Q = Q, ie is the complement of Q.

Now assume R goes first to 1 then returns to 0, what happens:

Reset goes active

When R goes active 1, the output from the first gate must be 0. This 0 feeds
R=1 Q=0

S=0

~Q = 1

back to gate 2 Since both inputs are 0 the output is forced to 1

The output ~Q is fed back to gate 1, both inputs being 1 the output Q stays at 0.

R=1

Q=0

S=0

~Q = 1

Reset goes in-active

When R now goes inactive 0, the feedback from ~Q (still 1), holds Q at 0.
The pulse in R has changed the output as shown in the function table:
We went from here To here R 0 0 1 1 S 0 1 0 1 Qn+1 Qn 1 0 ? R=0 Q=0

S=0

~Q = 1

And back again

In that process, Q changed from 1 to 0. Further signals on R will have no effect.

Set the latch

Similar sequences can be followed to show that setting S to 1 then 0 activating S will set Q to a 1 stable state. When R and S are activated simultaneously both outputs will go to a 0
R=1
Q=0

S=1

~Q = 0

When R and S now go inactive 0, both inputs at both gates are 0 and both gates output a 1. This 1 fedback to the inputs drives the outputs to 0, again both inputs are 0 and so on and so on and so on and so on.

The Clocked SR Latch

In some cases it is necessary to disable the inputs to a latch This can be achieved by adding a control or clock input to the latch
When C = 0 R and S inputs cannot reach the latch
Holds its stored value

When C = 1 R and S inputs connected to the latch R

Functions as before
C Q

Clocked SR Latch

R C S

R C

R X 0 0 1 1

S X 0 1 0 1

C 0 1 1 1 1

Qn+1 Qn Qn 1 0 ?

Hold Hold Set Reset Unused

Clocked D Latch
Simplest clocked latch of practical importance is the Clocked D latch
D S

Q
C

Q
R

It means that both active 1 inputs at R and S cant occur. Notice weve reversed S and R so when D is 1 Q is 1.

D Latch
It removes the undefined behaviour of the SR latch Often used as a basic memory element for the short term storage of a binary digit applied to its input Symbols are often labeled data and enable/clock (D and C)
D C

S C R

D X 0 1

C 0 1 1

Qn+1 Qn Hold 0 Reset 1 Set

Circuit

Symbol

Function Table

JK Flip-flop
The most versatile of the flip-flops Has two data inputs (J and K) Do not have an undefined state like SR flip-flops
J Q

Q When J & K both equal 1 the output toggles on theK +ve edge triggered active clock edge JK flip-flop

Most JK flip-flops based on the edge-triggered principle

The C column indicates +ve edge triggering (usually omitted)

J 0 0 1 1 X

K 0 1 0 1 X

Qn+1 Qn 0 1 Qn Qn

Hold Reset Set Toggle Hold

Example JK circuit
J Ck A Q

E
F B

D ~Q

K Assume Q = 0, ~Q = 1, K = 1 Gate B is disabled (Q = 0, F = 1) Make J = 1 to change circuit, when Ck = 1, all inputs to A = 1, E goes to 0, makes Q = 1 Now Q and F are both 1 so ~Q = 0 and the circuit has toggled. J 0 0 1 1 X K 0 1 0 1 X C

Qn+1 Qn 0 1 Qn Qn

Hold Reset Set Toggle Hold

Timing diagram for JK Flip-flop

cloc k

Negative Edge Triggered

Q toggle J=K=1 hold J=K=0 reset J= 0 K=1 set J= 1 K=0

Clock Pulse
The JK flip flop seems to solve all the problems associated with both inputs at 1. However the clock rise/fall is of finite duration. If the clock pulse takes long enough, the circuit can toggle. For the JK flip flop it is assumed the pulse is quick enough for the circuit to change only ideal / actual edge pulse once.

Registers
Register:- Flip-flop we can store data bitwise but usually data does
not appear as single bits. Instead it is common to store data words of n bit with typical word lengths of 4, 8, 16, 32 or 64 bit. Thus, several flip-flops are combined to form a register to store whole data words. Registers are synchronous circuits thus all flip-flops are controlled by a common clock line. The data can be entered in serial(one bit at a time) or in parallel form (all the bit simultaneously) and can be retrieved in the serial and parallel form .Registers are classified depending upon the way in which data are entered and retrieved :-

Serial in, serial out register(SISO) Serial in, parallel out register(SIPO) Parallel in, serial out register(PISO) Parallel in, parallel out register(PIPO)

Shift Registers