ANDHRA PRADESH
Name : K Padmavathi
Designation : lecturer
Branch : E.C.E
Institute : Government polytechnic for women
kakinada
Year/semester : III semester
Subject : Digital Electronics
Subject code : CM -305
Topic : Logic Families
Duration : 60 Minutes
Sub Topic : ECL Gates
Teaching Aids : Tabular forms diagrams
CM305. 26 1
OBJECTIVES
be able to
• Know the working of ECL gate circuit.
• Compare ECL gates with TTL and CMOS gates.
CM305. 26 2
RECAP
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Vcc=GND Vcc=GND
220ohm 245ohm
NOR
output Y1
OR
VBB=-1.3V
output Y2
50kohm
50kohm 50kohm 779ohm
A B C VEE=-5.2V
CM305. 26 5
• The Emitter Coupling does not allow the transistor to
saturate.
• The two voltage levels for the output are about -0.8V
for the high state and -1.8V for the low state.
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• ECL family advantages
1. lowest propagation delay
2. fast switching speed
3. High Fan-Out.
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• For the above reasons ECL is only practicable for
use in fast computing applications.
• The output is high only when all the inputs are low
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• Basically ECL is realized using difference amplifier in
which the emitters of the two transistors are connected.
CM305. 26 9
Comparison of ECL gates with TTL and CMOS
gates
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• The noise margin is about 0.3 volts and not as
good as in TTL gate.
CMOS it is 0.01mw
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• The CMOS fabrication process is simpler than TTL
and ECL and it provides a greater packing density
CM305. 26 12
Comparision of TTL,CMOS and ECL Families
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SUMMARY
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Quiz
(c) TTL
(e) CMOS
(g) ECL
(i) NMOS
CM305. 26 15
Frequently asked questions
CM305. 26 16