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Soham Lodh Asst.

Professor MCKV Institute of Engineering

Overview:
Intel 8086 is a 16bit microprocessor:
16b data registers, 16bit ALU

Width of external data bus:


8086: 16bit 8088: 8bit

Width of external address bus:

16bit+4bit=20bit Some techniques to optimise the CPU performance when its executing programs

Contd
Remember the Fetch-Decode-Execute cycle? Fetching from EXTERNAL MEMORY is

SLOW The 8086/8 used an instruction queue to speed up performance While the processor is decoding and executing an instruction, its bus interface can be reading new instructions, since at that time the bus is not actually in use

8086/8088 Functional Units


Bus Interface Unit(BIU) Fetches Opcodes, Reads Operands, Writes Data

Execution Unit (EU)

8086/8088 MPU

Contd
8086/8088 consists of two internal units
The execution unit (EU) - executes the

instructions The bus interface unit (BIU) - fetches instructions, reads operands and writes results The 8086 has a 6Bit prefetch queue The 8088 has a 4Bit prefetch queue

8086/8088 20-bit Addresses


CS 16-bit Segnment Base Address 0000

IP 16-bit Offset Address

20-bit Physical Address

8086/8 In Circuit (1)


8086/8 microprocessors need support

circuits in a microcomputer system 8086/8 multiplex the address and data buses on the same pins This saves pins but at a price: Demultiplexing logic is needed to build up separate address and data buses to interface with RAMs and ROMs

Pin Diagram
MAXIMUM MODE GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
20 21 1 40

MINIMUM MODE

Vcc AD15 A16,S3 A17,S4 A18,S5 A19,S6 /BHE,S7 MN,/MX /RD

8086

/RQ,/GT0 /RQ,/GT1 /LOCK /S2 /S1 /S0 QS0 QS1 /TEST READY RESET

HOLD HLDA /WR IO/M DT/R /DEN ALE /INTA

8086/8 In Circuit (2)


In Maximum Mode the 8086/8 needs at

least the following: 8288 Bus Controller, 8284A Clock Generator, 74HC373s and 74HC245s With the aid of these devices the 8086 begins to look like the ideal microprocessor we looked at earlier

ALE and Address/data Bus Multiplexing


8086/8 Multiplexes the Address and Data

signals onto the same set of pins Need off-chip logic to separate the signals Transparent latches designed just for address demultiplexing

ALE and 74HC373 Transparent Latch


Clock Address/ Data Bus Address Time Data Time ALE

Output of 74HC373

Microcomputer AddressBus

74HC373 or equivalent

Address/ Data Bus

In0:In7

Q0:Q7

System Address Bus

ALE

LE OE# TriState Control signal, OE#, shown connected to GND for simplicity

Internal Architecture of 8086

BIU Elements
Instruction Queue: the next instructions or data can be

fetched from memory while the processor is executing the current instruction
The memory interface is slower than the processor execution time

so this speeds up overall performance

Segment Registers:
CS, DS, SS and ES are 16bit registers Used with the 16bit Base registers to generate the 20b address Allow the 8086/8088 to address 1MB of memory Changed under program control to point to different segments as a

program executes

Instruction Pointer (IP) contains the Offset Address of the

next instruction, the distance in bytes from the address given by the current CS register

Contd

CS - the Code Segment Register DS - the Data Segment Register SS - the Stack Segment Register ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP,

written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode.

Contd
The EU contains the following 16-bit registers:
AX BX CX DX

- the Accumulator - the Base Register - the Count Register - the Data Register SP - the Stack Pointer BP - the Base Pointer SI - the Source Index Register DI - the Destination Register

Contd
These are referred to as general-purpose registers,

although, as seen by their names, they often have a special-purpose use for some instructions.
The AX, BX, CX, and DX registers can be considered

as two 8-bit registers, a High byte and a Low byte. This allows byte operations and compatibility with the previous generation of 8-bit processors, the 8080 and 8085. The 8-bit registers are:

AX --> AH,AL BX --> BH,BL CX --> CH,CL DX --> DH,DL

Architecture of 8086 (contd..)

Fetching the next instruction while current instruction

is under execution is called pipelining.


When 8086 is reset the contents of IP are 0000 H and

contents of CS are FFFF H. Other registers are cleared to 0000 h.

Memory Segmentation

Advantages of memory segmentation

Allow the memory capacity to be 1Mb even though the

addresses associated with the individual instructions are only 16 bits wide. Facilitate the use of separate memory areas for the program, its data and the stack. Permit a program and/or its data to be put into different areas of memory each time the program is executed. Multitasking becomes easy.

Generation of 20 bit physical address

Flag Register ( PSW)


Bit 0 - CF Carry Flag - Set by carry out of msb Bit 2 - PF Parity Flag - Set if result has even parity Bit 4 - AF Auxiliary Flag - for BCD arithmetic Bit 6 - ZF Zero Flag - Set if result is zero Bit 7 - SF Sign Flag = msb of result Bit 8 - TF Single Step Trap Flag Bit 9 - IF Interrupt Enable Flag Bit 10 - DF String Instruction Direction Flag Bit 11 - OF Overflow Flag Bits 1, 3, 5, 12-15 are undefined.

Addressing Modes
A] Data Category

1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Register Indirect Addressing 5) Register Relative addressing 6) Base Index addressing 7) Relative Base Index addressing

B] Branch Category
1) Intrasegment Direct

2) Intersegment Indirect
3) Intrasegment Direct 4) Intersegment Indirect

INSTRUCTION SET OF 8086


1] Data Transfer 2] Arithmetic 3] Logical 4] Branch 5] Loop 6] Machine Control 7] Flag Manupulation 8] Shift & Rotate 9] String

Instruction Set
MOV: Move

Direct loading of the segment registers with immediate data is not permitted. MOV DS,5000H; IS NOT PERMITTED MOV AX,5000H MOVDS,AX Register : MOV AX,BX Direct: MOV AX, [2000H]

XCHG:

XCHG BX,AX IN AL,03H IN AX,DX

PUSH, POP
LEA: Load effective address LEA BX,ADR

ADD AX, 0100H; immediate ADD AX,BX; register ADD AX, [SI]; register indirect ADD AX, [5000H] ;direct ADD[5000h];0100h ADD 0100H; destination AX (Inplicit) ADC 0100H ;Immedite (Implicit) ADC AX,BX

INC: Increment INC AX ; Register DEC: Decrement DEC AX SUB: Substract SUB AX, 0100H; Immediate SUB [5000h], 0100h; immediate SBB: Substract with borrow SBB AX,BX MUL: Unsigned multiplication MUL BX IMUL: Signed multiplication IMUL CX

THANK YOU