USB Protocol

PC to DSK board communication over a high speed USB link

Bharath Bhushan Lohray Summer II 2009

Objective

EMIF CY7C68013A DSK 6713 Board

PC

Components - USB
PC

CY7C68013A EMIF- FIFO

USB

EP 0 EP1 IN
EP1 OUT

Control Endpoint

EP 2 EP 4

Full & High Speed: Up to 30 endpoints configurable as either IN or OUT Low Speed: 2 additional endpoints

EP 6

Corresponding Slave FIFOs. No access to EP0. CPU only access to EP1

EP 2 EP 4

EP 6
EP 8

DSK 6713 Board

EP 8

Components - USB
PC

CY7C68013A EMIF- FIFO

USB

Endpoint Buffering Schemes

DSK 6713 Board 4

Components - USB
PC

USB

Bulk Mode Packets

CY7C68013A EMIF- FIFO

Interrupt Mode Packets

DSK 6713 Board

Isochronous Mode

Components - USB
PC

CY7C68013A EMIF- FIFO DSK 6713 Board 6

USB

Components - USB
PC Start

Load Configuration Enable Interrupts ReNumerate

Endpoint Interrupts

USB

Service endpoint CY7C68013A EMIF- FIFO Got SUD?

No

Return
Yes

Service Request from Host DSK 6713 Board 7

Components - USB
PC

CY7C68013A EMIF- FIFO DSK 6713 Board

dalida.com technical Specification Sheet

USB

Components - USB
PC

48 MHz

Bus Powered
PB0-PB7 PD0-PD7

USB

External Memory Interface of the DSP

CY7C68013A

EP2 Half Full (>=512 bytes) EP6 Half Full (>=512 bytes) SLRD SLWR SLOE

EXT5 EXT4 CE + ARE CE + AWE CE + AOE

External Interrupt pins of the DSP

CY7C68013A EMIF- FIFO

Signals Generated by the TMS320C6713

DSK 6713 Board 9

Components - PC NI VISA Driver Generation

BhL_CY_FX2 Board.inf BhL_CY_FX2 Board_vista&7.inf USB

CY7C68013A EMIF- FIFO

bcdedit.exe -set TESTSIGNING ON

DSK 6713 Board 10

Components - PC USB Classes & VISA USB Handling

CY7C68013A EMIF- FIFO

USB

Reading & Writing to and from a VISA Resource in Lab View

DSK 6713 Board Opening Generation Waveform& Closing VISA Resource in Lab View 11

Components - DSK
PC
PB0-PB7 PD0-PD7 EP2 Buffer EP6 Buffer DSP Routine DSP Routine EXT5 Triggers EDMA Transfer of 512 bytes from the FIFO to EP2 buffer. On completion, the interrupt is cleared and the EDMA channel is ready for the next transfer request. Tx Ping & Tx Pong buffer data are sent to the codec continuously.

USB

ARE AWE

AOE
CE

CY7C68013A EMIF- FIFO

Tx Ping Tx Pong McBSP

Out
AIC23 Codec

EP2 Half Full (>=512 bytes) EP6 Half Full (>=512 bytes)

EXT5 EXT4

Rx Ping Rx Pong

DSK 6713 Board

In
12

Components - DSK
PC
PB0-PB7 PD0-PD7 EP2 Buffer EP6 Buffer DSP Routine DSP Routine On completion of an Rx ping or Rx pong, the data from the Rx buffers are optionally transferred into the Tx buffers and the DSP routine is called that transfers the data into the EP6 buffer. An EDMA request is then triggered to transfer the EP6 buffer to the FIFO over the EMIF.

USB

ARE AWE

Trigger EDMA

AOE
CE

CY7C68013A EMIF- FIFO

Tx Ping Tx Pong McBSP

Out
AIC23 Codec

EP2 Half Full (>=512 bytes) EP6 Half Full (>=512 bytes)

EXT5 EXT4
Transfer Complete Interrupt

Rx Ping Rx Pong

DSK 6713 Board

In
13

Reference Cypress CY7C68013A Datasheet EZ-USB Technical Reference Manual USB Complete Jan Axelson