RISC CONCEPTS WITH

BY : MAHIN BASHA SYED 1005-10-744406

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 EVOLUTION OF CISC AND RISC CONCEPTS RISC VS CISC INTRODUCTION TO ARM PROCESSOR FAMILY OF ARM BLOCK DIAGRAM OF ARM REGISTERS DIAGRAM 3 STAGE PIPELINED ARM 5 STAGE PIPELINED ARM INSTRUCTION SETS OF ARM
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Out lines

THE ART OF PROCESSOR DESIGN IS TO

cisc evolution

DEFINE AN INSTRN SET THAT SUPPORTS FUNCTIONS

WHAT SORT INSTRN SET MAKES A GOOD

COMPILER TARGET

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WHY DOES COMPILER NEEDED???

THE SEMANTIC GAP BETWEEN A HIGH

LEVEL LANGUAGE CONSTRUCT AND A MACHINE INSTRN IS BRIDGED BY COMPILER

HIGH LEVEL LANGUA GE

COMPIL ER

MACHINE INSTRN SET

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THE

AIM OF PROCESSOR DESIGN SHOULD DEFINE HIS OR HER INSRTN SET TO BE GOOD COMPILER TARGET

COMPILER TARGET ??

COMPLEXITY

SEMANTIC GAP BY COMPILER

THIS LEDS TO THE CISC DEVELOPMEENT

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MINI COMPUTERS DEVELOPED WHICH HAS

MAIN MEMORY CONTROLLED BY MICRO CODE ROMS WHICH ARE FASTER THAN MAIN MEMORY
MINI COMPUTERS USES CISC IN 1970, MICRO PROCESSORS DEVEL0PED

FASTLY IN SEMICONDUCTOR INDUSTRY BUT MICRO CODE ROM IS NEEDED FOR ALL COMPLEX ROUTINES
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WHAT IS CISC ??
CISC is an acronym for Complex Instruction Set

Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive,

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RISC evolution
INSTRN TYPE
DATA MOVEMENT CONTROL FLOW ARITHMETIC OPERATION COMPARISIONS LOGICAL OPERATIONS `OTHERS

DYNAMIC USAGE IN %

43 23 15 13

5 1

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WHAT IS RISC ??
RISC, or Reduced Instruction Set Computer. is a

type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

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Sr. RISC No 1 Simple instructions

taking 1 cycle.

RISC VS CISC
CISC
Complex instructions taking multiple cycles. reference memory.

2 Only LOADS/STORES Any instruction may

reference memory. Not pipelined or less pipelined. 4 Instructions executed Instructions interpreted by the hardware. by the microprogram.

3 Highly pipelined

5 Fixed format
instructions.

Variable 5/6/12 format instructions.

RISC ARCHITECTURAL FEATURES

FIXED LENTH INSTRUCTION

32 BIT
LOAD STORE ARCHITECTURE FEWER ADDRESSING MODES INSTRUCTION PIPELINE LARGE NUMBER OF REGISTERS DELAYED LOADS AND BRACHES SEPARATE INSTRN AND DATA

STREAMS

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EVOLUTION OF ARM
Founded in 1990. ARM -Advanced Risc

Machines

32bit RISC processor from

ARM Holdings.
ARM Holding is a joint

venture between Acron 5/6/12 computers, Apple

features
Features used Features rejected Load - strore Register architecture window Fixed length 32 bit instructions 3 address Delayed branches Single 5/6/12 cycle

cont
The combination of the simple hardware with

an instruction set that is grounded in risc ideas but retains a few key cisc features

The ARM achieves a significantly better code

density and power efficiency and its smalll core size.

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ARM: 32-bit RISC-processor core (32-bit

instructions) available)

37 pieces of 32-bit integer registers (16 Pipelined (ARM7: 3 stages) Cached (depending on the

implementation)
Von Neuman-type bus structure (ARM7),

Harvard (ARM9)
8 / 16 / 32 -bit data types
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family of arm
ARM REVISION ARM V 1 ARM V2 ARM V 2a ARM V 3 ARM V 3M ARM V4 ARM V 4T ARM V5 TE ARM V STEJ ARM V6 PROSCESSORS CORE ARM 1 ARM 2 ARM 3 ARM 6 and ARM 7DI ARM 7M STORNG ARM ARM 7 TDMI and ARM 9T ARM 9E and ARM 10 E ARM 7EJ and ARM 926EJ ARM 11
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NOMENCLATURE
ARM

{X}{Y}{Z}{T}{D}{M}{I}{E}{J}{F}{S}

T: Thumb D: On-chip debug ARM support M: Enhanced multiplier TDM7I I: Embedded ICE hardware T2: Thumb-2 S: Synthesizable code E: Enhanced DSP instruction
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CD CD

DATA

BASIC MODEL OF ARM

SIGN EXTEND WRI ED TE READ REGISTER FILES R0 R15 BARREL SHIFTER ALU ADDRESS REGISTER ADDRESS

INSTRN DECODER Rd

MAC

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3 STAGE PIPELINING

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REGISTERS OF ARM
ARM7 register set
thirty-seven 32bit registers. 30 are general purpose registers 16 general purpose registers(R0 to R15)

are available in ARM-mode (user mode)

Register structure depends on mode of operation R13 - Stack Pointer (SP) R14 - subroutine Link Register for branch and link instructions 5/6/12

Register Organization Summary

Current Visible Registers
Abort Mode
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr

Banked out Registers

User FIQ
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

IRQ

SVC

Undef

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

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processor,processor operation mode,interrupt B3enable bit B28 B2 B25 to B24B8 B7 B6 B5 B0 B30 B29 status,etc.
1 7 B26 to B23 to B4

CPSR holds execution status of the

CPSR-Current program status register

V Q

F T Mod

e Sele ct

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OPERATING MODES
1.

User Mode- Normal program execution state high priority interrupt is raised.

2. Fast Interrupt Processing (FIQ) Mode - when a 3. Normal Interrupt Processing (IRQ) Mode4.

when a normal priority interrupt is raised. Supervisor /Software Interrupt ModeProtected mode for operating system support . Eg: when reset /software interrupt instruction is executed. aborted.

5. Abort Mode - when data or instruction fetch is 6.

5/6/12 System Mode for running Operating system tasks.

7 MODES
User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr spsr spsr spsr spsr

FIQ
User mode r0-r7, r15, and cpsr

IRQ
User mode r0-r12, r15, and cpsr

SVC
User mode r0-r12, r15, and cpsr

Undef
User mode r0-r12, r15, and cpsr

Abort
User mode r0-r12, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

Thumb state Low registers Thumb state High registers

Note: System mode uses the User mode register set

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BARALLEL SHIFTER
LSL : Logical Left Shift
C F

ASR: Arithmetic Right Shift

0

Destination

Destination

LSR : Logical Shift Right

... 0

Multiplication by a power of 2
Destination

C F

Division by a power of 2, ROR: Rotate the preserving Right sign bit

Destination

C F

C F

Division by a power of 2

Bit rotate with wrap around RRX: Rotate Right Extended from LSB to MSB C Destination
F

Single bit rotate with wrap around from CF to MSB

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BARREL SHIFTER
Operand 1 Operand 2
Barrel Shifter

Register, optionally with shift operation

Shift value can be either

be:
5 bit unsigned integer Specified in bottom byte of

another register.

Used for multiplication by

ALU

constant

Result

Immediate value
8 bit number, with a

range of 0-255. 5/6/12

Rotated right through even

PIPELINE CONCEPT IN ARM

Fetch instruction Decode instruction Execute instruction Access operand Write result
Note: Slight variations depending on

processor

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PIPELINE CONCEPT IN ARM WITH OUT PIPELING

Clock Cycle 1 2 3 4 5 6 7 8 9 10

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WITH PIPELING
The processor is able to

perform each stage simultaneously.

If the processor is decoding

an instruction, it may also fetch another instruction at the same time.

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Clock Cycle

1 2 3

4 5 6 7

Instr 1 Instr 2 Instr 3 Instr 4 Instr 5

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3 STAGE PIPELING
FETCH DECOD E FETCH EXECUT E DECOD E FETCH DECODE

EXECUT E

EXECUT E

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WHY 5 STAGE PIPELING

Tprog = Ninst * CPI / fclk
Tprog: the time that executes a given

program

Ninst: the number of ARM instructions

executed in the
program => compiler dependent CPI: average number of clock cycles per

instructions =>
hazard causes pipeline stalls fclk: frequency
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5 STAGE PIPELING
FETC H DECO DE FETC H EXECU TE DECO DE ACCESS OPERAND EXECU TE WRITE

ACCESS OPERAND

WRITE

FETC H

DECO DE

EXECU TE

ACCESS OPERAND

WRITE

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 5 STAGE PIPELING

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INSTRN SETS OF ARM

V

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1. ARM Instruction Set-The original ARM

instruction.Here all instruction are

32bit

wide and word aligned.since all

instructions are word aligned,one single fetch reads four 8bit memory locations.
2. Thumb Instruction Set-These instructions

can be considered as a 16bit compressed form of the orginal 32bit ARM instruction. These instructions can be executed by decompressing the instruction to the original 32bit ARM instructions technique that allows Java Bytecode to be executed directly in the ARM architecturea. 5/6/12

3. 3.Jazelle Instruction Set- Jazelle is a

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Thumb is a 16-bit instruction set

Optimised for code density from C code (~65% of

ARM code size)

Improved performance from narrow memory Subset of the functionality of the ARM instruction
31

ADDS set r2,r2,#1

Core has additional most instructions state - by compiler: For execution generated Thumb
Switch between ARM and Thumb using BX
n n n n
1 5

32-bit ARM Instruction

Conditional execution is not used Only Low registers used Constants are of limited size Inline barrel shifter not used

instruction

Source and destination registers identical

ADD r2,#1

16-bit Thumb Instruction

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5/6/12

ARM10(TDMI) ARM10TDMI processor core: Realizes the ARM instruction set with

binary compatibility including the Thumb

extension Instruction set expanded to version 5

(v5TE), 32x16 MAC-multiplier instructions

6-stage pipeline for fixed point 42 Ville Pietikinen 2002

Embedded_3_ARM_2003.ppt / 19112002

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5/6/12

ADVANTAGES OF ARM
HIGH CODE DENSITY PRICE SENSITIVE HARD WARE DEBUG TECHNOLOGY SMALL AREA

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APPLICATIONS

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THANK U

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