Anda di halaman 1dari 12

# | 


The circuit shown is a CMOS differential stage in which the aspect
ratio W/L is indicated. The NMOS devices have k = 25 0 / V2,
VT = 1.5 V and V0 = 1/ = 50 V; the PMOS devices have k =
12.5 0 / V2, VT = -1.5 V, V0 = 1/ = 100V.
(a)Determine the bias drain currents in 3, 5, and 7.
(b) Evaluate 0DM and the CMRR.



D





h





 h 

 h 
Di









 h 

KVL:



Di

Di

0lso

Di

A h

o


 h

 
o   A


(1)




o h  h A




A



(2)

o h






 
 


Di 
D  
  
  o D
o
o

 
 
 
 
  


 h
o
o  
  h

(3)

## or PMOS current mirror:

Dr





 h

o r

  h

o  h   h  A

 h






A
 A 


o h

 
 
   
 
o
o
o   o
 h   

 
  

h

(4)





o  i i

G
rh

  h  

o    
 
  h 

o 


## Common mode gain 0CM:

  rh
rh

i

A   i

  o  i i o    h  o  


   
o
o 

A  h h
h 

 DD o





o
o  



0ns.

rh

i
h

|  
Each stage of a CE-CE configuration uses transistor 0, and each is
biased at IC = 1 m0. The component values are Rs = 0.6 k,
RC1 = RC2 = 1.2k  .
(a)Determine 0VO and the approximate value of fH.
(b) Estimate the location of the closest nondominant pole.
D
D



D

In a CE-CE configuration


o 

D o  

oD

o  

ind
(i) 0VO & fH

## (ii) location of closest nondominant pole.

-  r




 

 





G



 

 







  r

 




 

 




 






G

 o



o
h h

 o




o 


 h
o
o h


h



o 







 

 



  


   h 

o    o




 
o

h

  
h o
A  h




h
o
A h



from 
from 

A

o 













o A
A A
o   0ns.

h

h


A


h

 

 




A

 D

A

 h





A

h o  h 
h o  r

D o h o  h
 o




D


o





A


D


D

 

h

h

D

 

 
D



## D o D o D   o  h o  h


D o D
o D   D

D




o  h 

  
 o 
h
h



D o D

  o   h o 


oD
D o D

 


  o 


A  D
D  o D  o D

o 
A

  o



 o D

where

D A






 o  h
o  h
 o

  D




h


o

   h




h

D




D



D A



 D









h







## If transistors are assumed to be identical then,

 o

 




 o

 A




or


o



h
  


 
h

o  h r

o  h r   h r


  o

o  h r

o  h r

 
   


o
  o 



0ns.