Logic gate delay  Logic gate power consumption

Delay is one of the most important properties of a logic gate.

Gate delay is measured as the time required for the gate to change its output voltage from a logic 0 to a logic 1or vice versa.

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Solid logic 0/1 defined by VSS/VDD. Inner bounds of logic values VL/VH are not directly determined by circuit properties, as in some other logic families.
VDD

logic 1 Unknown X
VH VL

VSS

logic 0

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Levels at output of one gate must be sufficient to drive next gate. Given our logic design and process parameters, we can guarantee that the max: voltage produced for a logic 1 will be some value VOH and that the min: voltage produced for a logic 0 will be VOL . These same constraints place limitations on the input voltages. If the gates are to work together , we must ensure that VOL < VIL and VOH > VIH .

To compute the values of VIL and VIH ,we need to define those values.

A standard definition is based on the transfer characteristics of the inverter.

Transfer

curve

shows

static

input/output

relationshiphold input voltage, measure output voltage.

Choose threshold voltages at points where slope of transfer curve = -1.

Inverter has a high gain between VIL and VIH points, low gain at outer regions of transfer curve. So that even a large change at the input causes only a small change at the o/p, attenuating the noise at the gates i/p.

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Assume ideal input (step), RC load. RC model is good enough to make a variety of basic design decisions.

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A simple but effective model of delay in logic gate is the (tau) model of Mead and Conway. Assume resistor model for transistor. The transistor does not obey Ohms law as it drives the gates output . As shown in Fig1:, the pulldown spends the first part of the 1 0 transition in the saturation region, then moves into the linear region. But the resistive model will give sufficiently accurate results to both estimate gate delay and to understand the sources of delay in a logic circuit.

As shown in Fig 1: the pulldown spends the first part of the 1 0 transition in the saturation region, then moves to linear region.

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How we do choose a resistor value to represent the transistor over its entire operating range? A standard resistive approximation for a transistor is to measure the transistors resistance at two points in its operation and take the average of the two values. Average V/I at two voltages: maximum output voltage middle of linear region Voltage is Vds, current is given Id at that drain voltage. Step input means that Vgs = VDD always.

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Fig: 2 shows the approximation points for an n-type transistor. The inverters max: o/p voltage, VDS = VDD VSS where the transistor is in the saturation region. The middle of the linear region, VDS = (VDD VSS -Vt)/2

 We will call the first value Rsat = Vsat /Isat And the second value Rlin = Vlin /Ilin .

This gives the basic formula

Vsat Vlin Rn ! I I sat lin 0.5

type Rn Rp

VDD VSS =1V 11.1 k 24.0 k

Load is resistor + capacitor, driver is resistor.

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X model: gate delay based on RC time constant X. The capacitor has an initial voltage of VDD , the transistor discharges the load capacitor from VDD to VSS ; the output voltage as a function of time is: Vout(t) = VDD exp{-t/(Rn+RL)CL}

We typically use RL to represent the resistance of the wire which connects the inverter to the next gate; in this case, assume RL =0, simplifying the total resistance to R = Rn .

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Transition time is calculated as tf = t2 t1. tf = 2.2 R CL For pullup time, use pullup resistance.

What is fall time with 90nm process parameters? Assume a min: size pulldown, no wire resistance and a capacitive load equal to two min: size transistors gate capacitance. Solution The model parameters for 90 nm process:
Rn = 11.1 k; Cl = 0.12 fF
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So
tf = 2.2 x 11.1E3 x 0.12E-15 = 2.9 ps.

Analyzing the power consumption of an inverter provides an alternative window into the cost and performance of a logic gate.

Static CMOS gates are remarkably efficient in their use of power to perform computation.

However, leakage increasingly threatens to drive up chip power consumption.

Dynamic power consumption comes from switching behavior. Static power dissipation comes from leakage currents. Surprising result: dynamic power consumption is independent of the sizes of the pullups and pulldowns. Analysis given here ignores the leakage current.

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Input is square wave. After the o/p capacitance has been fully charged or discharged, only one of the pullup and pulldown transistors is on. Power is consumed when gates drive their output to new values. Power consumption depends only on the size of the capacitive load at the output and the rate at which the inverters o/p switches.

Energy required to charge the capacitor is calculated as: E = CL(VDD - VSS)2

A single cycle requires one charge and one discharge of capacitor, so the total energy consumption is : E = CL(VDD - VSS)2 .

Power is energy per unit time, so the power consumed by the circuit depends on how frequently the inverters output voltage changes. The worst case is that the inverter alternatively charges and discharges its output capacitance. This seeks two clock cycles. Clock frequency f = 1/t. Energy E = CL(VDD - VSS)2. Power = E x f = f CL(VDD - VSS)2.

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Power consumption in CMOS circuits depends on the frequency at which they operate.

This source of the power consumption is known as dynamic power.

Power

consumption

depends

on

operating

frequency.
Slower-running circuits use less power .

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Also known as power-delay product. Helps measure quality of a logic family. For static CMOS:
SP = (1/f )P = CV2.

This result suggests an important method for power consumption reduction known as Voltage scaling. We can often reduce power consumption by reducing the power supply voltage and adding parallel logic gates to make up for the lower performance.