Branch Prediction
13-stage pipeline Cortex-A8 processor implements a two-level global history branch predictor. Branch Target Buffer (BTB) and the Global History Buffer (GHB). The BTB indicates whether or not the current fetch address will return a branch instruction and its branch target address. On a hit in the BTB a branch is predicted and the GHB is accessed. A return stack is used to predict subroutine return addresses. The return stack has eight 32-bit entries.
Thumb-2
Combined 32 and 16 bit instruction set Instructions can be freely mixed 16 bit instructions include the original Thumb instruction set Some new 16 bit instructions for key code size wins Conditional execution made available via IT instruction. ARM = 20 bytes Thumb-2 = 14 bytes CMP r3,#1 ; 4 bytes CMP r3, #1 ;2 bytes EOREQ r1,r1,#0x400 ; 4 bytes ITTET ;2 bytes EOREQ r1,r1,#2 ; 4 bytes MOVWEQ r3, #0x4002 ; 4 bytes MOVNE r3,#0 ; 4 bytes EOREQ r1, r3 ; 2 bytes MOVEQ r3,#1 ; 4 bytes MOVNE r3, #0 ; 2 bytes MOVEQ r3, #1 ; 2 bytes
TrustZone
Architectural extensions to introduce a Security state. Only the secure CPU can access the secure memory & peripherals TrustZone adds a parallel world to run secure OS and applications Normal and Secure worlds have different memory views, enforced by hardware Memory tagged as secure and non-secure by the system Secure Monitor is a software gatekeeper between the two worlds Device integrity, Digital Rights Management, Electronic payment, etc.
TrustZone
Jazelle-RCT
Beneficial to Java and a wide range of emerging languages
Microsoft .NET MSIL, Perl, Python etc.
Small memory footprint result in lower power Broad industry adoption Sun Microsystems, Aplix and Esmertec are early adopters
Cortex-A8 Features
Cortex-A8 Technologies TrustZone Security Jazelle RCT Acceleration Thumb-2 Instruction Set NEON Advanced SIMD(+VFPv3) Superscalar ARMv7 Core Description Device Integrity / Secure Transactions Fast & Responsive Java Applications Greater Performance With Less Code Size Enhanced Multimedia Experience Highest-performance mobile processor
Reference
[1].Design & Test of Computers,IEEE( 10.1109/MDT.2009.19) [2].Test Conference. ITC . IEEE International(10.1109/TEST.2006.297638) [3].http://www.arm.com/products/processors/cortex-a /cortex-a8.php