A BIST Scheme for FPGA Interconnect Delay Faults

Chun-Chieh Wang, Jing-Jia Liou,

Yen-Lin Peng, Chih-Tsun Huang, and Cheng-Wen Wu

Laboratory for Reliable Computing (LaRC) Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan 30013

Outline

Introduction
Objective Proposed BIST architectures Experimental results Conclusions

Introduction
The causes of FPGA delay fault More circuits operating at high speed DSM processes have resulted in more defects affecting the delay FPGA delay testing problem Path delay fault model is not appropriate Segment delay fault model is used At-speed testing is practically difficult Need BIST approach
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Objective
Why test the interconnects of FPGA? Delay faults are mostly associated with interconnects Universal testing method Application-independent testing methodology The objective: A BIST scheme for interconnect delay faults with minimal clock skew effects
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Clock Skew Effect

FF1 D Q A B FF2 D Q

CLK

TAB TCLK TCLK-TSkew

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Proposed BIST Design (BIST1)

Assumptions: The PUT has to be the longest path among all paths in the BIST Ignore skew between FFs in a CLB

PUT
D1 Q1

1 TPG 0 Controller

EC

101 100

D2 Q2

110
CLB

EC

Falling 6

Test Result Observation

Readback mechanism

The two phase approach

D1 Q1 EC
BIST BIST BIST ORA ORA ORA

CLB for BIST

ORA ORA ORA BIST BIST BIST

Go NoGo CLB for ORA

BIST

BIST

BIST

ORA

ORA

ORA

First phase

Second phase

WE and NS Switch Testing Issues

The loop-back PUTs targeting WE and NS are
too long Shorter PUTs are connected between different CLBs Need to validate clock skews
PUT

CLB

WE CLB

CLB

WE CLB

PUT
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Clock Skew Validation

Using tested paths to validate clock Change test clock: TCLK = TCLK + TSkew Violations can be detected when they cause strobe time to be earlier than TPath Shortest path has small TSlack to detect small violations
TCLK TCLK Undetectable detectable
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TPath

TSlack

Modified BIST Design (BIST2)

Assumptions: The clock skews have been validated The PUT is longest Other paths have been tested
D3 Q3

D1 Q1

PUT 011 0 CLB2

EC
D2 Q2

001 000 110

EC

CLB1

EC
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Experimental Results
Target device: a 14x14 Xilinx Spartan Series FPGA Only single-length lines are considered After TC reduction BIST1 has lower utilization than BIST2
BIST type Target segments
All wire segments NE, WS, WN, and ES switches All WE, NS switches

# of TCs

Total

BIST1

1 1

16 24

40

BIST2

All wire segments NE, WS, WN, and ES switches

Clock skew between 2 adjacent CLBs All WE & NS switches

16
4 16 36

2 2

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Segment Coverage
A metric to measure how much resources are covered by test configurations BIST-based methods never cover segments involved with IOB
CLB block used CLB pins used I/O pins used Tracks used Switches used Segment coverage Effective segment coverage Array size: 14 x 14 BIST1 196/196 1568/1568 0/112 3360/3840 9392/10800 87.89% 100% BIST1&2 196/196 1568/1568 0/112 3360/3840 9392/10800 87.89% 100%
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Statistical Delay Defect Coverage

Use Poisson distribution to model the fault distribution Adopt a Monte Carlo process to produce

samples
Effective statistical delay defect coverage (ESDDC) = Sdetected / Sfailed Sdetected: total failed samples that have been detected Sfailed: total failed samples
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ESDDC
BIST1
Defect Coverage (%)
100.0% 99.0% 98.0% 97.0% 96.0% 95.0% 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 The Mean Value of Defect Size (unit time)

BIST1&2

Sample count: 10K Defect count (mean): 1.3 Slack: 10% of segment spec. FPGA size: 14 x 14
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Conclusions and Future Work

We have proposed new BIST designs for FPGA interconnect delay faults At-speed testing Without being affected by clock skew Easy implementation on different FPGA architectures Test configurations are generated automatically Future work: interconnect delay fault diagnosis
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