Nexray

RTD 2009

Nexray
A. DommannA, H. von KnelC, P. GrningB, T. BandiA, R. BergamaschiniD, C.A. BosshardA, F. CardotA, D. ChrastinaD, H.R. ElsenerB, C. FalubC, S. GiudiceA, A. GonzalezC, F. IsaD, G. IsellaD, R. Jose JamesA, R. KaufmannA, C. KottlerA, Th. KreiligerC, R. LongtinB, A. MarzegalliD, L. MiglioD, A. NeelsA, P. NiedermannA, A. PezousA, J. SanchezB, G. Spinola DuranteA, Y. ZhaA A: CSEM B: EMPA C: ETHZ, D: L-NESS, Politecnico di Milano, Como, Italy

Zrich, 26. 4. 2012

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Nexray

RTD 2009

A System Approach

Source

Sample

Detector

Spectrum, power, Coherence, Size

Contrast mechanism

Resolution, Size, Efficiency

Miniaturized, fast and programmable X-ray sources

Phase contrast Xray imaging

Direct X-ray detectors without bump-bonding

Breakthroughs required in all key building blocks of X-ray systems

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RTD 2009 Nexray Network of Integrated Miniaturized X-ray Systems Operating in Complex Environments

Miniaturized, fast and programmable X-ray sources

Single-photon solidstate X-ray detection

Si-Ge layers highenergy X-ray detection

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RTD 2009

Novel Concepts of Applications

Large area X-ray sources Pixelated X-ray sources Pulsed operation of X-ray source (and individual source-pixels) Highly efficient sensors, applicable in medical diagnostics
Detector

Energy resolved X-ray image detection

Source

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Nexray

RTD 2009

X-ray Source Microfabrication

Diamond X-ray Window

Extraction Anode

Emission Cathode

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RTD 2009

Microfabrication
CNT compatibility to Micro-fabrication
CNT samples grown on Ni catalyst on Si Tested for resist application and lift off No mechanical delamination found

Gold-Tin solder electroplating developed to bond extraction grid on cathode

Layers for Transient Liquid Phase bonding Eutectic gold tin Thickness of up to 17 m achieved To lower the extraction grid voltage
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AuSn Ring for sealing

Compatibility to CNT deposition

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RTD 2009

Integration
Gold-Tin hermetic sealing
High temperature stable(375C/30mins) UBM for Getter activation developed Transient liquid phase (TLP) bonding tests for step annealing and 3D stacking shows first results; Transformation to Au5Sn proved Hermetic sealing with a leak rate >10-12mbar*l/sec (at 105 mbar atmosphere) proven with Eutectic
Vacuum levels inside the package to be tested

Silicon AuSn solder Silicon

High temperature UBM Window Grid CNT cathode

AuSn bond Spacer AuSi bond AuSn bond

Au5Sn

AuSi tests
To be used for grid-spacer stack bonding Electroplated Au to bare silicon Hermeticity achieved on smaller area samples

TLP Fully transformed Au5Sn

AuSi Flow out shows formation of Eutectic

After shear test bonded through out the ring

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RTD 2009

CNT Fabrication 1: Paste CNT Cathode

Paste based CNT deposition
Stencil printing technology: Pixel size of 400m Process development Different substrates (Si/Mo), processes Surface grinding techniques to improve emission
CNT paste on Mo after Sintering

Results
86 mA/cm2 at 350V achieved (Measured using SAFEM) Short term reliability tests show stability V-I follows Fowler-Nordheim plot Grinding of surface improves emission characteristics
V-I characteristics of CNT paste measured using SAFEM
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RTD 2009

CNT Fabrication 2: PE-CVD based CNT

PE-CVD based CNT Deposition
Process development Different Underlayers /recipes Best growth achieved on Ni catalyst on Si wafer Tests ongoing to improve homogeneity of the growth/emission using E-beam lithography Results 0.5 mA/cm2 at 250V achieved (Measured using SAFEM) Short term reliability tests show stability V-I has a some shift from Fowler-Nordheim E-beam lithography tests needs to be improved for vertical growth
V-I characteristics of the PE-CVD CNT measured using SAFEM
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PE-CVD CNT deposited on Si substrate with Ni catalyst

Nexray

RTD 2009

Emission Comparison of Different Cathodes

Comparison of emission for different substrates

Paste deposition on Mo substrates after grinding shows best results

PECVD growth has potential for improvements with the E-beam lithography

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RTD 2009

Device tests
CTNs show also reproducible electron emission in a source mock-up
CNTs
4 4 4 4

Extraction grating
Transmission anode (Cu, Ag, ?) C

Insulator (Kapton, Macor, ?)

Insulators
X

Assembly holder (Macor, Tef lon, ?)

B 4 4

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RTD 2009

MEMS for X-ray: Novel X-ray Detector

pixel

im plant

CMO S circuit in p-we ll

back-thinned Si

charge ca rrie rs

Ge

HV x-ray

Epitaxial pillar-like growth of Ge on microstructured silicon wafers Direct detection without bump-bonding
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RTD 2009

MEMS for X-ray: Concept of X-ray Detector

X-ray - HV

Thick Ge layer (50 150 m) Epitaxially grown with LEPECVD On backside of CMOS wafer Ge absorption layer is hence monolithically integrated

p- Ge

eh
depleted area electric field lines CMOS circuit

n Si

p+

n+

1 Pixel

No bump-bonding needed

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RTD 2009

Low Energy Plasma Enhanced CVD

Primary coil Wobblers Wobblers Wafer stage Wafer Gas inlet Argon plasma Turbo pump Anode plate Load lock

Primary coil

Plasma source

Electrons emitted by a hot filament sustain a DC plasma Low (~10eV) ion energy no ion damage Discharge confined by a magnetic field (~1 mT) Deposition rates 0.01-10nm/s depending on gas flow and plasma density Gas phase precursors: SiH4, GeH4
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RTD 2009

From Isolated Pillars to Closely Spaced Arrays

The self-limiting growth mode could be modeled by taking into account the diffusion equations and the mutual flux shielding.

Mutual flux shielding

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RTD 2009

HRXRD analysis: 50 m Ge towers

Si

HRXRD around Ge (004) peak

XRD reciprocal space maps of 50 m high Ge towers, including Si substrate Detailed scan of Ge(004) reflection

~ 50 m
SEM picture of 50 m high Ge towers, no fusion occurring

Ge

HRXRD measurements on 50 m Ge towers show that they are fully relaxed

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RTD 2009

HRXRD analysis: 50 m Ge towers

Reference: Pure Ge bulk

Ge tower 50 m

Ge (relaxed) (115) (004)

(004) reflection (115) reflection

Si (substrate)

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RTD 2009

Dislocation Management by Surface Faceting

415 C

515 C

585 C

All dislocations can be eliminated by controlling the morphology of Ge towers.

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RTD 2009

TDD of Ge/Si Pillars: In Situ Thermal Annealing

6 cycles x 2 min at 780-600C At different times during the growth
TDD (cm )
-4

444 . x 4

Pillars S (444 44m = ) Unpatterned Ge

4 4

Pillars S (444 444 = m )

Comparison to unpatterned layer growth

444 . x 4

444 . x 4

444 . x 4

44 .

Anneal. step distance from interface( m)

In situ annealing most efficient at early stages of the growth When Ge pillars are relaxed thermal treatments become inefficient
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RTD 2009

Self-Limiting Lateral Growth

Ge coverage: 7 m

Ge coverage: 50 m(!) T=490 C

Similar growth morphology irrespective of the thickness!
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RTD 2009

Post-Processing Details

200 mm processed CMOS wafers Thinned to 100 m withTaiko process, Si backside preparation Ge growth Oxide passivation & etchback, Ge etching, electrode deposition Dicing

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RTD 2009

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RTD 2009

Post-Processing Tests

On dummy test wafers (150 mm) and CMOS processed wafers (200 mm) Thinned to 100 m Ge growth, 10-50 m pillar growth 200 mm wafers were cut down to 150 mm for post-processing

Fully processed CMOS wafer with grown Ge pillars (on the backside)

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RTD 2009

CMOS Diode Array

Array with hetero-test diodes produced

Intended for Ge-Si diode characterisation Front side processing done by Lfoundry LFoundry closed one of two production sites Delays Back side processing done by CSEM & LETI

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RTD 2009

CMOS Read-Out Electronics

itst vtst is vref Register calib CSA +
+ Pulse Shaper + -

ith the Gray dval Cnt ibias

4 4

column bus cout

tm 4 sensor: heterojunction diode -HV

vref

(substr)

Si Ge calib calck

calib grs DAC gtx rsel

dval

C al FSM

cval rng

Block diagram and transistor-layout of the photon counting pixel with leakage current suppression Impementation only this summer due to LFoundry delays
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RTD 2009

Electrical Measurements on Individual Germanium Towers

Ge towers are electrically insulated from neighbors by passivated sidewalls
I-V characteristics of individual Ge tower acting as p-i-n diode

SiO2
Electrical setup at open prober station SEM picture of Au wire

Au wire
p-Si p-Ge Ge Ge Ge

Id

Au wire
open prober station

Vd
n-Si
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RTD 2009

Electrical measurements in SEM chamber in-situ

Electrical setup at SEM chamber SEM picture of top contact on individual germanium tower

SEM chamber
tungsten tip p-Si p-Ge Ge Ge Ge

Id

Vd
n-Si
SEM Zeiss Nvision 40

2 m
I-V characteristics measured in-situ

Conduct ive tungste n tip

10 m

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RTD 2009

Status Summary (as of today)

Detector: Thick Ge layers can be grown in towers First electrical tests on Ge-towers Temperature compatible CMOS process is developed Post-processing is tested, needs some fine-tuning First CMOS processed wafers with Ge towers ready Source: Fist electrons could be extracted and accelerated with 10 KV Extraction currents from CNTs sufficient for X-ray operation Elements of packaging solutions ready

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Nexray

RTD 2009

Cosmicmos

Add-on Nexray

A. DommannA, H. von KnelC, J. FompeyrineB, Mirja RichterB, Emanuele UcelliB, C. FalubC, R. KaufmannA, A. NeelsA, E. MllerC, A. GonzalezC, Th. KreiligerC, T. BandiA, F. IsaD, G. Isella D, D. Chrastina D, L. Miglio D, A. MarzegalliD, R. Bergamaschini D A: CSEM; B: IBM, C: ETHZ, D:L-NESS, Politecnico di Milano, Como, Italy

Zrich, 26. 4. 2012

2012 | Page 29

COSMICMOS

Nexray

RTD 2009

Integration of III-V Materials on Si Substrates for HEMTs Development

Si substrates
-Small mass -Good thermal conductivity -Large wafer diameter

GaAs
-direct band gap alignment -high carrier mobility -Optimum for the development of optoelectronic devices

Challenges
4% a0GaAs= 5.6532 lattice mismatch High a0Si = 5.6532 TDD 60% difference in thermal expansion coefficient Anti Phase Domains: Inherent to the growth of a polar material (GaAs) on top of a non-polar substrate (Si) -As-As and Ga-Ga bondings -high electric fields -donor and acceptor centres. Leak currents

Solved by the introduction of Ge intermediate layers

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RTD 2009

MBE regrowth: Ge (001) vs. Ge, 6 miscut towards (110

h Si patterning + LEPCVD 2 mGe pillars growth + MBE GaAs regrowth

Epitaxial structure Substrate: Ge (001)

me epitaxial structure in two different patterned substrates after regrowth them with 2 m of epitaxial a 6 miscut towards (110)

Antiphase domains formatio n, both in the unpatter ned Good morphology in the unpatterned area part and the pillars

Subst: Ge 6 miscut towards (110)

(001)
Ge tower on Si
interactio n between different facets

GaAs/Ge tower on Si

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RTD 2009

GaAs MBE regrowth: PL

Method: Photoluminescence signal of the QWs growth on the two different patterned substrates (Ge/Si (001) and Ge/Si with a 6 miscut towards (110)) has been compared with the one coming from the same structure growth by MBE both on a GaAs and a miscut (9 towards (110)) Ge comercial substrates

Substrate GaAs Ge (9 off) 27 Ge/Si Ge Pillars (6 (001) (1515 off) m2) 36 1268 165

Intensity ratio

GaAs growth on Ge (001) substrates leads to APD formation GaAs good quality material has been growth on unpatterned miscut (6-(110)) Ge Our main problem in Ge pillars on miscut wafers comes from the interaction between different facets Comparable PL intensity coming from the QWs grown in the LEPCVD Ge substrate to a commercial 9 offcut Ge one Factor 4.5 on the PL intensity between the 1515 m2 pillars and the unpatterned area
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COSMICMOS

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RTD 2009

GaAs MOVPE
Substrates:5 m of epitaxial Ge grown on CSEM Bosch patterned miscut Si and patterned passivated (SiOx) Growth: 2 temperatures growth method- Low temperature, nominal growth rate 6 nm/min during 5 min, high temperature , nominal growth rate 29 nm/min during 34 min We have selectivity on
GaAs on (passivated )Si GaAs on Ge

GaAs regrowth by MOVPE of pillars passivated with SiOx. The first attempt of GaAs regrowth directly on Si result in low quality polycrystalline material Even though the first results on pillars are promising, an optimization of the Ge epi-ready treatment is needed

Polycrystalline growth. Selectivity on SiOx pillar

Faceted material

2012 | Page 33

COSMICMOS

Nexray

RTD 2009

GaAs on Si Substrates: Challenges

a0GaAs= 5.6532 a0Si = 5.6532

Lattice mismatch (4%) ~>1012 dislocationscm-2

2 3

60% difference in thermal expansion coefficient GaAs is a polar material and Si is non-polar ~> anti phase domains (As-As and Ga-Ga bondings) It involves the presence of high electric fields and donor and acceptor centers. Leak currents

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RTD 2009

Thank you for your attention

2012 | Page 35