Little- and big-endian memory organizations

bi t 3 1
23 19 15 11 7 3 22 18 14 10 6 2 21 17 13 9 5 1

bi t 0
20 16 12 8 4 0

bi t 3 1
20 16 12 8 21 17 13 9 5 1 22 18 14 10 6 2

bi t 0
23 19 15 11 7 3

w ord16 half -w ord14 half -w ord12 w ord8 byte6 half -w ord4 byte3 byte2 byte1 byte0 (a) Little-endian memory organization byte address
4 0

w ord16 half -w ord12 half -w ord14 w ord8 byte5 half -w ord6 byte0 byte1 byte2 byte3 (b) Big-endian memory organization byte address

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ARM operating modes and register usage.

CPS R[ 4 : 0 ] 10000 10001 10010 10011 10111 11011 11111

Mo de User FIQ IRQ SVC Abort Undef System

Us e Normal user code Processing fast interrupts Processing standard interrupts Processing software interrupts (SWIs) Processing memory faults Handling undefined instruction traps Running privileged operating system tasks

Re g i s t e rs user _fiq _irq _svc _abt _und user

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Exception vector addresses

Ex c e p t i o n Reset Undefined instruction Software interrupt (SWI) Prefetch abort (instruction fetch memory fault) Data abort (data access memory fault) IRQ (normal interrupt) FIQ (fast interrupt)

Mo de SVC UND SVC Abort Abort IRQ FIQ

Ve c t o r addre s s 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000018 0x0000001C

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The ARM condition code field

31

28 27

cond

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ARM condition codes

Op c o de [3 1 :2 8 ] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Mn e mo n i c ex tens i o n EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL NV In t e rp re t at i o n Equal / equals zero Not equal Carry set / unsigned higher or same Carry clear / unsigned lower Minus / negative Plus / positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Signed greater than or equal Signed less than Signed greater than Signed less than or equal Always Never (do not use!) S t at us f l ag s t at e f o r e x e c ut i o n Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N is not equal to V Z clear and N equals V Z set or N is not equal to V any none

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Branch and Branch with Link binary encoding

31

28 27

25 24 23

cond

101 L

24-bit signed w ord off set

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Branch (with optional link) and exchange instruction binary encoding

(1) BX|BLX Rm
31 28 27 6 5 4 3 0

cond (2) BLX label

31 28 27

0001001011111111111100

L 1

Rm

25 24 23

1111 101 H

24-bit signed word offset

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Software interrupt binary encoding

31

28 27

24 23

cond

1111

24-bit (interpreted) immediate

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Data processing instruction binary encoding

31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond

0 0 # opcode S

Rn

Rd

operand 2
destination register first operand register set condition codes arithmetic/logic function

25

11

8 7

1
immediate alignment
11

#rot

8-bit immediate

7 6 5 4 3

#shift
25

Sh 0

Rm

immediate shift length shift type second operand register

11 8 7 6 5 4 3 0

Rs
register shift length

0 Sh 1

Rm

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ARM data processing instructions

Op c o de [2 4 :2 1 ] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Mn e mo n i c AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN Me an i n g Logical bit-wise AND Logical bit-wise exclusive OR Subtract Reverse subtract Add Add with carry Subtract with carry Reverse subtract with carry Test Test equivalence Compare Compare negated Logical bit-wise OR Move Bit clear Move negated Ef f e c t Rd := Rn AND Op2 Rd := Rn EOR Op2 Rd := Rn - Op2 Rd := Op2 - Rn Rd := Rn + Op2 Rd := Rn + Op2 + C Rd := Rn - Op2 + C - 1 Rd := Op2 - Rn + C - 1 Scc on Rn AND Op2 Scc on Rn EOR Op2 Scc on Rn - Op2 Scc on Rn + Op2 Rd := Rn OR Op2 Rd := Op2 Rd := Rn AND NOT Op2 Rd := NOT Op2

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Multiply instruction binary encoding

31

28 27

24 23

21 20 19

16 15

12 11

8 7

4 3

cond

0000

mul

S Rd/RdHi Rn/RdLo

Rs

1001

Rm

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Multiply instructions

Op c o de [2 3 :2 1 ] 000 001 100 101 110 111

Mn e mo n i c MUL MLA UMULL UMLAL SMULL SMLAL

Me an i n g Multiply (32-bit result) Multiply-accumulate (32-bit result) Unsigned multiply long Unsigned multiply-accumulate long Signed multiply long Signed multiply-accumulate long

Ef f e c t Rd := (Rm * Rs) [31:0] Rd := (Rm * Rs + Rn) [31:0] RdHi:RdLo := Rm * Rs RdHi:RdLo += Rm * Rs RdHi:RdLo := Rm * Rs RdHi:RdLo += Rm * Rs

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Count leading zeros instruction binary encoding

31

28 27

16 15

12 11

4 3

cond

0 001 011 000 00

Rd

00 000 001

Rm

destination register

source register

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Single word and unsigned byte data transfer instruction binary encoding
31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0

cond

01 # P U BW L

Rn

Rd

of fset
source /d esti nati on regi ste r ba se regi ste r l oad /sto re wri te -ba ck (au to -i nd ex) un si gne d byte /wo rd up /d own pre-/post-i nde x

25

11

12-bit immediate

25

11

7 6 5 4 3

1
i mmedi ate sh ift l en gth shi ft type offse t regi ster

#shift

Sh 0

Rm

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Half-word and signed byte data transfer instruction binary encoding

31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 6 5 4 3 0

cond

000 P U # W L

Rn

Rd

of fsetH 1 S H 1 of fsetL
source /d esti nati on regi ste r ba se regi ste r l oad /sto re wri te -ba ck (au to -i nd ex) up /d own pre-/post-i nde x

22

11

Imm[7:4]

Imm[3:0]

22

11

0
offse t regi ster

0000

Rm

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Data type encoding

S 1 0 1

H 0 1 1

Dat a t y p e Signed byte Unsigned half-word Signed half-word

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Multiple register data transfer instruction binary encoding

31

28 27

25 24 23 22 21 20 19

16 15

cond

100 P U SW L

Rn

register list
ba se regi ste r l oad /sto re wri te -ba ck (au to -i nd ex) resto re PS R a nd force user bi t up /d own pre-/post-i nde x

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Swap memory and register instruction binary encoding

31

28 27

23 22 21 20 19

16 15

12 11

4 3

cond

00010

B 00

Rn

Rd

00001001

Rm

de sti natio n re gi ster ba se regi ste r un si gne d byte /wo rd source reg iste r

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Status register to general register transfer instruction binary encoding

31

28 27

23 22 21

16 15

12 11

cond

00010

R 001111

Rd

000000000000
de sti natio n re gi ster SPS R/CPSR

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Transfer to status register instruction binary encoding

31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0

cond

00 # 10 R 10

field

1111

operand

fi eld mask SPSR/CPSR

25 11 8 7 0

1
immediate alignment
25 11

#rot

8-bit immediate

4 3

0
operand register

00000000

Rm

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Coprocessor data processing instruction binary encoding

31

28 27

24 23

20 19

16 15

12 11

8 7

5 4 3

cond

1110

Cop1

CRn

CRd

CP#

Cop2 0

CRm

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Coprocessor data transfer instruction binary encoding

31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 0

cond

1 1 0 P U NW L

Rn

CRd

CP#

8-bit off set

source /d esti nati on regi ste r ba se regi ste r l oad /sto re wri te -ba ck (au to -i nd ex) da ta size (cop ro cesso r de pen den t) up /d own pre-/post-i nde x

2000 Addison Wesley

Coprocessor register transfer instruction binary encoding

31

28 27

24 23

21 20 19

16 15

12 11

8 7

5 4 3

cond

1110

Cop1 L

CRn

Rd

CP#

Cop2 1

CRm

l oad from cop ro cesso r/sto re to co proce ssor

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Breakpoint instruction binary encoding

31

28 27

20 19

16 15

12 11

8 7

4 3

111 0

00 010 010

xxxx

x xx x

xxxx

01 11

xxxx

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Arithmetic instruction extension space

31

28 27

22 21 20 19

16 15

12 11

8 7

4 3

cond

000001

op

Rn

Rd

Rs

1001

Rm

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Control instruction extension space

31

28 27

23 22 21 20 19

16 15

12 11

8 7 6

4 3

cond cond cond

00010 00010 00110

op1 0 op1 0 op1 0

Rn Rn Rn

Rd Rd Rd

Rs Rs #rot

op2

Rm Rm

0 op2 1

8-bit immediate

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Data transfer instruction extension space

31

28 27

25 24 23 22 21 20 19

16 15

12 11

8 7 6 5 4 3

cond

000 P U BW L

Rn

Rd

Rs

1 op1 1

Rm

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Coprocessor instruction extension space

31

28 27

25 24 23 22 21 20 19

16 15

12 11

8 7

cond

1100

op 0 X

Rn

CRd

CP#

of fset

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Undefined instruction space

31

28 27

25 24

5 4 3

cond

011

X X X XX X X X X X X XX X X X X X X X

1 XXXX

2000 Addison Wesley

Summary of ARM architectures

Core Architecture ARM1 v1 ARM2 v2 ARM2as, ARM3 v2a ARM6, ARM600, ARM610 v3 ARM7, ARM700, ARM710 v3 ARM7TDMI, ARM710T, ARM720T, ARM740T v4T StrongARM, ARM8, ARM810 v4 ARM9TDMI, ARM920T, ARM940T v4T ARM9ES v5TE ARM10TDMI, ARM1020E v5TE
2000 Addison Wesley