Computer Architecture and Organization Chapter 2 The Central Processing Unit

Does the calculations Everything else in the computer is there to service this unit Handles integers May handle floating point (real) numbers May be separate FPU (math's co-processor) May be on chip separate FPU (486DX +)

Arithmetic & Logic Unit

ALU Inputs and Outputs

Integer Representation
Only have 0 & 1 to represent everything Positive numbers stored in binary
e.g. 41=00101001

No minus sign Non negative numbers representation is straight forward

Sign-Magnitude
Left most bit (MSB) is sign bit 0 means positive 1 means negative +18 = 00010010 -18 = 10010010

Drawbacks/problems
Need to consider both sign and magnitude in arithmetic Two representations of zero (+0 and -0)

Twos Compliment
MSB Sign bit For positive Numbers
Sign bit 0 Number zero as Positive

For negative Numbers

Sign bit 1

Benefits
One representation of zero Arithmetic works easily

Conversion between different lengths

n bit integer has to be stored in m bit register, where m>n In sign magnitude representation,
Move the sign bit to the new leftmost position Fill with zeros

Twos complement
Move the sign bit to the new leftmost position Fill with the copies of sign bit

Integer Arithmetic - Negation

Sign magnitude
Invert the sign bit

2s complement
Take Boolean complement of each bit including sign bit Add one two the result

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Negation Special Case

Case 1: negation of 0 is 0 Case 2 : negation of -128 is -128 Unavoidable

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 8 bit 2s compliment

Range of Numbers

+127 = 01111111 = 27 -1 -128 = 10000000 = -27

16 bit 2s compliment
+32767 = 011111111 11111111 = 215 - 1 -32768 = 100000000 00000000 = -215

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 Normal binary addition Result is positive we get a positive number in 2s complement Result is negative a negative number in 2s complement Carry has to be ignored If the result is larger than the word size being used, then this condition is called overflow When an overflow is occurred ALU must be signaled that the result should not be used.
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Addition

Overflow rule
If two numbers are added, and they are both positive or both negative, then overflow occurs if and only if the result has the opposite sign.

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Subtraction
Rule: Take twos compliment of subtrahend and add to minuend
i.e. a - b = a + (-b)

So we only need addition and complement circuits

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Hardware for Addition and Subtraction

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Multiplication
Complex Work out partial product for each digit Take care with place value (column) Add partial products Multiplication
Multiplier Q , Multiplicand M A reg and c 0 Control logic reads the bit from Q reg and if it is 1 M is added to A and result is stored in A and C A Q Shifted O means only Shifting
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Unsigned Binary Multiplication

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Execution of Example

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Flowchart for Unsigned Binary Multiplication

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Multiplying Negative Numbers

This does not work Solution 1
Convert to positive Multiply as unsigned integer If signs were different, negate answer

Solution 2
Booths algorithm

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Booths Algorithm

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Example of Booths Algorithm

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Division
More complex than multiplication Negative numbers are really bad! Based on long division

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Division of Unsigned Binary Integers

00001101 1011 10010011 1011 001110 Partial 1011 Remainders 001111 1011 100 Divisor Quotient Dividend

Remainder

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Flowchart for Unsigned Binary Division

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2s complement Division
Load the divisor-M register and dividend - A, Q registers. Shift A, Q left 1 bit position. If M and A have same signs, performs A=A-M or A=A+M Operation is successful if the sign of A is same before and after the operation.
If A=0 then set Q0= 1 If A not equal to 0 then set Q0= 0

Repeat the above steps as many bits in Q position

The remainder is in A and the quotient is in Q.

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M = 0011

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Real Numbers
Numbers with fractions Could be done in pure binary
1001.1010 = 24 + 20 +2-1 + 2-3 =9.625

Where is the binary point? Fixed?

Very limited

Moving?
How do you show where it is?

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Floating Point

+/- .significand x 2exponent Radix point is at the right of the MSB Biased representation( A fixed value called BIAS from the field to get the true exponent value) Normalized
MSB of the significand is non Zero

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Floating Point Examples

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 First bit is sign bit First bit of significand value is 1 (no need to store) 127 is subtracted from the true exponent value

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 Using 32 bits

-ve overflow -ve underflow Zero +ve underflow +ve overflow

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Expressible Numbers

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 In 32 bits
8 bits - exponent 23 bits - significand

No. of bits in the exponent increases range also increases But only fixed number of values are expressed, we have reduced the density and precision Only way to increase both is to increase the bits So most computers offers two
Single precision (32 bits) Double precision (64 bits)
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IEEE 754
Standard for floating point storage Developed to facilitate the portability of programs from processor to another Defines 32 bit single and 64 bit double standards 8 and 11 bit exponent respectively Extended formats also (both significant and exponent)

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IEEE 754 Formats

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 The following numbers use the IEEE 32-bit floating-point format. What is the equivalent decimal value? 1 10000011 11000000000000000000000 Express the following numbers in IEEE 32-bit floating-point format:
-1.5 Ans: 1 01111111 10000000000000000000000 384 Ans: 0 10000111 00000000000000000000000
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Floating point Arithmetic

For Addition and subtraction both operands should have the same exponent value Require shifting the radix point on one of the operands Multiplication and division are more straightforward A floating-point operation may produce one of these conditions
Exponent overflow: A positive exponent exceeds the maximum possible exponent value. Exponent underflow: A negative exponent is less than the minimum possible exponent value Significand underflow: In the process of aligning significands, digits may flow off the right end of the significand. Significand overflow: The addition of two significands of the same sign may result in a carry out of the most significant bit
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 Addition and subtraction are more complex than multiplication and division, because of the need for alignment. four basic phases of the algorithm
Check for zeros Align significands (adjusting exponents) Add or subtract significands Normalize result

FP Arithmetic Addition and subtraction

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FP Addition & Subtraction Flowchart

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FP Arithmetic Multiplication and Division

Check for zero Add/subtract exponents Multiply/divide significand Normalize Round

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Floating Point Multiplication

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Floating Point Division

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Instruction Sets: Characteristics and Functions

What is an Instruction Set?

The complete collection of instructions that the processor can execute Machine Code Binary

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Elements of an Instruction
Operation code (Op code)
Specifies the operation to be performed Specified by a binary code called opcode

Source Operand reference

One more source operands Operands that are input for operation

Result Operand reference

Put the answer here

Next Instruction Reference

where to fetch the next instruction
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Source and result operands

Main memory (or virtual memory or cache) CPU register I/O device

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Instruction Cycle State Diagram

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Instruction Representation
In machine code each instruction has a unique bit pattern For human consumption a symbolic representation is used
e.g. ADD, SUB, LOAD

Opcodes represented by abbreviations called as mnemonics Operands can also be represented in this way
ADD R,Y
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Simple Instruction Format

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Instruction Types
Data processing Data storage (main memory) Data movement (I/O) Program flow control

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Number of Addresses (a)

3 addresses
Operand 1, Operand 2, Result Not to change value of any operand a = b + c; Needs very long words to hold everything

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Number of Addresses (b)

2 addresses
One address has double duty
as operand and result

a=a+b Reduces length of instruction

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Number of Addresses (c)

1 address
Implicit second address Usually a register (accumulator) Common on early machines

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Number of Addresses (d)

0 (zero) addresses
All addresses implicit Uses a stack

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How Many Addresses

More addresses
More complex More registers
Inter-register operations are quicker

Fewer instructions per program

Fewer addresses
Less complex Shorter length to store More instructions per program Longer execution time
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Instruction set Design

Operation repertoire How many operations? What can they do? How complex are they? Data types Instruction formats Length of op code field Number of addresses Registers Number of CPU registers used Addressing modes
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Types of Operand
Addresses Numbers
Difference between numbers used in ordinary maths and computers Latter is limited Integer, floating point and decimal

Characters
ASCII and IRA EBCDIC used in IBM

Logical Data
Bits or flags
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x86 Data Types

8 bit Byte 16 bit word 32 bit double word 64 bit quad word 128 bit double quad word Data accessed across 32 bit bus in units of double word read at addresses divisible by 4 Little endian

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x86 Numeric Data Formats

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 Packed byte and packed byte integer Bytes packed into 64-bit quadword or 128-bit double quadword Packed word and packed word integer 16-bit words packed into 64-bit quadword or 128-bit double quadword Packed doubleword and packed doubleword integer 32-bit double word packed into 64-bit quadword or 128-bit double quad word Packed quad word and packed quadword integer Two 64-bit quadwords packed into 128-bit double quadword Packed single-precision floating-point and packed double-precision floating-point Four 32-bit floating-point or two 64-bit floating-point values packed into a 128-bit double quadword
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SIMD Data Types

 8 (byte), 16 (halfword), 32 (word) bits Halfword access should be halfword aligned and word accesses should be word aligned Nonaligned access Default Treated as truncated Bits[1:0] treated as zero for word Bit[0] treated as zero for halfword Data abort signal indicates alignment fault for attempting unaligned access All data types supports both Unsigned integer and Twos-complement signed
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ARM Data Types

 Majority of ARM processors do not provide floatingpoint hardware Saves power and area Floating-point arithmetic implemented in software

Optional floating-point coprocessor

Single- and double-precision IEEE 754 floating point data types

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ARM Endian Support

E-bit in system control register Under program control

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Types of Operation
Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control

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Data Transfer
Specify
Source Destination length of data

May be different instructions for different movements

e.g. IBM 370

Or one instruction and different addresses

e.g. VAX

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Arithmetic

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LOGICAL

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Shift and Rotate Operations

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Conversion

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Input/output
May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA)

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Systems Control
Executed on special state Used for Control registers For operating systems use

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NEED FOR CONTROL INSTRUCTIONS

Group of codes needs to be executed repeatedly Decision making, satisfying condition Breaking of tasks into smaller pieces

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Transfer of Control
Branch or Jump instruction
Conditional Unconditional

Consider subtraction
BRP X - Branch to location X if result is positive. BRN X - Branch to location X if result is negative. BRZ X - Branch to location X if result is zero. BRO X - Branch to location X if overflow occurs.

BRE R1, R2, X

Branch to X if contents of R1 contents of R2.
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 Skip
Skip the next instruction e.g. increment and skip if zero ISZ Register1

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Procedure call
Advantages
Code reuse Efficient use of storage

Two basic instructions

Call - branches from the present location to the procedure Return- returns from the procedure to the place from which it was called

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Nested Procedure Calls

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Use of Stack

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Stack Frame Growth Using Sample Procedures P and Q

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X86 status flags

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X 86 operation types

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ARM operation types

Load and store instructions Branch instruction Data processing instruction Multiply instructions Parallel addition and subtraction instruction
Image processing applications

Status register access instructions

N, Z, C, V,

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Unusual aspects of ARM

All instructions includes a condition code.
Not only branch instructions

All data processing instructions include an S bit

Defines any updates ha been made to condition flags

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Instruction Sets: Addressing Modes and Formats

Addressing Modes
Immediate Direct Indirect Register Register Indirect Displacement Stack

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 All architectures provides more than one of these addressing modes How the processor can determine which address mode is being used ?
one or more bits in the instruction format can be used as a mode field. Value of the mode field determines which addressing mode is to be used

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Immediate Addressing

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Immediate Addressing
Operand is part of instruction Operand = address field e.g. ADD 5
Add 5 to contents of accumulator 5 is operand

No memory reference to fetch data Fast Limited range

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Direct addressing

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Direct Addressing
Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A
Add contents of cell A to accumulator Look in memory at address A for operand

Single memory reference to access data No additional calculations to work out effective address Limited address space
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Indirect Addressing

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 Address field refer to the address of a word in memory, which in turn contains a full-length address of the operand EA = (A)
Look in A, find address (A) and look there for operand
e.g. ADD (A)

Indirect Addressing

Add contents of cell pointed to by contents of A to accumulator

Large address space Multiple memory accesses to find operand Hence slower
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Register Addressing

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Operand is held in register named in address field EA = R Limited number of registers Advantages
Small address field is needed for instructions so shorter instructions less time

Register Addressing

Less number of registers available

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Register Indirect Addressing

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Register Indirect Addressing

indirect addressing EA = (R) Operand is in memory cell pointed by contents of register R Large address space One fewer memory access than indirect addressing

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Displacement Addressing

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Displacement Addressing
Uses both direct and register indirect addressing EA = A + (R) Address field hold two values
A = base value R = register that holds displacement

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Relative Addressing
A version of displacement addressing R = Program counter, PC EA = A + (PC)

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Base-Register Addressing
A holds displacement R contains a main memory address

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Indexed Addressing
A = base R = displacement EA = A + R Good for accessing arrays

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Combinations
R value is incremented or decremented automatically auto indexing Post index indexing is performed after the indirection
EA = (A) + (R) Address is fetched and indexed with the register value

Pre index before the indirection

EA = (A+(R))

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Stack Addressing
Operand is on top of stack Stack pointer

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x86 Addressing Modes

Virtual or effective address
Starting address plus effective address gives linear address This goes through page translation if paging enabled to get physical address

addressing modes available

Immediate Register Displacement Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative

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x86 Addressing Mode Calculation

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ARM Addressing Modes Load/Store Only instructions that reference memory base register plus offset Offset Offset added to or subtracted from base register contents to form the memory address Preindex Memory address is formed as for offset addressing Memory address also written back to base register Postindex Memory address is base register value Offset added or subtracted Result written back to base register Base register acts as index register for preindex and postindex addressing Offset either immediate value in instruction or another register
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ARM Indexing Methods

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ARM Data Processing Instruction Addressing & Branch Instructions

Data Processing
Register addressing Or mixture of register and immediate addressing

Branch
Immediate

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ARM Load/Store Multiple Addressing

Load/store subset of general-purpose registers Sequential range of memory addresses Increment after, increment before, decrement after, and decrement before Base register specifies main memory address Incrementing or decrementing starts before or after first memory access

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ARM Load/Store Multiple Addressing Diagram

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Instruction Formats
Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set

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Instruction Length
Affected by and affects:
Memory size Memory organization Bus structure CPU complexity CPU speed

Trade off between powerful instruction repertoire and saving space

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Allocation of Bits
Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity

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Assembly language
Machines store and understand binary instructions E.g. N= I + J + K initialize I=2, J=3, K=4

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Improvements
Use hexadecimal rather than binary
Code as series of lines
Hex address and memory address

Need to translate automatically using program

Add symbolic names or mnemonics for instructions Three fields per line
Location address Three letter opcode If memory reference: address

Need more complex translation program

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 First field (address) now symbolic Memory references in third field now symbolic Now have assembly language and need an assembler to translate

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