8237 DMA controller

DMA Controller
A DMA controller interfaces with several peripherals that may request DMA.

The controller decides the priority of simultaneous DMA requests

communicates with the peripheral and the CPU, and provides memory
addresses for data transfer.

DMA controller commonly used with 8086 is the 8237 programmable device.

The 8237 is in fact a special-purpose microprocessor.

Normally it appears as part of the system controller chip-sets.

The 8237 is a 4-channel device. Each channel is dedicated to a specific

peripheral device and capable of addressing 64 K bytes section of memory.
Pin diagram of 8237
 DMA
Some important signal pins:

• DREQ3 – DREQ0 (DMA request): Used to

request a DMA transfer for a particular DMA
channel.

• DACK3 – DACK0 (DMA channel acknowledge):

Acknowledges a channel DMA request from a
device.

• HRQ (Hold request): Requests a DMA transfer.

• HLDA (Hold acknowledge) signals the 8237 that

the microprocessor has relinquished control of
the address, data and control buses.
 DMA
Some important signal pins:

• AEN (Address enable): Enables the DMA address

latch connected to the 8237 and disable any buffers
in the system connected to the microprocessor. (Use
to take the control of the address bus from the
microprocessor)

• ADSTB (Address strobe): Functions as ALE to latch

address during the DMA transfer.

• EOP (End of process): bi direction, Signals the end

of the DMA process.

• IOR (I/O read): bi-dir, Used as an input strobe to

read data from the 8237 during programming and
used as an output strobe to read data from the port
during a DMA write cycle.
 DMA
Some important signal pins:

• IOW (I/O write): bi-dir Used as an input strobe

to write data to the 8237 during programming and
used as an output strobe to write data to the port
during a DMA read cycle.

• MEMW (Memory write): Used as an output to

cause memory to write data during a DMA write
cycle.

• MEMR (Memory read): Used as an output to

cause memory to read data during a DMA read
cycle

• A3 – A0 : address pins select an internal register

during programming and provide part of the DMA
transfer address during DMA operation.
 DMA

Some important signal pins:

• A7 – A4 : address pins are outputs that provide

part of the DMA transfer address during a DMA
operation.

• DB0 – DB7 : data bus, connected to

microprocessor and are used during the
programming DMA controller.
 Internal registers:
•8237 supports four DMA channels
It has the following internal register

• CAR : The current address register, is used to hold the 16-bit

memory address used for the DMA transfer.

• CWCR : The current word count register, programs a channel for the number
of bytes (up to 64K) transferred during a DMA action.

• BA & BWC : The base address and base word count , registers
are used when auto-initialization is selected for a channel. In this mode, their
contents will be reloaded to the CAR and CWCR after the DMA action is
completed.

• The command register (CR) programs the operation of the

8237 DMA controller
• MR : The mode register, programs the mode of operation for a
channel. Each channels has its own mode register (RD/WR-INC/DEC..)

• RR : The request register, is used to request a DMA transfer

via software, which is very useful in memory-to-memory
Transfers where external signals is not available for DMA transfer

• MRSR :Used to disable a specific channel

The mask register set/reset, sets or clears the channel
mask to disable or enable particular DMA channels. If the mask is set,
The channel is disabled

• MSR : The mask register, clears or sets all of the masks with
one command instead of individual channels as with the
MRSR.

• SR : The status register, shows the status of each DMA channel. TC

Bits indicate, terminal count

TR:Temporary register: Used for memory-to-memory transfers

 Addresses
• 0000 = Base and Current Address (Ch0)
• 0001 = Base and Current Word (Ch0)
• 0010 = Base and Current Address (Ch1)
• 0011 = Base and Current Word (Ch1)
• 0100 = Base and Current Address (Ch2)
• 0101 = Base and Current Word (Ch2)
• 0110 = Base and Current Address (Ch3)
• 0111 = Base and Current Word (Ch3)
 Addresses
• 1000 = RD Status / WR Command
• 1001 = Request Register
• 1010 = RD Command / WR single Mask bit
• 1011 = Mode Register
• 1100 = Set/ Clear Last F/F
• 1101 = Read Temp Register / Master clear
• 1110 = CLR mode , counter / clear mask
• 1111 = All Masks bit
 DMA
Programming the address & count register
Operation signals InternalData bus
Channel Register CS IOR IOW A3 A2 A1 A0 f/f DB0 - DB7
0 0 1 0 0 0 0 0 0 A0-A7
Base & Current addr w rite 0 1 0 0 0 0 0 1 A8-A15
0 0 1 0 0 0 0 0 A0-A7
Current addr read 0 0 1 0 0 0 0 1 A8-A15
0 1 0 0 0 0 1 0 W0-W7
Base & Current w ord w rite 0 1 0 0 0 0 1 1 W8-W15
0 0 1 0 0 0 1 0 W0-W7
Current w ord read 0 0 1 0 0 0 1 1 W8-W15
1 0 1 0 0 0 1 0 0 A0-A7
Base & Current addr w rite 0 1 0 0 0 1 0 1 A8-A15
0 0 1 0 0 1 0 0 A0-A7
Current addr read 0 0 1 0 0 1 0 1 A8-A15
0 1 0 0 0 1 1 0 W0-W7
Base & Current w ord w rite 0 1 0 0 0 1 1 1 W8-W15
0 0 1 0 0 1 1 0 W0-W7
Current w ord read 0 0 1 0 0 1 1 1 W8-W15
2 0 1 0 0 1 0 0 0 A0-A7
Base & Current addr w rite 0 1 0 0 1 0 0 1 A8-A15
0 0 1 0 1 0 0 0 A0-A7
Current addr read 0 0 1 0 1 0 0 1 A8-A15
0 1 0 0 1 0 1 0 W0-W7
Base & Current w ord w rite 0 1 0 0 1 0 1 1 W8-W15
0 0 1 0 1 0 1 0 W0-W7
Current w ord read 0 0 1 0 1 0 1 1 W8-W15
3 0 1 0 0 1 1 0 0 A0-A7
Base & Current addr w rite 0 1 0 0 1 1 0 1 A8-A15
0 0 1 0 1 1 0 0 A0-A7
Current addr read 0 0 1 0 1 1 0 1 A8-A15
0 1 0 0 1 1 1 0 W0-W7
Base & Current w ord w rite 0 1 0 0 1 1 1 1 W8-W15
0 0 1 0 1 1 1 0 W0-W7
Current w ord read 0 0 1 0 1 1 1 1 W8-W15

DMA channel & I/O port address

Advanced Microprocessor 17
 DMA

8237A – 5 Command & control port assignment

Signals Operation
A3 A2 A1 A0 IOR IOW
1 0 0 0 0 1 Read status register
1 0 0 0 1 0 Write command
1 0 0 1 0 1 Illegal
1 0 0 1 1 0 Write request register
1 0 1 0 0 1 Illegal
1 0 1 0 1 0 Write single mask
1 0 1 1 0 1 Illegal
1 0 1 1 1 0 Write mode register
1 1 0 0 0 1 Illegal
1 1 0 0 1 0 Clear byte pointer
1 1 0 1 0 1 Read temporary
1 1 0 1 1 0 Master clear
1 1 1 0 0 1 Illegal
1 1 1 0 1 0 Clear mask register
1 1 1 1 0 1 Illegal
1 1 1 1 1 0 Write all mask register

Advanced Microprocessor 18
 DMA

Data Transfer modes:

Single Transfer Mode

• In Single Transfer mode the device is programmed to make one

transfer only.

• The word count will be decremented and the address

decremented or incremented following each transfer.

Advanced Microprocessor 19
 DMA

Block Transfer Mode

• In Block Transfer mode the device is activated by DREQ to

continue making transfers during the service until a TC, caused
by word count going to FFFFH, or an external End of Process
(EOP) is encountered.

• DREQ need only be held active until DACK becomes active.

Again, an Autoinitialization will occur at the end of the service
if the channel has been programmed for it.

Advanced Microprocessor 20
 DMA

Demand Transfer Mode:

• In Demand Transfer mode the device is programmed to continue
making transfers until a TC or external EOP is encountered or until
DREQ goes inactive.

• Transfers may continue until the I/O device has exhausted its data
capacity. the DMA service can be re-established by means of a DREQ.

• During the time between services when the microprocessor is

allowed to operate, the intermediate values of address and word count
are stored in the 8237A Current Address and Current Word Count
registers.

• EOP can cause an Autoinitialize at the end of the service. EOP is

generated either by TC or by an external signal.

Advanced Microprocessor 21
 DMA

Cascade Mode:
• more than one 8237A
together for simple system
expansion.

•The HRQ and HLDA signals

from the additional 8237A are
connected to the DREQ and
DACK signals of a channel of
the initial 8237A.

•This allows the DMA requests

of the additional device to
propagate through the priority
network circuitry of the
preceding device.

Advanced Microprocessor 22
 DMA

Internal registers:

• CAR : The current address register, is used to hold the 16-bit

memory address used for the DMA transfer.

• CWCR : The current word count register, programs a channel for

the number of bytes (up to 64K) transferred during a DMA action.

• BA & BWC : The base address and base word count , registers
are used when auto-initialization is selected for a channel. In this
mode, their contents will be reloaded to the CAR and CWCR after
the DMA action is completed.

• The command register (CR) programs the operation of the

8237 DMA controller

• Each channel has its own CAR, CWCR, BA and BWC.

Advanced Microprocessor 25
 DMA

• MR : The mode register, programs the mode of operation for a

channel. Each channels has its own mode register

• RR : The request register, is used to request a DMA transfer

via software, which is very useful in memory-to-memory
Transfers where external signals is not available for DMA transfer

• MRSR : The mask register set/reset, sets or clears the channel

mask to disable or enable particular DMA channels. If the mask is set,
The channel is disabled

• MSR : The mask register, clears or sets all of the masks with
one command instead of individual channels as with the
MRSR.

• SR : The status register, shows the status of each DMA channel. TC

Bits indicate, terminal count

Advanced Microprocessor 26
 DMA

8237A-5 Command register 8237A-5 Mode register

2 2 CP
4 CP

Advanced Microprocessor 27
 DMA
8237A-5 Request register
8237A-5 mask set / reset register

8237A-5 Mask register 8237A-5 Status register

Advanced Microprocessor 28
 DMA

Data Transfer modes:

Single Transfer Mode

• In Single Transfer mode the device is programmed to make one
transfer only.

• The word count will be decremented and the address

decremented or incremented following each transfer.

• When the word count ``rolls over'' from zero to FFFFH, a

Terminal Count (TC) will cause an Auto initialize if the channel
has been programmed to do so.

Advanced Microprocessor 29
 DMA

Block Transfer Mode

• In Block Transfer mode the device is activated by DREQ to

continue making transfers during the service until a TC, caused
by word count going to FFFFH, or an external End of Process
(EOP) is encountered.

• DREQ need only be held active until DACK becomes active.

Again, an Autoinitialization will occur at the end of the service
if the channel has been programmed for it.

Advanced Microprocessor 30
 DMA

Demand Transfer Mode:

• In Demand Transfer mode the device is programmed to continue
making transfers until a TC or external EOP is encountered or until
DREQ goes inactive.

• Transfers may continue until the I/O device has exhausted its data
capacity. the DMA service can be re-established by means of a DREQ.

• During the time between services when the microprocessor is

allowed to operate, the intermediate values of address and word count
are stored in the 8237A Current Address and Current Word Count
registers.

• EOP can cause an Autoinitialize at the end of the service. EOP is

generated either by TC or by an external signal.

Advanced Microprocessor 31
 DMA

Cascade Mode:
• more than one 8237A
together for simple system
expansion.

•The HRQ and HLDA signals

from the additional 8237A are
connected to the DREQ and
DACK signals of a channel of
the initial 8237A.

•This allows the DMA requests

of the additional device to
propagate through the priority
network circuitry of the
preceding device.

Advanced Microprocessor 32
 DMA
Software Command:
• There are 3 software commands used to control the operation
of the 8237.

• These commands do not have a binary bit pattern,

• A simple output to the correct port number enables the software

command.

Software commands,
- Clear the first/last f/f : clear the first/last f/f within the 8237.
if F/L = 0, the low order byte is selected for read/write in the
current address & current count register.
if F/L = 1, the high order byte is selected for read/write in the
current address & current count register.

- Master clear : acts same as RESET signal to the 8237, this command
disables all channels

- Clear mask register : Enables all 4 DMA channels.

Advanced Microprocessor 33
 DMA

Programming the 8237:

the state of the F/L f/f determines whether the LSB or MSB
Is programmed

if the state of the F/L f/f is unknown, the count and address
Could be programmed incorrectly

disable the DMA channel before programming the count &

address

There are 4 steps required to program the address and

count registers first:
1. Clear the F/L flip-flop with a clear F/L command
2. Disable the channel
3. Program the LSB and then MSB of the address
4. Program the LSB and then MSB of the count

• Additional programming is required to select the mode of

operation before the channel is enabled and started.
Advanced Microprocessor 34
 DMA Action

Memory

CPU DMA
Data – Address - Control

Handshaking
Typical DMA Module Diagram
Block Transfer Mode

• In Block Transfer mode the device is activated by DREQ to continue

making transfers during the service until a TC, caused by word count
going to FFFFH, or an external End of Process (EOP) is encountered.

• DREQ need only be held active until DACK becomes active. Again, an
Autoinitialization will occur at the end of the service
if the channel has been programmed for it.
Demand Transfer Mode:
• In Demand Transfer mode the device is programmed to continue making
transfers until a TC or external EOP is encountered or until DREQ goes inactive.

• Transfers may continue until the I/O device has exhausted its data capacity.
the DMA service can be re-established by means of a DREQ.

• During the time between services when the microprocessor is allowed to

operate, the intermediate values of address and word count are stored in the
8237A Current Address and Current Word Count registers.

• EOP can cause an Autoinitialize at the end of the service. EOP is generated
either by TC or by an external signal.
 DMA

Cascade Mode:
• more than one 8237A together
for simple system
expansion.

•The HRQ and HLDA signals from

the additional 8237A are
connected to the DREQ and
DACK signals of a channel of the
initial 8237A.

•This allows the DMA requests of

the additional device to
propagate through the priority
network circuitry of the preceding
device.

Advanced Microprocessor 40
 Data Transfer modes:

Single Transfer Mode

• In Single Transfer mode the device is programmed to make one transfer
only.

• The word count will be decremented and the address decremented or

incremented following each transfer.

• When the word count ``rolls over'' from zero to FFFFH, a Terminal Count
(TC) will cause an Auto initialize if the channel has been programmed to do
so.
 DMA
• A remote bus master microprocessor can execute variable
software but the DMA controller can only transfer data.
• Access to the shared bus for the remote bus master is
accomplished via a bus arbiter.
• A bus arbiter functions to resolve priority between bus
masters and allows only one device at a time to access the
shared bus.

Bus Arbiter:

• The 8289 bus arbiter controls the interface of a bus master

to a shared bus.

• The 8289 is designed to function with the 8086/8088

microprocessors.

Advanced Microprocessor 43
 DMA

DMA Definitions:

• DMA occurs between an I/O device and memory without the

use of the microprocessor

• DMA read transfer data from the memory to I/O device

• DMA write transfer data from the I/O to memory

• MRDC & IOWC signals to simultaneously activate for read

DMA

• DMA write signals MWTC & IORC

• DMA controller provides the memory with its address and a

signals from the controller DACK selects the I/O device, during
the DMA transfer

Advanced Microprocessor 44
 DMA
Basic DMA operation:

•The direct memory access (DMA) I/O technique provides direct

access to the memory while the microprocessor is temporarily
disabled.

• A DMA controller temporarily borrows the address bus, data

bus, and control bus from the microprocessor and transfers the
data bytes directly between an I/O port and a series of memory
locations.

• The DMA transfer is also used to do high-speed memory-to

memory transfers.

• Two control signals are used to request and acknowledge a DMA

transfer in the microprocessor-based system.

Advanced Microprocessor 45
DMA

Advanced Microprocessor 46
 DMA

Example: memory-to-device transfer

Advanced Microprocessor 47
 DMA

The 8237 DMA controller:

• The 8237 DMA controller supplies the memory and I/O with
control signals and memory address information during the DMA
transfer.

• The 8237 is a four-channel device that is compatible to the

8086/8088 microprocessors and can be expanded to include any
number of DMA channel inputs.

• The 8237 is capable of DMA transfers at rates of up to 1.6M bytes

per second.

• Each channel is capable of addressing a full 64K-byte section of

memory and can transfer up to 64K bytes with a single
programming.

Advanced Microprocessor 48
 DMA

Advanced Microprocessor 49
 DMA
Some important signal pins:

• DREQ3 – DREQ0 (DMA request): Used to

request a DMA transfer for a particular DMA
channel.

• DACK3 – DACK0 (DMA channel

acknowledge): Acknowledges a channel
DMA request from a device.

• HRQ (Hold request): Requests a DMA

transfer.

• HLDA (Hold acknowledge) signals the

8237 that the microprocessor has
relinquished control of the address, data
and control buses.

Advanced Microprocessor 50
 DMA
Some important signal pins:

• AEN (Address enable): Enables the DMA

address latch connected to the 8237 and
disable any buffers in the system connected
to the microprocessor. (Use to take the
control of the address bus from the
microprocessor)

• ADSTB (Address strobe): Functions as ALE

to latch address during the DMA transfer.

• EOP (End of process): bi direction, Signals

the end of the DMA process.

• IOR (I/O read): bi-dir, Used as an input

strobe to read data from the 8237 during
programming and used as an output strobe
to read data from the port during a DMA write
cycle. Advanced Microprocessor 51
 DMA

Some important signal pins:

• IOW (I/O write): bi-dir Used as an input

strobe to write data to the 8237 during
programming and used as an output strobe
to write data to the port during a DMA read
cycle.

• MEMW (Memory write): Used as an output

to cause memory to write data during a
DMA write cycle.

• MEMR (Memory read): Used as an output

to cause memory to read data during a DMA
read cycle

• A3 – A0 : address pins select an internal

register during programming and provide
part of the DMA transfer address during
Advanced Microprocessor 52
DMA operation.
 DMA

Some important signal pins:

• A7 – A4 : address pins are outputs that

provide part of the DMA transfer address
during a DMA operation.

• DB0 – DB7 : data bus, connected to

microprocessor and are used during the
programming DMA controller.

Advanced Microprocessor 53
 I/O Data Transfer (cont’d)
• 8237 supports four types of data transfer
– Single cycle transfer
• Only single transfer takes place
• Useful for slow devices
– Block transfer mode
• Transfers data until TC is generated or external EOP signal is
received
– Demand transfer mode
• Similar to the block transfer mode
• In addition to TC and EOP, transfer can be terminated by
deactivating DREQ signal
– Cascade mode
• Useful to expand the number channels beyond four
 Basic process of DMA
In maximum mode:
Handshaking Pins: RQ/GT1 and RQ/GT0  DMA request and acknowledge

Sequences:

1) Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has
higher priority)

2) CPU completes its current bus cycle and enters into a HOLD state

3) CPU grants the right of bus control by asserting a grant signal via the same pin
as the request signal.
4) DMA operation starts
5) Upon completion of the DMA operation, the peripheral asserts the
request/grant pin again to relinquish bus control.

In minimum mode:
The HOLD and HLDA pins are used for handshaking