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TranspRF1_v1r0

MSEI_JRG_UD1_04_Sigma_Delta

MSEI_JRG_UD1_03_ADCs

MSEI_JRG_UD1

1. Make-SoCs-flexible-with-embedded-FPGA

7. Vivado_HLS_to_Zynq_design_Summary_jgarrigos

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US7741796