Kelompok : INTEL
Anggota :
Hanafiah
13.04.1041
Leonard Sambone
13.04.1042
Agung Dwi Priyambodo 13.04.1043
M.Ali Janudin
13.04.1048
7 Assembly Language
Programs
Program Bahasa
Assembly
A
s
s
e
m
b
l
e
r
Program
Bahasa
Mesin
L
i
n
k
e
r
Eksekusi
Program
Bahasa
Mesin
l
o
a
d
e
r
Memori
Konten
Symbol Table
Assembly language program
addi$s0,$zero,9
sub$t0,$s0,$s0
add$t1,$zero,$zero
test:bne$t0,$s0,done
addi$t0,$t0,1
add$t1,$s0,$zero
jtest
done:sw$t1,result($gp)
Symbol
table
done
result
test
28
248
12
Location
000100000000100000000000000001001
400000010000100000100000000100010
800000001001000000000000000100000
1200010101000100000000000000001100
1600100001000010000000000000000001
2000000010000000000100100000100000
2400001000000000000000000000000011
2810101111100010010000000011111000
oprsrtrdshfn
Field boundaries shown to facilitate understanding
Determined from assembler
directives not shown here
Program Bahasa Assembly adalah versi dari bahasa mesin dan tabel
simbol itu yang dibuat selama proses Assembly
max: .word
35000 # name & initialize data word(s)
small: .float
2E-3 # name short float (see Chapter 12)
.align
2 # align next item on word boundary
array: .space
600 # reserve 600 bytes = 150 words
str1: .ascii
a*b # name & initialize ASCII string
str2: .asciiz xyz # null-terminated ASCII string
. Penyelesaian :
a. noppr: .asciiz Warning: The printer is out of paper!
b. size: .byte 4 # small constant fits in one byte
c. width: .word 4 # byte could be enough, but ...
d. mill: .word 1000000 # constant too large for byte
e. vect: .space 1000 # 250 words = 1000 bytes
not
$s0
# complement ($s0)
nor
$s0,$s0,$zero
# complement ($s0)
abs
$t0,$s0
add
slt
beq
sub
Jan. 2011
$t0,$s0,$zero
$at,$t0,$zero
$at,$zero,+4
$t0,$zero,$s0
#
#
#
#
Slide 7
MiniMIPS
Copy
Pseudoinstructions
Arithmetic
Shift
Logic
Memory access
Control transfer
Pseudoinstruction
Usage
Move
move
regd,regs
Load address
la
regd,address
Load immediate
li
regd,anyimm
Absolute value
abs
regd,regs
Negate
neg
regd,regs
mul
regd,reg1,reg2
div
regd,reg1,reg2
Remainder
rem
regd,reg1,reg2
sgt
regd,reg1,reg2
sle
regd,reg1,reg2
sge
regd,reg1,reg2
Rotate left
rol
regd,reg1,reg2
Rotate right
ror
regd,reg1,reg2
NOT
not
reg
Load doubleword
ld
regd,address
Store doubleword
sd
regd,address
blt
reg1,reg2,L
bgt
reg1,reg2,L
ble
reg1,reg2,L
bge
reg1,reg2,L
Penyelesaian :
.macro mx3r(m,a1,a2,a3)
move
m,a1
bge
m,a2,+4
move
m,a2
bge
m,a3,+4
move
m,a3
.endmacro
Jika makro digunakan sebagai mx3r ($ t0, $ s0, $ S4, $ s3), assembler menggantikan
argumen m, a1, a2, a3 dengan $ t0, $ s0, $ S4, $ s3, berurutan
Result
1 Print integer
Integer in $a0
Integer displayed
2 Print floating-point
Float in $f12
Float displayed
3 Print double-float
Double-float in $f12,$f13
Double-float displayed
4 Print string
Pointer in $a0
Cntl
Input
Output
($v0) Function
5 Read integer
6 Read floating-point
7 Read double-float
8 Read string
9 Allocate memory
Slide 13
Menu bar
PCSpim
User
Interface
Tools bar
PCSpim
File Simulator Window Help
File
Open
Sav e Log File
Ex it
Simulator
Clear Regis ters
Reinitializ e
Reload
Go
Break
Continue
Single Step
Multiple Step ...
Breakpoints ...
Set Value ...
Disp Symbol Table
Settings ...
Window
Tile
1 Messages
2 Tex t Segment
3 Data Segment
4 Regis ters
5 Console
Clear Console
Toolbar
Status bar
Status bar
Registers
PC
= 00400000
Status = 00000000
R0
R1
(r0) = 0
(at) = 0
EPC
= 00000000
Cause = 00000000
HI
= 00000000
LO
= 00000000
General Registers
R8 (t0) = 0
R16 (s0) = 0
R24
R9 (t1) = 0
R17 (s1) = 0
R25
Text Segment
[0x00400000]
[0x00400004]
[0x00400008]
[0x0040000c]
[0x00400010]
0x0c100008
0x00000021
0x2402000a
0x0000000c
0x00000021
;
;
;
;
;
43
44
45
46
47
Data Segment
DATA
[0x10000000]
[0x10000010]
[0x10000020]
Messages
See the file README for a full copyright notice.
Memory and registers have been cleared, and the simulator rei
D:\temp\dos\TESTS\Alubare.s has been successfully loaded
8 Instruction Set
Variations
Slide 15
Instruction
Instruction
Instruction
Instruction
Microinstruction
Microinstruction
Microinstruction
Microinstruction
Microinstruction
31
31
31
op
25
rs
20
rt
15
rd
10
sh
fn
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
Opcode
Source
register 1
Source
register 2
Destination
register
Shift
amount
Opcode
extension
op
25
rs
20
rt
15
operand / offset
6 bits
5 bits
5 bits
16 bits
Opcode
Source
or base
Destination
or data
Immediate operand
or address offset
op
6 bits
Opcode
Jan. 2011
25
Dapat memulai
pembacaan register
Memory word address (byte address divided by 4)
bahkan sebelum
decoding instruksi
Computer Architecture, Instruction0
1 0 0 0 0 0 0 0 0 0 0 0 260 bits
0 0 0 0 0 0 0 1 1 1 1 0 1
Set Architecture
Slide 16
Machine
Instruction
Effect
Pentium
MOVS
PowerPC
cntlzd
IBM 360-370
CS
Digital VAX
POLYD
Jan. 2011
Destination
string
cntlzd
6 leading 0s
POLYD
(Polynomial evaluation in
double floating-point)
Coefficients
MOVS
(Move string)
Jan. 2011
Slide 18
Jan. 2011
Set Architecture
Slide 19
Instruction
Implied
Lets
refresh
our
memory
(from
Chap. 5)
Extend,
if required
Immediate
Reg spec
Register
Reg file
Constant offset
Base
Reg base
PC-relative
Reg file
Reg
data
Constant offset
Reg data
Mem
Add addr
Mem
Add addr
PC
Pseudodirect
Operand
PC
Mem
Memory data
Mem
Memory data
Mem
addr Memory Mem
data
Slide 20
Table 6.2
Instruction
Usage
Instruction
Usage
lui
rt,imm
Move from Hi
mfhi
rd
Add
add
rd,rs,rt
Move from Lo
mflo
rd
Subtract
sub
rd,rs,rt
Add unsigned
addu
rd,rs,rt
slt
rd,rs,rt
Subtract unsigned
subu
rd,rs,rt
Add immediate
addi
rt,rs,imm
Multiply
mult
rs,rt
slti
rd,rs,imm
Multiply unsigned
multu rs,rt
AND
and
rd,rs,rt
Divide
div
rs,rt
OR
or
rd,rs,rt
Divide unsigned
divu
rs,rt
XOR
xor
rd,rs,rt
addiu rs,rt,imm
NOR
nor
rd,rs,rt
sll
rd,rt,sh
AND immediate
andi
rt,rs,imm
srl
rd,rt,sh
OR immediate
ori
rt,rs,imm
sra
rd,rt,sh
XOR immediate
xori
rt,rs,imm
sllv
rd,rt,rs
Load word
lw
rt,imm(rs)
srlv
rd,rt,rs
Store word
sw
rt,imm(rs)
srav
rd,rt,rs
Jump
Load byte
lb
rt,imm(rs)
Jump register
jr
rs
lbu
rt,imm(rs)
bltz
rs,L
Store byte
sb
rt,imm(rs)
Branch
equal
Jan. 2011
beq
Computer Architecture,
Instructionrs,rt,L
Jump
and link
jal
bne
rs,rt,L
Set Architecture
System call
syscall
Slide 21
Instruction
Indexed
Reg file
Index reg
Base reg
Increment amount
Update
(with base)
Base reg
Update
(with index ed)
Reg file
Increment
amount
Indirect
Reg file
Base reg
Index reg
Operand
x := B[i]
Mem
Mem
Add addr Memory data
x := Mem[p]
p := p + 1
Mem
Incre- addr
Mem
Memory data
ment
Mem
Mem
Add addr Memory data
x := B[i]
i := i + 1
Increment
Mem data
PC
Memory
Mem addr
This part maybe replaced with any
Mem addr,
other form of address specif ication
2nd access
Memory
Mem data,
2nd access
t := Mem[p]
x := Mem[t]
x := Mem[Mem[p]]
Slide 22
$t0,A($s0)
$s1,$s1,$t0
$s0,$s0,-1
$s0,$zero,loop
Branch to location Li
if s = i (switch var.)
T
T+4
T+8
T + 12
T + 16
T + 20
L0
L1
L2
L3
L4
L5
Slide 23
Format
Opcode
Description of operand(s)
One implied operand in register $v0
0-address
1-address
2-address
0 rs rt
24 mult
3-address
0 rs rt rd
32 add
12 syscall
Address
Jan. 2011
Slide 24
Push b
Add
Push d
Push c
Subtract
Multiply
b
a
a+b
d
a+b
c
d
a+b
cd
a+b
Result
Polish string: a b + d c
a
b
t
c
d
t
Slide 26
Two-Address Architectures
Dua alamat dapat digunakan dalam berbagai cara
Operand1/result and operand 2
Condition to be checked and branch target address
Example: Evaluating the expression (a + b) (c d)
load
add
load
subtract
multiply
$1,a
$1,b
$2,c
$2,d
$1,$2
Instructions of a hypothetical
two-address machine
Variasi yang mengunakan salah satu alamat seperti pada oneaddress machine dan yang kedua untuk menentukan cabang di
setiap instruksi
Jan. 2011
Slide 27
Operand/address
size overwrites and
other modifiers
Opcode (1-2 B)
ModR/M
SIB
Most memory
operands need
these 2 bytes
Instructions can
contain
up to 15 bytes
Immediate (0, 1, 2, or 4 B)
Components that form a variable-length IA-32 (80x86) instruction.
Jan. 2011
Slide 28
1-byte
5 3
2-byte
4 4
3-byte
4-byte
5-byte
4 3
6-byte
8
8
8
32
32
Opcode
Description of operand(s)
PUSH
JE
MOV
XOR
ADD
TEST
Slide 29
Processor
design
team
New
machine
project
Instruction-set
definition
Implementation
Performance
objectives
Fabrication &
testing
Sales
&
use
?
Tuning &
bug fixes
Feedback
Figure 8.4
ISA memiliki dua kelas sederhana (S) dan kompleks (C) instruksi.
Pada implementasi referensi dari ISA, instruksi kelas-S account
untuk 95% dari waktu berjalan untuk program menarik. Sebuah
versi RISC mesin sedang dipertimbangkan yang mengeksekusi
hanya petunjuk kelas-S secara langsung dalam perangkat keras,
dengan instruksi kelas C diperlakukan sebagai petunjuk semu.
Diperkirakan dalam versi RISC, instruksi kelas-S akan berjalan
20% lebih cepat sementara instruksi kelas-C akan melambat
dengan faktor 3. Apakah pendekatan RISC menawarkan lebih baik
atau kinerja buruk dibandingkan dengan implementasi referensi?
Solusinya : Per asumsi, 0,95 dari pekerjaan dipercepat dengan
faktor 1,0 / 0,8 = 1,25, sedangkan sisanya 5% diperlambat
dengan faktor 3. RISC speedup adalah 1 / [0.95 / 1.25 + 0,05 x 3]
= 1.1. Dengan demikian, peningkatan 10% dalam kinerja dapat
diharapkan dalam versi RISC.
Slide 34
at1,at1,+1
at1,src1,+1
at1,src2,+1
dest,dest,+1
dest,at1,+1
at1,at1,+1
at1,one,label
#
#
#
#
#
#
#
at1 = 0
at1 = -(src1)
at1 = -(src1)(src2)
dest = 0
dest = -(at1)
at1 = 0
at1 = -1 to force jump
URISC Hardware
URISC instruction:
Word 1
Word 2
Word 3
Source 1
Source 2 / Dest
Jump target
Comp
0
C in
PC in
MDR in
P
C
Adder
N in
R in
Write
Read
MAR in
Z in
N
M
D
R
1 Mux 0
M
A
R
Memory
unit
PCout
Slide 38