FAKULTAS TEKNIK
DEPARTEMEN TEKNIK ELEKTRO
(ELECTRICAL ENGINEERING STUDY PROGRAM – BACHELOR DEGREE)
TUGAS 02
(ASSIGNMENT)
s=’00's=’01'
en=0 z=’01'
z=’10' en=1 z=’11'
en=1 z=’11' en=0
s=’11' s=’10'
en=1
z=’11'z=’00'
en=0
0 0 0 0 0 X 0 X 0 1 0 X 1 X 0 0 1 1
0 1 0 0 0 X X 1 1 0 1 X X 1 0 1 1 1
1 0 1 0 X 0 0 X 1 1 X 0 1 X 0 0 1 1
1 1 1 0 X 0 X 1 0 0 X 1 X 1 1 0 1 1
S1 S0 S1 S J K J K0 S S0 J K J K0 Z1 Z0 Z1 Z0
0 1 1 0 1 1 1 0
J1
S1S0
00 En 01 11 10
J1 = EnS0
0 0 0 X X
1 0 1 X X
K1
S1S0
En K1 = EnS0
0
x x 0 0
00
x 01
x 11
1 10
0
1
J0
S1S0
00 01 11 10 J0 = En
En
0 0 x x 0
1 1 x x 1
K
0
S1S0 K0 = 1
En
x 1 1 X
0
00
x 01
1 11
1 10
x
Z1
0 Z1 = En+S1S0
00 01 11 10
1 0 0 1 0
1 1 1 1
Z0
0
00 01 11 10
Z0 = En+S1’S0
1 0 1 0 0
1 1 1 1
2. Rancanglah rangkaian logika dari sistem digital yang digambarkan
dengan diagram keadaan berikut ini menggunakan flipflop-JK.
en=0
en=1
s=’00' s=’01'
z=’00' z=’01'
en=0
en=1
en=1
en=0
s=’11' s=’10'
z=’11' z=’10'
en=1
en=0
0 0 0 0 0 X 0 X 0 1 0 X 1 X 0 0 0 1
0 1 0 0 0 X X 1 1 0 1 X X 1 0 0 1 0
1 0 1 0 X 0 0 X 1 1 X 0 1 X 1 0 1 1
1 1 1 0 X 0 X 1 0 0 X 1 X 1 1 0 0 0
S1 S0 S1 S J K J K0 S S0 J K J K0 Z1 Z0 Z1 Z0
0 1 1 0 1 1 1 0
J1
S1S0
00 En 01 11 10
J1 = EnS0
0 0 0 X X
S1S0
En 1
0 1 X X
K1
S1S0
En K1 = EnS0
0
x x 0 0
00
x 01
x 11
1 10
0
1
J0
S1S0
00 01 11 10 J0 = En
En
0 0 x x 0
1 1 x x 1
K
0
S1S0 K0 = 1
En
x 1 1 X
0
00
x 01
1 11
1 10
x
Z1
0 Z1 = En’S1+S1S0’+EnS1’S0
00 01 11 10
1 0 0 1 1
0 1 0 1
Z0
S1S0
EnS1S0
00 01 11 10
En
0 Z0 = EnS0’
0 0 0 0
1
1 0 0 1
S1S0
En