Disusun Oleh
NIM : 20302241008
2021
I. Tujuan
A. Membiasakan mengenali letak dan fungsi pin (kaki) pada IC gerbang logika dasar.
B. Memahami cara kerja gerbang logika dasar.
C. Menyusun suatu unit rangkaian dari gerbang logika dasar sedemikian hingga
membentuk suatu sistem rangkaian dengan fungsi tertentu.
II. Data dan Analisis Data
A. Tabel Data Hasil Percobaan
1. Rangkaian Gerbang AND
A B Volt LED
0 0 0 0
(mati)
0 1 0 0
(mati)
1 0 0 0
(mati)
1 1 +2.36 1
(hidup
)
2. Rangkaian Gerbang OR
A B Volt LED
0 0 0 0
(mati)
0 1 +2.36 1
(hidup)
1 0 +2.36 1
(hidup)
1 1 +2.36 1
(hidup)
3. Rangkaian Gerbang NOT
0 +2.36 1
(hidup)
1 0 0
(mati)
A B Volt LED
0 0 +2.36 1
(hidup)
0 1 +2.36 1
(hidup)
1 0 +2.36 1
(hidup)
1 1 0 0
(mati)
A B Volt LED
0 0 +2.36 1
(hidup
)
0 1 0 0
(mati)
1 0 0 0
(mati)
1 1 0 0
(mati)
A B Volt LED
0 0 0 0
(mati)
0 1 +2.28 1
(hidup)
1 0 +2.28 1
(hidup)
1 1 0 0
(mati)
A B Volt LED
0 0 +2.28 1
(hidup
)
0 1 0 0
(mati)
1 0 0 0
(mati)
1 1 +2.28 1
(hidup
)
Input Output
0 0 0
0 1 0
1 0 0
1 1 1
Gerbang logika AND dengan menggunakan IC-7408 memiliki dua input dan
satu output. Berdasarkan simulasi, tegangan yang dihasilkan apabila A dan B
dihubungkan ke ground akan menghasilkan tegangan 0 V atau sama dengan
logika Nol. Kemudian, apabila A dihubungkan ke ground dan B dihubungkan ke
baterai 5 V menghasilkan tegangan 0 V atau sama dengan logika Nol.
Selanjutnya, apabila A dihubungkan ke baterai 5 V dan B dihubungkan ke ground
menghasilkan tegangan 0 V atau sama dengan logika Nol. Terakhir, apabila A
dan B dihubungkan ke baterai 5 V menghasilkan tegangan +2.36 V atau sama
dengan logika Satu. Jika dibandingkan dengan tabel kebenaran maka nilainya
sesuai.
2. Rangkaian Gerbang OR
Tabel kebenaran gerbang OR
Input Output
0 0 0
0 1 1
1 0 1
1 1 1
Input Output
0 1
1 0
Gerbang logika NOT dengan menggunakan IC-7404 memiliki satu input dan
satu output. Berdasarkan simulasi, tegangan yang dihasilkan apabila A
dihubungkan ke ground akan menghasilkan tegangan +2.36 V atau sama dengan
logika Satu. Kemudian apabila A dihubungkan ke Baterai 5 V menghasilkan
tegangan 0 V atau sama dengan logika Nol. Jika dibandingkan dengan tabel
kebenaran maka nilainya sesuai.
Input Output
0 0 1
0 1 1
1 0 1
1 1 0
Input Output
0 0 1
0 1 0
1 0 0
1 1 0
Gerbang logika NOR dengan menggunakan IC-7402 memiliki dua input dan
satu output. Berdasarkan simulasi, tegangan yang dihasilkan apabila A dan B
dihubungkan ke ground akan menghasilkan tegangan +2.36 V atau sama dengan
logika Satu. Kemudian, apabila A dihubungkan ke ground dan B dihubungkan
ke baterai 5 V menghasilkan tegangan 0 V atau sama dengan logika Nol.
Selanjutnya, apabila A dihubungkan ke baterai 5 V dan B dihubungkan ke ground
menghasilkan tegangan 0 V atau sama dengan logika Nol. Terakhir, apabila A
dan B dihubungkan ke baterai 5 V menghasilkan tegangan 0 V atau sama dengan
logika Nol. Jika dibandingkan dengan tabel kebenaran maka nilainya sesuai.
Input Output
0 0 0
0 1 1
1 0 1
1 1 0
Input Output
0 0 0
0 1 1
1 0 1
1 1 0
III. Pembahasan
Pada praktikum kali ini, dilakukan percobaan tentang gerbang logika. Tujuan
dari praktikum ini, yaitu membiasakan mengenali letak dan fungsi pin (kaki) pada IC
gerbang logika dasar, memahami cara kerja gerbang logika dasar, dan menyusun suatu
unit rangkaian dari gerbang logika dasar sedemikian hingga membentuk suatu sistem
rangkaian dengan fungsi tertentu. Adapun alat yang digunakan yaitu laptop dan
aplikasi Proteus 8 Professional.
Gerbang (gate) logika adalah suatu rangkaian digital yang mempunyai satu atau
lebih input dan hanya mempunyai satu output. Output gerbang logika ini tergantung
sinyal yang diberikan pada inputnya. Keluarannya dapat tinggi/High (1) atau
rendah/Low (0) tergantung level digital yang diberikan pada terminal input. Gerbang
logika yang digunakan pada praktikum ini, yaitu gerbang AND, OR, NOT, NAND,
NOR, EX-OR, dan EX-NOR.
A. Rangkaian Gerbang AND
Pada rangkaian gerbang AND menggunakan satu gerbang IC-7408 yang
memiliki dua input dan satu output. Adapun bentuk, posisi, dan fungsi pin (kaki)
dari IC seri 7408 (gerbang AND 2-masukan) adalah sebagai berikut :
Sifat logika dari rangkaian gerbang AND ini sama dengan rangkaian saklar seri.
Artinya, apabila salah satu saklar terputus maka arus tidak dapat mengalir. Hal ini
sesuai dengan data hasil percobaan. Apabila masukkan diberi tegangan rendah atau
salah satu diberi tegangan rendah, keluaran akan menghasilkan tegangan rendah
dan LED mati. Sebaliknya, apabila semua masukkan diberi tegangan tinggi maka
arus dapat mengalir dan LED hidup.
B. Rangkaian Gerbang OR
Pada rangkaian gerbang OR menggunakan satu gerbang IC-7432 yang memiliki
dua input dan satu output. Adapun bentuk, posisi, dan fungsi pin (kaki) dari IC seri
7432 (gerbang OR 2-masukan) adalah sebagai berikut :
Sifat logika dari rangkaian gerbang OR ini sama dengan rangkaian saklar
paralel. Artinya, apabila salah satu saklar terputus maka arus tetap dapat mengalir.
Hal ini sesuai dengan data hasil percobaan. Apabila masukkan diberi tegangan
tinggi atau salah satu diberi tegangan tinggi, keluaran akan menghasilkan tegangan
tinggi dan LED hidup. Namun, apabila semua masukkan diberi tegangan rendah
maka arus tidak dapat mengalir dan LED mati.
C. Rangkaian Gerbang NOT
Pada rangkaian gerbang NOT menggunakan satu gerbang IC-7404 yang
memiliki satu input dan satu output. Adapun bentuk, posisi, dan fungsi pin (kaki)
dari IC seri 7404 (gerbang NOT) adalah sebagai berikut :
dengan A1 merupakan masukan dan O1 merupakan keluaran.
Prinsip kerja rangkaian gerbang NAND, yaitu kebalikan dari gerbang AND.
Hal ini sesuai dengan data hasil percobaan. Apabila masukkan diberi tegangan
rendah atau salah satu diberi tegangan rendah, keluaran akan menghasilkan
tegangan tinggi dan LED hidup. Namun, apabila semua masukkan diberi tegangan
tinggi maka arus tidak dapat mengalir ke LED dan LED mati.
Prinsip kerja rangkaian gerbang Ex-OR, yaitu ketika kedua masukkan diberi
tegangan rendah atau keduanya diberi tegangan tinggi, keluaran akan menghasilkan
tegangan rendah dan LED mati. Namun, apabila salah satu masukan diberi tegangan
tinggi atau salah satu diberi masukan rendah maka arus dapat mengalir ke LED dan
LED hidup.
G. Rangkaian Gerbang EX-NOR
Rangkaian gerbang Ex-NOR atau exclusive NOT OR menggunakan satu
gerbang IC-4077 yang memiliki dua input dan satu output. Adapun bentuk, posisi,
dan fungsi pin (kaki) dari IC seri 4077 (gerbang Ex-NOR 2-masukan) adalah
sebagai berikut :
Prinsip kerja rangkaian gerbang Ex-NOR kebalikan dari rangkaian gerbang Ex-
OR. Apabila kedua masukkan diberi tegangan rendah atau keduanya diberi
tegangan tinggi, keluaran akan menghasilkan tegangan tinggi dan LED hidup.
Namun, apabila salah satu masukan diberi tegangan tinggi atau salah satu diberi
masukan rendah maka arus tidak dapat mengalir ke LED dan LED mati.
IV. Kesimpulan
A. Letak dan fungsi pin (kaki) pada IC gerbang logika dasar, yaitu :
1. IC-7408
a. A berfungsi untuk masukan pertama
b. B berfungsi untuk masukan kedua
c. O berfungsi untuk keluaran
d. Vcc berfungsi menghubungkan ke power supply
e. Gnd berfungsi menghubungkan ke ground
2. IC-7432
2. Gerbang logika OR
Menghubungkan kabel input pada lubang nomor 1 (A) dan 2 (B) dan keluaran
dipasang pada lubang nomor 3 (O).
3. Gerbang logika NOT
Menghubungkan kabel input pada lubang nomor 1 (A) dan keluaran dipasang
pada lubang nomor 2 (O).
V. Daftar Pustaka
https://www.dicoding.com/blog/gerbang-logika-dan-tabel-kebenaran/. Diakses pada
hari Senin, 27 September 2021 pukul 15.19 WIB.
https://www.hajarfisika.com/2018/01/laporan-praktikum-gerbang-logika.html.
Diakses pada hari Selasa, 28 September 2021 pukul 10.30 WIB.
http://nurikasandi.blogspot.com/2019/10/laporan-gerbang-logika.html. Diakses pada
hari Selasa, 28 September 2021 pukul 10.35 WIB.
https://www.academia.edu/33401822/Laporan_Praktikum_EX_OR_dan_EX_NOR_d
ocx. Diakses pada hari Selasa, 28 September 2021 pukul 17.20 WIB.
VI. Lampiran
DM7408 Quad 2-Input AND Gates
August 1986
Revised July 2001
DM7408
Quad 2-Input AND Gates
General Description
This device contains four independent gates each of which
performs the logic AND function.
Ordering Code:
Order Number Package Number Package Description
DM7408N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.4 3.4 V
Output Voltage VIL = Max
VOL LOW Level VCC = Min, IOL = Max
0.2 0.4 V
Output Voltage VIH = Min
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −18 −55 mA
ICCH Supply Current with Outputs HIGH VCC = Max 11 21 mA
ICCL Supply Current with Outputs LOW VCC = Max 20 33 mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol Parameter Conditions Min Max Units
tPLH Propagation Delay Time CL = 15 pF
27 ns
LOW-to-HIGH Level Output RL = 400Ω
tPHL Propagation Delay Time
19 ns
HIGH-to-LOW Level Output
www.fairchildsemi.com 2
DM7408 Quad 2-Input AND Gates
Physical Dimensions inches (millimeters) unless otherwise noted
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
3 www.fairchildsemi.com
DM74LS32 Quad 2-Input OR Gate
June 1986
Revised March 2000
DM74LS32
Quad 2-Input OR Gate
General Description
This device contains four independent gates each of which
performs the logic OR function.
Ordering Code:
Order Number Package Number Package Description
DM74LS32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.7 3.4 V
Output Voltage VIH = Min
VOL LOW Level VCC = Min, IOL = Max
0.35 0.5
Output Voltage VIL = Max V
IOL = 4 mA, VCC = Min 0.25 0.4
II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA
IOS Short Circuit Output Current VCC = Max (Note 3) −20 −100 mA
ICCH Supply Current with Outputs HIGH VCC = Max 3.1 6.2 mA
ICCL Supply Current with Outputs LOW VCC = Max 4.9 9.8 mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 2 kΩ
Symbol Parameter CL = 15 pF CL = 50 pF Units
Min Max Min Max
tPLH Propagation Delay Time
3 11 4 15 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
3 11 4 15 ns
HIGH-to-LOW Level Output
www.fairchildsemi.com 2
DM74LS32
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
3 www.fairchildsemi.com
DM74LS32
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com 4
DM74LS32 Quad 2-Input OR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
5 www.fairchildsemi.com
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74 Series
Features
Pin Layout
Pin Description
1 A Input Gate 1
2 Y Output Gate 1
3 A Input Gate 2
4 Y Output Gate 2
5 A Input Gate 3
6 Y Output Gate 3
7 Ground
8 Y Output Gate 4
9 A Input Gate 4
10 Y Output Gate 5
11 A Input Gate 5
12 Y Output Gate 6
13 A Input Gate 6
Dimensional Drawing
Technical Data
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air
0°C to +70°C
Temperature
Storage Temperature Range -65°C to +150°C
Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
Voh HIGH Level Output Voltage Vcc=Min Ioh=MAX Vil=MAX 2.4 3.4 V
Vol LOW Level Output Voltage Vcc=Min Iol=MAX Vih=MAX 0.2 0.4 V
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SN74LS00
VCC
14 13 12 11 10 9 8 http://onsemi.com
LOW
POWER
SCHOTTKY
1 2 3 4 5 6 7
GND
14
1
SOIC
D SUFFIX
CASE 751A
ORDERING INFORMATION
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2
SN74LS00
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M ––– 10_ ––– 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01
0.13 (0.005) M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
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3
SN74LS00
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
http://onsemi.com SN74LS00/D
4
DM7402 Quad 2-Input NOR Gates
August 1986
Revised February 2000
DM7402
Quad 2-Input NOR Gates
General Description
This device contains four independent gates each of which
performs the logic NOR function.
Ordering Code:
Order Number Package Number Package Description
DM7402N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Output
A B Y
L L H
L H L
H L L
H H L
H = HIGH Logic Level
L = LOW Logic Level
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 2)
VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max
2.4 3.4 V
Output Voltage VIL = Max
VOL LOW Level VCC = Min, IOL = Max
0.2 0.4 V
Output Voltage VIH = Min
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA
IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA
IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA
IOS Short Circuit VCC = Max
mA
Output Current (Note 3) −18 −55
ICCH Supply Current with Outputs HIGH VCC = Max 8 16 mA
ICCL Supply Current with Outputs Low VCC = Max 14 27 mA
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol Parameter Conditions Min Max Units
www.fairchildsemi.com 2
DM7402 Quad 2-Input NOR Gates
Physical Dimensions inches (millimeters) unless otherwise noted
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
3 www.fairchildsemi.com
Unit: mm
19.20
20.32 Max
14 8
7.40 Max
6.30
1 7
1.30
0° – 15°
10.06
10.5 Max
14 8
5.5
1 7
*0.22 ± 0.05
0.20 ± 0.04
2.20 Max
+ 0.20
7.80 – 0.30
1.42 Max 1.15
0° – 8°
0.10 ± 0.10
1.27 0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
0.15
0.12 M
Hitachi Code FP-14DA
JEDEC —
*Dimension including the plating thickness EIAJ Conforms
Base material dimension Weight (reference value) 0.23 g
Unit: mm
8.65
9.05 Max
14 8
3.95
1 7
1.75 Max
*0.20 ± 0.05
+ 0.10
6.10 – 0.30
0.635 Max 1.08
0° – 8°
0.11 0.60 +– 0.20
0.67
1.27 0.14 +– 0.04
*0.40 ± 0.06
0.15
0.25 M
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
Semiconductor
CD4070B,
CD4077B
CMOS Quad Exclusive-OR
June 1998 and Exclusive-NOR Gate
Features Description
• High-Voltage Types (20V Rating) The Harris CD4070B contains four independent Exclusive-
• CD4070B - Quad Exclusive-OR Gate OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.
• CD4077B - Quad Exclusive-NOR Gate
The CD4070B and CD4077B provide the system designer
• Medium Speed Operation
with a means for direct implementation of the Exclusive-OR
- tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF and Exclusive-NOR functions, respectively.
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
Ordering Information
• 5V, 10V and 15V Parametric Ratings TEMP. PKG.
• Maximum Input Current of 1µA at 18V Over Full PART NUMBER RANGE (oC) PACKAGE NO.
Package Temperature Range
CD4070BE -55 to 125 14 Ld PDIP E14.3
- 100nA at 18V and 25oC
CD4077BE -55 to 125 14 Ld PDIP E14.3
• Noise Margin (Over Full Package Temperature Range)
- 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V CD4070BF -55 to 125 14 Ld CERDIP F14.3
• Meets All Requirements of JEDEC Standard No. 13B,
CD4077BF -55 to 125 14 Ld CERDIP F14.3
“Standard Specifications for Description of ‘B’ Series
CMOS Devices CD4070BM -55 to 125 14 Ld SOIC M14.15
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
Pinouts
CD4070B CD4077B
(PDIP, CERDIP, SOIC) (PDIP, CERDIP, SOIC)
TOP VIEW TOP VIEW
A 1 14 VDD A 1 14 VDD
B 2 13 H B 2 13 H
J=A⊕B 3 12 G J=A⊕B 3 12 G
K=C⊕D 4 11 M = G ⊕ H K=C⊕D 4 11 M = G ⊕ H
C 5 10 L = E ⊕ F C 5 10 L = E ⊕ F
D 6 9 F D 6 9 F
VSS 7 8 E VSS 7 8 E
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 910.1
Copyright © Harris Corporation 1998
1
CD4070B, CD4077B
Functional Diagrams
CD4070B CD4077B
1 1
A 3 A 3
2 J 2 J
J=A⊕B B B
K=C⊕D 5 J =A ⊕B 5
C 4 C 4
6 K K=C ⊕D 6 K
M=G⊕ H D D
L=E⊕F 8 8
E 10 M=G ⊕H E 10
9 L 9 L
VSS = 7 F L =E⊕F F
VDD = 14 12 12
G 11 G 11
13 M 13 M
H H
VDD
VDD
VDD p
VDD p
B†
B† p
p 2(5,9,12) n
n n
2(5,9,12) n
n VSS p
VSS p p
p VDD J
VDD p J
p n 3(4,10,11)
n 3(4,10,11) A†
p n
A†
n 1(6,8,13) n
1(6,8,13) n
VSS
VDD VSS VDD
VSS VSS
VSS VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES) (1 OF 4 IDENTICAL GATES)
A B J A B J
0 0 0 0 0 1
1 0 1 1 0 0
0 1 1 0 1 0
1 1 0 1 1 1
NOTE: NOTE:
1 = High Level 1 = High Level
0 = Low Level 0 = Low Level
J=A⊕B J=A⊕B
2
CD4070B, CD4077B
300
200
SUPPLY VOLTAGE (VDD) = 5V
150 200 SUPPLY VOLTAGE (VDD) = 5V
100 10V
100
50 15V 10V
15V
0 0
0 20 40 60 80 100 110 0 20 40 60 80 100
CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF)
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
LOAD CAPACITANCE FUNCTION OF LOAD CAPACITANCE
105
tPHL, tPLH, PROPAGATION DELAY TIME (ns)
TA = 25oC TA = 25oC
LOAD CAPACITANCE CL = 50pF V
PD, POWER DISSIPATION (µW)
104 15
)=
300 D
E (V D 10V
103 AG
O LT CL = 50pF
YV
P PL
200
102 SU 10V
CL = 15pF
10 5V
100
1
0 10-1
0 5 10 15 20 10-1 1 10 102 103 104
VDD, SUPPLY VOLTAGE (V) fI, INPUT FREQUENCY (kHz)
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF SUPPLY VOLTAGE FUNCTION OF INPUT FREQUENCY
5
CD4070B, CD4077B
N
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C B1 0.045 0.070 1.15 1.77 8
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.735 0.775 18.66 19.68 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES:
E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC -
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7
Publication No. 95.
L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3. N 14 14 9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpen-
dicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
6
CD4070B, CD4077B
SECTION A-A
b1 0.014 0.023 0.36 0.58 3
bbb S C A-B S D S
b2 0.045 0.065 1.14 1.65 -
D
BASE b3 0.023 0.045 0.58 1.14 4
PLANE Q
-C- A c 0.008 0.018 0.20 0.46 2
SEATING
PLANE c1 0.008 0.015 0.20 0.38 3
L α
S1 D - 0.785 - 19.94 5
A A eA
b2 E 0.220 0.310 5.59 7.87 5
b e eA/2 c e 0.100 BSC 2.54 BSC -
ccc M C A-B S D S aaa M C A - B S D S eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat- L 0.125 0.200 3.18 5.08 -
ed adjacent to pin one and shall be located within the shaded Q 0.015 0.060 0.38 1.52 6
area shown. The manufacturer’s identification shall not be used
S1 0.005 - 0.13 - 7
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be α 90o 105o 90o 105o -
measured at the centroid of the finished lead surfaces, when aaa - 0.015 - 0.38 -
solder dip or tin plate lead finish is applied.
bbb - 0.030 - 0.76 -
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 -
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a M - 0.0015 - 0.038 2, 3
partial lead paddle. For this configuration dimension b3 replaces N 14 14 8
dimension b2.
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.