DAFTAR ISI

KATA PENGANTAR ..................................................................... v

SINGKATAN-SINGKATAN ...................................................... viii
DAFTAR ISI .................................................................................. xi
DAFTAR GAMBAR .................................................................... xix
BAB I Prinsip–prinsip Sistem Digital.................................. 1
1.1. Pendahuluan ................................................................ 1
1.2. Perbandingan Elektronika Analog dan Digital ............ 2
1.3. Level logika digital ...................................................... 5
1.4. Sistem Bilangan Desimal ............................................ 5
1.4.1. Notasi Posisional ........................................... 6
1.5. Sistem Bilangan Biner ................................................. 7
1.5.1. Notasi Posisional ........................................... 7
1.6. Sistem Bilangan Oktal ................................................. 8
1.6.1. Notasi Posisional ........................................... 8
1.7. Sistem Bilangan Heksadesimal ................................. 10
1.7.1. Notasi Posisional ......................................... 10
1.8. Komplemen bilangan ................................................. 12
1.8.1. Komplemen-R ............................................. 12
1.8.2. Komplemen-(R-1) ....................................... 13
1.9. Sandi Biner ................................................................ 13
1.9.1. Sandi Binary Coded Decimal (BCD) .......... 14
1.9.2. Sandi Excess 3 (XS-3) ................................. 14
1.9.3. Sandi 8, 4, -2, -1 .......................................... 15
1.9.4. Sandi Gray ................................................... 15
1.9.5. Sandi Alfanumerik ...................................... 17
1.10. Bit Paritas .................................................................. 19
1.11. Logika Gerbang ......................................................... 20
1.11.1. Operator Logika Dasar ................................ 21
1.11.2. Tabel kebenaran untuk operator logika ....... 21
1.11.3. Gerbang Logika ........................................... 22

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 1.11.4. Rangkaian logika kombinasional dari
fungsi logika ................................................ 22
1.12. Referensi .................................................................... 24
1.13. Pertanyaan ................................................................. 24
BAB II Programmable Logic Device ................................... 25
2.1. Pendahuluan .............................................................. 25
2.2. Metode Pemrograman Perangkat Keras ..................... 26
2.2.1. Teknologi Fusible Link ............................... 28
2.2.2. Teknologi Antifuse ...................................... 29
2.3. Piranti Mask-Programmed ........................................ 31
2.3.1. PROM ......................................................... 32
2.3.2. Teknologi berbasis EPROM ....................... 33
2.3.3. Teknologi berbasis EEPROM ..................... 35
2.3.4. Teknologi berbasis RAM–DRAM dan
SRAM ......................................................... 36
2.4. PLD, ASIC dan FPGA .............................................. 43
2.4.1. Programmable Logic Device (PLD) ........... 43
2.4.1.1 PROM ......................................... 45
2.4.1.2 Programmable Logic Array
(PLA) .......................................... 47
2.4.1.3 Programmable Array Logic
(PAL) .......................................... 49
2.4.1.4 Complex Programmable
Logic Device (CPLD) ................. 50
2.4.2. Application Spesific Integrated Circuit
(ASIC) ......................................................... 53
2.4.3. Field Programmable Gate Array
(FPGA) ........................................................ 57
2.5. Referensi .................................................................... 64
2.6. Pertanyaan ................................................................. 65
BAB III Field Programmable Gate Array ............................ 67
3.1. Pendahuluan .............................................................. 67
3.2. Reconfigurable Device .............................................. 70
3.3. Blok I/O Dasar .......................................................... 76

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 3.4. Configurable Logic Block (CLB) .............................. 78
3.5. Blok Interkoneksi yang Dapat Diprogram ................ 81
3.6. Optimasi Perancangan untuk FPGA .......................... 82
3.7. Aliran Perancangan FPGA Xilinx ............................. 86
3.8. Referensi .................................................................... 87
3.9. Pertanyaan ................................................................. 88
BAB IV Model Masukan Rancangan ................................... 89
4.1. Pendahuluan .............................................................. 89
4.2. Metode Masukan Rancangan ..................................... 91
4.3. Referensi .................................................................. 100
4.4. Pertanyaan ............................................................... 100
BAB V Metodologi Top-Down vs Bottom-Up ................... 101
5.1. Pendahuluan ............................................................ 101
5.2. Metodologi Perancangan terhadap EDA ................. 105
5.3. Implementasi Metodologi Perancangan .................. 109
5.4. Referensi .................................................................. 115
5.5. Pertanyaan ............................................................... 116
BAB VI Metode Perancangan ............................................. 117
6.1. Pendahuluan ............................................................ 117
6.2. Perancangan IC ........................................................ 119
6.3. Metodologi Perancangan Pewaktuan ...................... 122
6.3.1. Floorplanning dan Placement ................... 122
6.3.2. Floorplan Tingkat Tinggi .......................... 123
6.3.3. Floorplanning Terperinci .......................... 124
6.3.4. Sintesis Kendali Pewaktuan ...................... 126
6.3.5. Model Penyambungan ............................... 128
6.3.6. Placement and Route ................................. 130
6.3.7. Synthesis Back-Annotation ........................ 134
6.3.8. Verifikasi Pewaktuan ................................ 135
6.4. Referensi .................................................................. 137
6.5. Pertanyaan ............................................................... 138

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BAB VII Verifikasi Rancangan ............................................ 139
7.1. Pendahuluan ............................................................ 139
7.2. Verifikasi Perancangan ........................................... 140
7.3. Pembuktian Implementasi ....................................... 143
7.4. Jenis Verifikasi Uji .................................................. 149
7.5. Metode Verifikasi Uji .............................................. 150
7.6. Konfigurasi Pengujian ............................................. 151
7.7. Struktur Testbench ................................................... 152
7.8. Prosedur Verifikasi Pengaturan ............................... 154
7.9. Referensi .................................................................. 156
7.10. Pertanyaan ............................................................... 156
BAB VIII VHDL ..................................................................... 157
8.1. Pendahuluan ............................................................ 157
8.2. VHDL ...................................................................... 159
8.3. Tahap Perancangan ................................................. 163
8.4. Struktur Kode VHDL .............................................. 165
8.5. Entity ....................................................................... 169
8.6. Architecture ............................................................. 170
8.7. Referensi .................................................................. 172
8.8. Pertanyaan ............................................................... 172
BAB IX Mode Penyambungan ........................................... 173
9.1. Pendahuluan ............................................................ 173
9.2. Signal ....................................................................... 174
9.3. Variable ................................................................... 177
9.4. Perbandingan Signal dan Variable .......................... 178
9.5. Generic .................................................................... 179
9.6. Constant ................................................................... 180
9.7. Referensi .................................................................. 180
9.8. Pertanyaan ............................................................... 181
BAB X Tipe Data, Obyek dan Konversi ........................... 183
10.1. Pendahuluan ............................................................ 183
10.2. Tipe Data yang Belum Terdefinisi .......................... 183
10.3. Tipe Data yang Dapat Didefinisikan Pengguna ...... 189
10.4. Subtype .................................................................... 190

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 10.5. Larik (Array) ............................................................ 191
10.6. Larik dalam Port ...................................................... 193
10.7. Record ...................................................................... 194
10.8. Konversi Data .......................................................... 194
10.9. Referensi .................................................................. 197
10.10. Pertanyaan ............................................................... 198
BAB XI Operator dan Atribut ............................................ 199
11.1. Operator ................................................................... 199
11.1.1. Operator Keluaran .................................... 199
11.1.2. Operator Logika ........................................ 200
11.1.3. Operator Aritmatika .................................. 201
11.1.4. Operator Pembanding ............................... 202
11.1.5. Operator Geser .......................................... 202
11.1.6. Operator Overloading ............................... 203
11.1.7. Penggunaan Operator ................................ 204
11.2. Atribut Data ............................................................. 204
11.2.1. Atribut Signal Enumerasi .......................... 205
11.2.2. Atribut Signal ............................................ 206
11.2.3. Atribut yang Didefinisikan Pengguna ....... 207
11.3. Referensi .................................................................. 208
11.4. Pertanyaan ............................................................... 208
BAB XII Konkuren dan Sekuensial ..................................... 209
12.1. Kode Konkuren ....................................................... 209
12.2. Logik Kombinasional Versus Sekuensial ................ 209
12.3. Kode konkuren Versus Sekuensial .......................... 210
12.4. Deklarasi When ........................................................ 211
12.5. Generate .................................................................. 213
12.6. Block ........................................................................ 214
12.6.1. Simple Block ............................................. 214
12.6.2. Guarded Block ........................................... 215
12.7. Kode Sekuensial ...................................................... 216
12.7.1. Process ...................................................... 217
12.7.2. If ................................................................. 217
12.7.3. Wait ........................................................... 218

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 12.7.4. Case ........................................................... 220
12.7.5. Case Versus if ........................................... 220
12.7.6. Case Versus When ..................................... 221
12.8. Referensi .................................................................. 221
12.9. Pertanyaan ............................................................... 222
BAB XIII ROM dan RAM ..................................................... 223
13.1. Pendahuluan ............................................................ 223
13.2. Read-Only Memory (ROM) .................................... 224
13.3. Perancangan ROM .................................................. 226
13.4. Random Access Memory (RAM) ............................. 231
13.5. Referensi .................................................................. 233
13.6. Pertanyaan ............................................................... 234
BAB XIV Finite State Machine .............................................. 235
14.1. Pendahuluan ............................................................ 235
14.2. Finite State Machine ............................................... 237
14.3. Prinsip Kerja Finite State Machine ......................... 238
14.4. Referensi .................................................................. 251
14.5. Pertanyaan ............................................................... 252
BAB XV Implementasi FPGA untuk Sorting ..................... 253
15.1. Pendahuluan ............................................................ 253
15.2. Rekonfigurasi Field Programmable Gate Array
(FPGA) .................................................................... 254
15.2.1. Arsitektur FPGA ....................................... 256
15.2.2. Proses Implementasi FPGA ...................... 257
15.2.3. Optimasi Logik ......................................... 257
15.2.4. Pemetaan Teknologi .................................. 257
15.2.5. Penempatan ............................................... 258
15.2.6. Piranti Lunak Penjalaran ........................... 258
15.2.7. Bagian Pemrograman ................................ 258
15.3. VHDL Bahasa Pendukung FPGA ........................... 259
15.4. Mergesort ................................................................ 261
15.5. Rancangan Global ................................................... 262
15.5.1. Rangkaian Shift-Register ........................... 264
15.5.2. Multiplekser .............................................. 264

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 15.5.3. Rangkaian Pembanding (Comparator) ..... 265
15.5.4. Rangkaian Keluaran .................................. 265
15.6. Mergesort Berbasis FPGA ...................................... 266
15.7. Referensi .................................................................. 268
BAB XVI Implementasi FPGA untuk Arithmetic Logic
Unit .......................................................................... 271
16.1. Pendahuluan ............................................................ 271
16.2. Arithmetic Logic Unit (ALU) .................................. 274
16.2.1. Unit Logik ................................................. 277
16.2.2. Unit Aritmetik ........................................... 278
16.3. Unit Shifter .............................................................. 279
16.4. Unit Multiplekser ..................................................... 281
16.5. Implementasi FPGA ................................................ 284
16.6. Referensi .................................................................. 286
16.7. Pertanyaan ............................................................... 288
BAB XVII Implementasi FPGA untuk Convolutional
Encoder ................................................................... 289
17.1. Pendahuluan ............................................................ 289
17.2. Convolutional Code ................................................. 292
17.3. Field Programmable Gate Array (FPGA) .............. 294
17.4. Implementasi Convolutional Encoder dalam
FPGA ....................................................................... 296
17.5. Referensi .................................................................. 302
17.6. Pertanyaan ............................................................... 304
BAB XVIII Interoperabilitas VHDL antara FPGA Xilinx
dan Altera ............................................................... 305
18.1. Pendahuluan ............................................................ 305
18.2. Selayang Pandang VHDL ........................................ 307
18.2.1. Xilinx ISE .................................................. 311
18.2.2. Altera Max+Plus II .................................... 313
18.3. Interoperabilitas Xilinx ISE dan
Max + Plus II 10.2 ................................................... 315
18.4. Referensi .................................................................. 321
18.5. Pertanyaan ............................................................... 322

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BAB XIX Antarmuka pada FPGA Xilinx Spartan-3E ....... 323
19.1. Pendahuluan ............................................................ 323
19.2. Analog Capture Circuit ........................................... 324
19.2.1. Programmable Pre-Amplifier ................... 329
19.2.2. Analog-to-Digital Converter (ADC) ......... 336
19.3. Pemrosesan Sinyal Digital ...................................... 342
19.4. Digital-to-Analog Converter (DAC) ....................... 347
19.5. Referensi .................................................................. 357
19.6. Pertanyaan ............................................................... 358
BAB XX Implementasi FPGA untuk Pengukuran
Daya Listrik ........................................................... 359
20.1. Pendahuluan ............................................................ 359
20.2. FPGA Spartan-3E Starter Kit .................................. 360
20.3. Teori Daya Listrik ................................................... 363
20.4. Metodologi .............................................................. 366
20.4.1. Spesifikasi ................................................. 366
20.4.2. Verifikasi ................................................... 366
20.4.3. Implementasi ............................................. 367
20.4.4. Debug dan Pengujian ................................ 367
20.4.5. Hasil .......................................................... 367
20.5. Referensi .................................................................. 372
20.6. Pertanyaan ............................................................... 373
DAFTAR PUSTAKA ................................................................. 375
LAMPIRAN ................................................................................ 383
GLOSARIUM ............................................................................. 385
INDEKS .................................................................................. 387

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