Definition + Most signals we want to process are analog + i.e.: they are continuous and can take an inifinity of values Definition + Digital systems require discrete digital data + ADC converts an analog information into a digital information be op El mpExamples of use + Voltmeter e wf = 7.779 e + Cell phone (microphone) = Conversion process 3 steps: + Sampling * Quantification * Coding These operations are all performed in a same element: the A to D ConverterConversion process: Sampling * Digital system works with discrete states + The signal is only defined at determined times * The sampling times are proportional to the sampling period (T.) Poteet Conversion process: Quantification The signal can only take determined values Belonging to a range of conversion (AV,) + Based on number of bit combinations that the converter can output Number of possible states: N=2" where n is number of bits Resolution: Q= AV,/N x 4 at xi) I | HH HEConversion process: Coding + Assigning a unique digital word to each sample + Matching the digital word to the input signal Ded Poteet Accuracy The accuracy of an ADC can be improved by increasing: + The sampling rate (T,) + The resolution (Q)Accuracy Poteet Higher Sampling rate Higher Resolution Aull Sampling rate Nyquist-Shannon theorem: Minimum sampling rate should be at least twice the highest data frequency of the analog signal f,.>2fmax Poteet:Sampling (option 1) * 200Hz signal sampled at 2000Hz 4000) Points are digital data, solid curve isthe truth. What és the frequency? Signal onkat oo TE a 200 Hz \ 1800 Hz a \ \ 2200 Hz 1000 ON — 0 7 0,000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0,008 Time (sec) Sampling (option 1) * 1000Hz signal sampled at 2000Hz 3000 /\ f\ \ 270} i ! \ VV V 0,000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0,008 Time (see) 1000Sampling (option 1) + 2200Hz sian aD ie came ithe uth, What the fequeney? \\f ANNA AM \h ANAM ANA \ \| AANA {\] \\ WI {Hi WEVA This is aliasing Points ae dig dat, 0.000 0.001 0.002 0.003 0.004 9.005 0.006 0.007 0.008 Time (2) Sampling (option 2) * 100Hz signal sampled at 1600Hz SampledData 259 FFT Magnitude Time (5)Sampling (option 2) QA signal with DC, 100Hz and 400Hz sampled at 1600Hz FET Magaituse Time (a) Frequency (k12) Sampling (option 2) Q11500Hz signal sampled at 1600Hz This is aliasing FET Mgaitude ime (a8) Frequency (th)Sampling rate Analog signals are composed of an infinity of harmonics Need to limit the frequency band to its useful part Use of an analog filter tp SE mp In practice: f, + (3...5)-friter Example * 8 bits converter: n=8 + Range of conversion: AVr=5V. + Sampling time: T,=1ms + Number of possible states: N=2®=256 + Resolution: Q=AVr/N=19.5 mV + Analog Filter: fie, = fs/5 = 200 Hz 255 Gain isi \ Analog DigitalADC Process Quantization & Coding > Use original analog signal > Apply 3 bit coding > Better representation of input information with additional bits Ke2 000 K-16 0000 Kew. >» MCS12 has max of 10 He bits ont, 100 uu 101, 0 1 ADC Process-Accuracy The accuracy of an ADC can be improved by increasing: t Sampling Rate, Ts Resolution (bit depth),Q ° ‘ » Based on number of steps > Improves accuracy in required in the conversion measuring amplitude of process analog signal > Increases the maximum frequency that can be measuredTypes of ADC > Successive Approximation A/D Converter > Flash A/D Converter > Dual Slope A/D Converter > Delta-Sigma A/D Converter Successive Approximation ADC Elements + DAC = Digital to Analog Converter + EOC = End of Conversion + SAR = Successive Approximation Register + S/H= Sample and Hold Circuit 1. coc + Via =Input Voltage * Comparator Veer = Reference Voltage veSuccessive Approximation ADC i Elements : o;—W DAC = Digital to Analog Converter ‘Ody ind of Conversion oy uceessive Approximation Register 5/H = Sample and Hold Circuit Vj. = Input Voltage comparitor JH Veer = Reference Voltage te Fs \i— 3 4 “k Vv 25 F 5‘, Successive Approximation ADC = Algorithm + Uses an n-bit DAC and original analog results * Performs a binary comparison of Voqc and Vin + MSB is initialized at 1 for DAC * If Vin < Vac (Vaer / 2°") then MSB is reset to 0 + If Vin > Voac (Vaee/ 2") Successive Bits set to 1 otherwise 0 + Algorithm is repeated up to LSB + Atend DAC in = ADC out + N-bit conversion requires N comparison cyclesSuccessive Approximation ADC - Example = S-bit ADC, Vig=0.6V, Vye=1V DAC bit/voltage "Cycle 1 => MSB=1 Br ee | |S sar =10000 Voltage |.5|.25 |.125 | 0625 |.03125 Vn>Voac SAR unchanged =10000 v Voac™ 5 +25 =.75 Vin Vone SAR unchanged = 100 Yo = Cycle 5 os SAR=10011 Voge = -5+.0625+.03125= ,59375 al > Vip>Voxc SAR unchanged = 10011 Flash ADC = Also known as parallel ADC = Elements * Encoder — Converts output of comparators to binary * Comparators ont} —a 2Flash ADC src vt * Algorithm 4 Vj, Value lies between two comparators Resolution AV = oe, ie N= Encoder Output bits Comparators => 2"-1 = Example: Vier 8V, Encoder 3-bit 8 + Resolution AV Lov + Comparators 2'-1=7 " 1 additional encoder bit -> 2 x # Comparators Flash ADC Example Vin = 5-5V, Veeg= 8V ‘tees voiuge Vip lies in between Veomps & Veomps Veomps = Vret*5/8 = 5V Veomps = Vier*6/8 = 6V sso roy rook Comparator 1-5 => output 1 Comparator 6 - 7 => output 0 3 it ADC Encoder Octal Input = sum(0011111) = 5 5.5V 34 og Encoder Binary Output = 101 opDual-Slope ADC — How It Works An unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period (t,) Then, a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (t,) The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period The run-down time measurement is usually made in units of the converter's clock, so longer integration times allow for higher resolutions The speed of the converter can be improved by sacrificing resolution Vout} V,=NS, tt time Delta-Sigma A/D Converter Analog pers ser igma Digital Input paren ftenre | st OutputDelta-Sigma ADC — How It Works > Input over sampled, goes to integrator > Integration compared with ground > Iteration drives integration of error to zero » Output is a stream of serial bits lO ee een 4 ae Clock @——__ Comparison of ADC’s ee Ry efsr-ts [eers9 Resolution Me (relative) (relative) (bits) Dual Slope Slow Med 12-16 Flash Very Fast High 4-12 Successive Medium — Low 8-16 Approx Fast Sigma — Delta Slow Low 12-24