12 - Algoritma Viterbi
12 - Algoritma Viterbi
ALGORITMA VITERBI
Beby H. A. Manafe
Prodi Teknik Elektro – FST Undana
bebymanafe@staf.undana.ac.id
DECODING KODE KONVOLUSI
ALGORITMA
VITERBI
TRELLIS
DIAGRAM
STATE
DIAGRAM
BLOCK
DIAGRAM
S6 0 1 1
S7 1 1 1
00
S1 S3
11 11 01 11 10
00 S0 00 S2 S5 01 S7 01
11 10 00 10 11
S4 S6
01
L m 1 n 1
'( j )
'
M r y M ri yi
i 0 j 0
( j)
a riil,positif ' '
Max p r y juga Max M r y
b riil
a riil,negatif ' '
Max p r y diperoleh dari Min M r y
b riil
t0 t1
k 1 n1
( j)
k 1
M rk yk M ri yi M ri yi
k ' ( j)
i 0 i 0 j 0
X Y
S1
Contoh: 111 111
' O W Z
S0
Y M2 r y 000,111,... 000 000
t0 t1 t2
'
W M r1 y1 111
M r0(0) 0 M r0(1) 0 M r0(2) 0 M r1(0) 1 M r1(1) 1 M r1(1) 1
X M rt ( 0 ) 0 M rt (1) 0 M rt ( 2 ) 1 ,
Z Min
Y M rt 1 M rt 1 M rt 1
(0) (1) (2)
S2 X
001
100 Z
S1
Y 111
S0 000
t t+1
S2 X
001
100 Z
S1
111
Y
S0 000
t t+1
S1
11 10
00 S0 01 00 S3 01
11 00
S2
S3 01 01 01 01
10 10 10 10 10
00 00 00 00
S2
01 01 01 01 01
00 00 00 00
S1
11 11 11 11 11 11
11 11 11 11
S0
00 00 00 00 00 00
t0 t1 t2 t3 t4 t5 t6
Pada t=2
0
S3
10
Pada t=1
0 2
S1 S2
path 01
11 metric
2 0 3
S0 S1
00
t0 t1
11 11
diterima … 11 2 3
S0
00 00
t0 t1 t2
11 10
Pada t=3
0 01 0 0 0
S3 01
5 SURVIVOR
10 10 10
2 00 1 2 00 1
S2
01 01 3 01
0 3 00 3 0 00 3
S1
4
11 11 11 11
2 3 11 11
S0 3 3
00 00 00
t0 t1 t2 t34 t0 t1 t2 t3
11 10 01 11 10 01
Pada t=4
0 01 0 01 1
S3
4
10 10
2 00 1 00 0
S2
01 01 4
00
0 3 00 1
S1
5
11 11 11
3 11 3
S0
00
t0 t1 t2 t3 t43
11 10 01 00
Survivor: S3
0 01 0 01 1
10
00
S2 00 1 0
00
S1 0 1
11
11
S0 3
t0 t1 t2 t3 t4
11 10 01 00