DAFTAR ISI

Halaman

LEMBAR PENGESAHAN....................................................................................i
KATA PENGANTAR............................................................................................ii
DAFTAR ISI.........................................................................................................iii
DAFTAR GAMBAR..............................................................................................x
DAFTAR TABEL................................................................................................xii
DAFTAR RUMUS............................................................................................xviii
DAFTAR SIMBOL.............................................................................................xix
DAFTAR SINGKATAN .....................................................................................xx
MODUL 1 GERBANG – GERBANG LOGIKA
1.1 Tujuan.......................................................................................I-1
1.2 Landasan Teori.........................................................................I-1
1.3 Komponen dan Peralatan.........................................................I-7
1.4 Langkah Kerja..........................................................................I-7
1.5 Hasil Pratikum........................................................................I-14
1.6 Analisa Hasil..........................................................................I-16
1.6.1 Analisa Hasil Percobaan IC 7408 (AND)....................I-16
1.7 Kesimpulan..............................................................................I-23
1.8 Saran........................................................................................I-23
Lembar Asistensi............................................................................I-24
MODUL II RANGKAIAN MULTILEVEL NAND & NOR
2.1 Tujuan.....................................................................................II-1
2.2 Landasan Teori........................................................................II-1
2.3 Komponen dan Peralatan........................................................II-3
2.4 Langkah Percobaan.................................................................II-3
2.4.1 Percobaan 1 ................................................................II-3
2.4.2 Percobaan 2..................................................................II-4
2.5 Hasil Pratikum .......................................................................II-7
2.5.1 Tabel Percobaan 1 .......................................................II-7
2.5.2 Tabel Percobaan 2 .......................................................II-8

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 2.5.3 Rangkaian Konversi NAND .....................................II-10
2.5.4 Rangkaian Konversi NOR.........................................II-10
2.6 Analisa Hasil.........................................................................II-11
2.6.1 Analisa Hasil Percobaan 1.........................................II-11
2.6.2 Analisa Hasil Percobaan 2.........................................II-13
2.6.3 Analisa Rangkaian Konversi NAND.........................II-15
2.6.4 Analisa Rangkaian Konversi NOR............................II-16
2.7 Kesimpulan...........................................................................II-17
2.8 Saran.....................................................................................II-17
Lembar Asistensi.............................................................................II-18
MODUL III RANGKAIAN ARITMATIKA
3.1 Tujuan....................................................................................III-1
3.2 Landasan Teori......................................................................III-1
3.2.1 Penjumlah (Adder)......................................................III-1
3.2.2 Half Adder..................................................................III-1
3.2.3 Full Adder...................................................................III-3
3.2.4 Pengurang (Substractor).............................................III-4
3.2.5 Half Substractor.........................................................III-4
3.2.6 Full Substractor..........................................................III-5
3.3 Komponen dan Peralatan.......................................................III-6
3.4 Gambar Rangkaian................................................................III-6
3.5 Langkah Percobaan ...............................................................III-9
3.5.1 Adder..........................................................................III-9
3.5.2 Substractor ..............................................................III-10
3.6 Hasil Pratikum ....................................................................III-12
3.7 Analisa Hasil........................................................................III-14
3.7.1 Analisa Hasil Pengukuran Pada Rangkaian Half
Adder.........................................................................III-14
3.7.2 Analisa Hasil Pengukuran Pada Rangkaian Full
Adder.........................................................................III-15
3.7.3 Analisa Hasil Rangkaian Half Substractor................III-16
3.7.4 Analisa Hasil Pengukuran Rangkaian Full

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 Substractor................................................................III-17
3.8 Kesimpulan.........................................................................III-18
3.9 Saran...................................................................................III-18
Lembar Asistensi.........................................................................III-19
MODUL IV ENCODER-DECODER
4.1 Tujuan.................................................................................IV-1
4.2 Landasan Teori......................................................................IV-1
4.3 Komponen dan Peralatan.....................................................IV-10
4.4 Langkah Percobaan.............................................................IV-10
4.4.1 Rangkaian Encoder 4 ke-2.......................................IV-10
4.4.2 Rangkaian Decoder 2 ke-4.......................................IV-11
4.5 Hasil Pratikum.....................................................................IV-13
4.6 Analisa Hasil........................................................................IV-14
4.6.1 Analisa Hasil Percobaan 1........................................IV-14
4.6.2 Analisa Hasil Percobaan 2........................................IV-15
4.6.3 Analisa Hasil Percobaan Rangkaian Decoder 2 Ke-4 Saat
A0=1.........................................................................IV-16
4.7 Kesimpulan..........................................................................IV-17
4.8 Saran....................................................................................IV-17
Lembar Asistensi.........................................................................IV-18
MODUL V MULTIPLEXER – DEMULTIPLEXER
5.1 Tujuan.....................................................................................V-1
5.2 Landasan Teori.......................................................................V-1
5.2.1 Multiplexer....................................................................V-1
5.2.2 Demultiplexer................................................................V-3
5.3 Komponen dan Peralatan........................................................V-4
5.4 Langkah Percobaan.................................................................V-4
5.4.1 Rangkaian Multiplexer 4 ke-1.....................................V-4
5.4.2 Rangkaian Demultiplexer 1 ke-4.................................V-6
5.4.3 Rangkaian Multiplexer / Demultiplexer......................V-7
5.5 Hasil Pratikum......................................................................V-10
5.6 Analisa Hasil..........................................................................V-12

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 5.6.1 Analisa Hasil Rangkaian Multiplexer 4 ke-1..............V-12
5.6.2 Analisa Hasil Rangkaian Demultiplexer 1 ke-4.........V-13
5.6.3 Analisa Hasil Rangkaian Multiplexer /
Demultiplexer.............................................................V-14
5.7 Kesimpulan...........................................................................V-15
5.8 Saran.....................................................................................V-15
Lembar Asistensi..........................................................................V-16
MODUL VI FLIP – FLOP
6.1 Tujuan....................................................................................VI-1
6.2 Landasan Teori......................................................................VI-1
6.2.1 R-S Flip – Flop..........................................................VI-1
6.2.2 D Flip – Flop..............................................................VI-4
6.2.3 J-K Flip – Flop...........................................................VI-4
6.3 Komponen dan Peralatan.......................................................VI-6
6.4 Langkah Percobaan...............................................................VI-6
6.4.1 RS Flip – Flop...........................................................VI-6
6.4.2 RST Flip – Flop.........................................................VI-7
6.4.3 D Flip – Flop..............................................................VI-7
6.4.4 J-K Flip – Flop.........................................................VI-10
6.5 Hasil Pratikum.....................................................................VI-11
6.6 Analisa Hasil........................................................................VI-13
6.6.1 Analisa Hasil RS Flip - Flop...................................VI-13
6.6.2 Analisa Hasil RST Flip - Flop................................VI-14
6.6.3 Analisa Hasil D Flip - Flop.....................................VI-15
6.6.4 Analisa Hasil J-K Flip – Fop...................................VI-16
6.7 Kesimpulan..........................................................................VI-17
6.8 Saran....................................................................................VI-17
Lembar Asistensi........................................................................VI-18
MODUL VII SHIFT REGISTER
7.1 Tujuan..................................................................................VII-1
7.2 Landasan Teori.....................................................................VII-1
7.2.1 Shift Register.............................................................VII-1

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 7.2.2 SISO (Serial Input Serial Output).............................VII-2
7.2.3 PIPO (Paralel Input Paralel Output)........................VII-3
7.2.4 PISO (Paralel Input Serial Output)..........................VII-4
7.2.5 SIPO (Serial Input Paralel Output)..........................VII-5
7.3 Komponen dan Peralatan.....................................................VII-5
7.4 Langkah Percobaan..............................................................VII-6
7.4.1 Shift Register 2-bit Dengan D Flip – Flop................VII-6
7.4.2 Shift Register 4-bit Dengan JK Flip – Flop..............VII-8
7.5 Hasil Pratikum....................................................................VII-10
7.5.1 Tabel Output Shift Register 2-bit D Flip – Flop....VII-10
7.5.2 Tabel Output Shift Register 4-bit JK Flip – Flop. . .VII-10
7.5.3 Tabel Output Shift Register 4-bit JK Flip – Flop....VII-11
7.6 Analisa Hasil......................................................................VII-12
7.6.1 Analisa Hasil Shift Register 2-bit D Flip – Flop
.................................................................................VII-12
7.6.2 Analisa Hasil Shift Register 4-bit JK Flip – Flop
.................................................................................VII-13
7.6.3 Analisa Hasil Shift Register 4-bit JK Flip – Flop
.................................................................................VII-14
7.7 Kesimpulan........................................................................VII-15
7.8 Saran...................................................................................VII-15
Lembar Asistensi........................................................................VII-16
MODUL VIII BINARY COUNTER
8.1 Tujuan.................................................................................VIII-1
8.2 Landasan Teori...................................................................VIII-1
8.2.1 Counter.......................................................VIII-1
8.2.2 Counter Sinkron......................................................VIII-1
8.2.3 Up dan Down Counter...........................VIII-2
8.2.4 Rangkaian Up / Down Counter...............................VIII-4
8.2.5 Counter Asinkron....................................................VIII-4
8.2.6 Counter Asinkron mod-N........................................VIII-6
8.3 Komponen dan Peralatan....................................................VIII-7

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 8.4 Langkah Percobaan.............................................................VIII-7
8.4.1 Binary Counter 2-bit dengan D Flip – Flop............VIII-7
8.4.2 Binary Counter 4-bit Dengan JK Flip – Flop..........VIII-9
8.4.3 Binary Up Counter Dengan Reduce Count...........VIII-12
8.4.4 Binary Down Counter Dengan Reduce Count.......VIII-14
8.5 Hasil Pratikum................................................................ VIII-16
8.5.1 Hasil Pratikum Rangkaian Binary Counter 2-bit
D Flip- Flop...........................................................VIII-16
8.5.2 Hasil Pratikum Rangkaian Binary Counter 4-bit
JK Flip – Flop.........................................................VIII-16
8.5.3 Hasil Pratikum Rangkaian Binary Up Counter
Reduce Count.........................................................VIII-18
8.5.4 Hasil Pratikum Rangkaian Binary Down Counter
Reduce Count.........................................................VIII-19
8.6 Analisa Hasil.....................................................................VIII-20
8.6.1 Analisa Hasil Rangkaian Binary Counter 2-bit
D Flip –Flop...........................................................VIII-20
8.6.2 Analisa Hasil Rangkaian Binary counter 4-bit
JK Flip – flop....VIII-21
8.6.3 Analisa Hasil Rangkaian Biinary Up Counter
Reduce Count..........................................................VIII-22
8.6.4 Analisa Hasil Rangkaian Binary Down Counter
Reduce Count..........................................................VIII-24
8.7 Kesimpulan.......................................................................VIII-30
8.8 Saran.................................................................................VIII-30
Lembar Asistensi......................................................................VIII-31
DAFTAR PUSTAKA
DAFTAR RIWAYAT HIDUP

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 DAFTAR GAMBAR

Gambar Halaman
1.1 Simbol Inverter.............................................................................................I-1
1.2 Simbol Gerbang AND 2 Input......................................................................I-2
1.3 Simbol Gerbang OR 2 Input.........................................................................I-3
1.4 Simbol Gerbang NAND 2 Input...................................................................I-3
1.5 Simbol Gerbang NOR 2 Input......................................................................I-4
1.6 Simbol Gerbang EX-OR 2 Input..................................................................I-5
1.7 Gerbang AND 2 Input dan Gerbang AND 3 Input.......................................I-9
1.8 Gerbang OR 2 Input dan Gerbang OR 3 Input...........................................I-10
2.1 Bentuk – Bentuk Rangkaian Ekivalen........................................................II-2
2.2 Gerbang NAND 2 Input..............................................................................II-3
2.3 Konversi Gerbang Logika menjadi NAND atau NOR...............................II-4
2.4 Rangkaian Konversi NAND saja................................................................II-9
2.5 Rangkaian Konversi NOR saja.................................................................II-10
3.1 Simbol Half Adder.....................................................................................III-2
3.2 Simbol Full Adder.....................................................................................III-3
3.3 Rangkaian Half Adder Dengan Implementasi Sum Of Product................III-6
3.4 Rangkaian Half Adder Dengan Implementasi product Of sum.................III-6
3.5 Rangkaian Full Adder................................................................................III-7
3.6 Rangkaian Full Adder dengan 2 buah Half Adder dan 1 buah Gerbang
OR.............................................................................................................III-7
3.7 Half Substractor.........................................................................................III-7
3.8 Full Substractor.........................................................................................III-8
4.1 Sirkit Digitally Encoder – Decoder...........................................................IV-2
4.2 Sirkit Keyboard..........................................................................................IV-3

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4.3 Sirkit Gating..............................................................................................IV-3
4.4 Sirkit Encoder............................................................................................IV-4
4.5 Sirkit One Shot Multivibrator....................................................................IV-5
4.6 Sirkit Data Latching...................................................................................IV-6
4.7 Sirkit Decoder............................................................................................IV-6
4.8 Sirkit memori.............................................................................................IV-7
4.9 Sirkit Clock................................................................................................IV-8
4.10 Sirkit Counter............................................................................................IV-8
4.11 Sirkit Display Decimal..............................................................................IV-9
4.12 Sirkit Display Biner...................................................................................IV-9
4.13 Rangkaian Encoder 4 ke-2......................................................................IV-10
4.14 Rangkaian Decoder 2 ke-4......................................................................IV-12
5.1 Blok Diagram Multiplexer..........................................................................V-1
5.2 Simbol Multiplexer 4 ke-1..........................................................................V-2
5.3 Rangkaian Multiplexer 4 ke-1 dengan Strobe/Enable................................V-2
5.4 Blok Diagram Logika Demultiplexer..........................................................V-3
5.5 Rangkaian Multiplexer 4 ke-1.....................................................................V-4
5.6 Rangkaian Demultiplexer 1 ke-4................................................................V-6
5.7 Rangkaian Multiplexer / Demultiplexer......................................................V-7
6.1 Rangkaian RS Flip – Flop dengan 2 buah Gerbang NOR........................VI-1
6.2 Rangkaian RS Flip – Flop dengan 2 buah Gerbang NAND.....................VI-2
6.3 Rangkaian dan Simbol R-S-T Flip – Flop.................................................VI-3
6.4 Rangkaian D Flip – Flop...........................................................................VI-4
6.5 Rangkaian JK Flip – Flop.........................................................................VI-4
6.6 Blok diagram D Flip – Flop......................................................................VI-8
6.7 D Flip – Flop.............................................................................................VI-8
7.1 Shift Register............................................................................................VII-1
7.2 SISO (Serial Input Serial Output)............................................................VII-3
7.3 PIPO (Paralel Input Paralel Output).......................................................VII-3
7.4 PISO (Paralel Input Serial Output).........................................................VII-4
7.5 SIPO (Serial Input Paralel Output).........................................................VII-5
7.6 Shift Register 2-bit dengan D Flip – Flop................................................VII-6

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7.7 Shift Register 4-bit dengan JK Flip – Flop..............................................VII-8
8.1 Contoh Up Counter Sinkron 3-bit.......................................................... VIII-2
8.2 Rangkaian Up Counter Sinkron 3-bit.....................................................VIII-3
8.3 Rangkaian Down Counter Sinkron 3-bit.................................................VIII-4
8.4 Rangkaian Up / Down Counter Sinkron 3-bit.........................................VIII-4
8.5 Timing Diagram Up Counter Asinkron 3-bit.........................................VIII-5
8.6 Up Counter Asinkron 3-bit.....................................................................VIII-6
8.7 Binary Counter 2-bit dengan D Flip – Flop...........................................VIII-7
8.8 Binary Counter 4-bit dengan JK Flip – Flop..........................................VIII-9
8.9 Binary Up Counter dengan Reduce Count............................................VIII-12
8.10 Binary Down Counter dengan Reduce Count.......................................VIII-14

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 DAFTAR TABEL

Tabel Halaman
1.1 Kebenaran Inverter........................................................................................I-2
1.2 Kebenaran Gerbang AND 2 Input................................................................I-2
1.3 Kebenaran Gerbang OR 2 Input...................................................................I-3
1.4 Kebenaran Gerbang NAND 2 Input.............................................................I-4
1.5 Kebenaran Gerbang NOR 2 Input................................................................I-4
1.6 Kebenaran Gerbang EX-OR 2 Input.............................................................I-5
1.7 Kebenaran Gerbang logika pada IC 7408.....................................................I-6
1.8 Kebenaran Gerbang logika pada IC 7432.....................................................I-7
1.9 Kebenaran Gerbang logika pada IC 7404.....................................................I-7
1.10 Kebenaran Gerbang logika pada IC 7400.....................................................I-8
1.11 Kebenaran Gerbang logika pada IC 7402.....................................................I-8
1.12 Kebenaran Gerbang logika pada IC 7486.....................................................I-9
1.13 Kebenaran Gerbang AND 2 Input dan 3 Input.............................................I-9
1.14 Kebenaran Gerbang OR 2 Input dan 3 Input..............................................I-10
1.15 Hasil Percobaan dengan IC 7408 (AND)...................................................I-12
1.16 Hasil Percobaan dengan IC 7432 (OR)......................................................I-12
1.17 Hasil Percobaan dengan IC 7404 (INVERTER)..........................................I-12
1.18 Hasil Percobaan dengan IC 7400 (NAND)................................................I-12
1.19 Hasil Percobaan dengan IC 7402 (NOR)....................................................I-13
1.20 Hasil Percobaan dengan IC 7486 (EX-OR)................................................I-13
1.21 Hasil Percobaan dengan IC 7411 AND 3 Input..........................................I-13
1.22 Hasil Percobaan dengan IC 7432 Gerbang OR 3 Input..............................I-14
1.23 Analisa Hasil Percobaan dengan IC 7408 (AND)......................................I-15
1.24 Analisa Hasil Percobaan dengan IC 7432 (OR).........................................I-16

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1.25 Analisa Hasil Percobaan dengan IC 7404 (INVERTER)............................I-17
1.26 Analisa Hasil Percobaan dengan IC 7400 ( NAND)..................................I-18
1.27 Analisa Hasil Percobaan dengan IC 7402 (NOR)......................................I-19
1.28 Analisa Hasil Percobaan dengan IC 7486 ( EX-OR).................................I-20
1.29 Analisa Hasil Percobaan dengan IC 7411 AND 3 Input............................I-21
1.30 Analisa Hasil Percobaan dengan IC 7432 Gerbang OR 3 Input................I-22
2.1 Output led L................................................................................................II-3
2.2 Output led ...................................................................................................II-5
2.3 Hasil Pratikum percobaan 1, 4 Gerbang NAND dengan 2 Input................II-7
2.4 Hasil Perhitungan Manual Percobaan 1, 4 Gerbang NAND 2
Input...................................................................................................II-7
2.5 Hasil Pratikum Percobaan 2, 2 Gerbang AND dan 1 Gerbang OR 4
Input............................................................................................................II-8
2.6 Perhitungan Manual Percobaan 2, 2 Gerbang AND, 1 Gerbang OR 4
Input............................................................................................................II-9
2.7 Hasil Analisa Pratikum Percobaan 1, 4 Gerbang NAND dengan 2
Input..........................................................................................................II-11
2.8 Hasil Analisa Perhitungan Manual Percobaan 1, 4 Gerbang NAND 2
Input..........................................................................................................II-11
2.9 Hasil analisa praktikum percobaan 2, 2 Gerbang AND dan 1 Gerbang
OR 4 Input.................................................................................................II-13
2.10 Hasil Analisa Perhitungan Manual Percobaan 2, 2 Gerbang AND, 1
Gerbang OR 4 Input..................................................................................II-14
3.1 Kebenaran Fungsi Half Adder...................................................................III-2
3.2 Kebenaran Fungsi Full Adder....................................................................III-3
3.3 Kebenaran Fungsi Half Substractor..........................................................III-4
3.4 Kebenaran Fungsi Full Substractor...........................................................III-5
3.5 Input dan Output Half Adder.....................................................................III-8
3.6 Input dan Output Fungsi Carry..................................................................III-9
3.7 Input dan Output Substractor....................................................................III-9
3.8 Input dan Output Fungsi Borrow.............................................................III-10
3.9 Hasil Pengukuran Pada Rangkaian Half Adder.......................................III-11

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3.10 Hasil Pengukuran Pada Rangkaian Full Adder........................................III-11
3.11 Hasil Pengukuran Pada Rangkaian Half Substractor..............................III-11
3.12 Hasil Pengukuran Pada Full Substractor.................................................III-12
3.13 Hasil Analisa Pengukuran Pada Rangkaian Half Adder..........................III-13
3.14 Kebenaran Rangkaian Half Adder...........................................................III-15
3.15 Hasil Analisa Pengukuran Pada Rangkaian Full Adder..........................III-17
3.16 Hasil Analisa Pengukuran Pada Rangkaian Half Substractor.................III-18
4.1 Kebenaran Encoder.................................................................................IV-11
4.2 Kebenaran Decoder.................................................................................IV-12
4.3 Hasil Rangkaian Encoder 4 ke-2.............................................................IV-14
4.4 Hasil Rangkaian Decoder 2 ke-4.............................................................IV-14
4.5 Hasil Rangkaian Decoder 2 ke-4 saat A0 = 1.........................................IV-14
4.6 Analisa Hasil Rangkaian Encoder 4 ke-2................................................IV-15
4.7 Analisa Hasil Rangkaian Decoder 2 ke-4................................................IV-16
4.8 Analisa Hasil Rangkaian Decoder 2 ke-4 saat A0 = 1............................IV-16
5.1 Rangkaian Multiplexer 4 ke-1.....................................................................V-5
5.2 Rangkaian Demultiplexer 1 ke-4................................................................V-7
5.3 Rangkaian Multiplexer / Demultiplexer......................................................V-8
5.4 Kebenaran Rangkaian Multiplexer 4 ke-1................................................V-10
5.5 Kebenaran Rangkaian Demultiplexer 1 ke-4............................................V-10
5.6 Kebenaran Rangkaian Multiplexer / Demultiplexer..................................V-11
5.7 Kebenaran Rangkaian Multiplexer / Demultiplexer..................................V-11
5.8 Kebenaran Analisa Hasil Rangkaian Multiplexer 4 ke-1..........................V-12
5.9 Kebenaran Analisa Hasil Rangkaian Demultiplexer 1 ke-4......................V-14
5.10 Kebenaran Analisa Hasil Rangkaian Multiplexer / Demultiplexer...........V-15
5.11 Kebenaran Analisa Hasil Rangkaian Multiplexer / Demultiplexer...........V-15
6.1 Kebenaran RS Flip – Flop dengan 2 Gerbang NOR.................................VI-2
6.2 Kebenaran RS Flip – Flop dengan 2 Gerbang NAND..............................VI-2
6.3 Kebenaran R-S-T Flip – Flop....................................................................VI-3
6.4 Kebenaran D Flip – Flop...........................................................................VI-4
6.5 Kebenaran JK Flip – Flop.........................................................................VI-5
6.6. Kebenaran RS Flip – Flop.........................................................................VI-6

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6.7 Kebenaran R-S-T Flip – Flop....................................................................VI-7
6.8 Kebenaran D Flip – Flop...........................................................................VI-7
6.9 Input dan Output D Flip – Flop.................................................................VI-9
6.10 Kebenaran JK Flip – Flop.......................................................................VI-10
6.11 Kebenaran RS Flip – Flop dengan 2 buah Gerbang NOR......................VI-11
6.12 Kebenaran RS Flip – Flop dengan 2 buah Gerbang NAND...................VI-11
6.13 Kebenaran R-S-T Flop – Flop.................................................................VI-12
6.14 Kebenaran D Flip – Flop.........................................................................VI-12
6.15 Kebenaran JK Flip – Flop.......................................................................VI-12
6.16 Kebenaran Analisa Hasil RS Flip –Flop dengan 2 buah Gerbang
NOR........................................................................................................VI-13
6.17 Kebenaran Analisa hasil RS Flip – Flop dengan 2 buah Gerbang
NAND......................................................................................................VI-13
6.18 Kebenaran Analisa Hasil R-S-T Flip – flop............................................VI-15
6.19 Kebenaran Analisa Hasil D Flip – Flop..................................................VI-16
6.20 Kebenaran Analisa Hasil JK Flip – Flop.................................................VI-20
7.1 Output State QA dan QB..........................................................................VII-7
7.2 Output State..............................................................................................VII-9
7.3 Output State..............................................................................................VII-9
7.4 Output State QA dan QB Shift Register 2-bit dengan D Flip – Flop.....VII-10
7.5 Output State QA,QB,QC, dan QD Shift Register 4-bit dengan JK
Flop - Flop.............................................................................................VII-10
7.6 Data Setting untuk Output State QA,QB,QC,dan QD Shift Register
4-bit JK Flip- Flop.................................................................................VII-11
7.7 Analisa Hasil Output State QA dan QB Shift Register 2-bit D Flip -
Flop........................................................................................................VII-12
7.8 Analisa Hasil Output State QA,QB,QC dan QD Shift Register 4-bit
JK Flip – Flop.......................................................................................VII-13
7.9 Analisa Hasil Data Setting untuk Output State QA,QB,QC dan QD
Shift Register 4-bit JK Flip – Flop.........................................................VII-14
8.1 Ps / Ns untuk Up dan Down Counter 3-bit.............................................VIII-3
8.2 Kebenaran Dari Up Counter Asinkron 3-bit...........................................VIII-5

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8.3 Clock Pulse QB dan QA.........................................................................VIII-8
8.4 Clock Pulse QB dan QA.........................................................................VIII-8
8.5 Clock Pulse QB,QA,QC, dan QD.........................................................VIII-10
8.6 Clock Pulse QD,QC,QB dan QA..........................................................VIII-11
8.7 Kebenaran Binary Up Counter dengan Reduce Count.........................VIII-13
8.8 Kebenaran Binary Down Counter dengan Reduce Count.....................VIII-15
8.9 Dua-bit Output State QA dan QB.........................................................VIII-16
8.10 Dua-bit Output State QA dan QB.........................................................VIII-16
8.11 Empat-bit Output State QB,QA,QC dan QD........................................VIII-17
8.12 Empat-bit Output State QD,QC,QB dan QA........................................VIII-18
8.13 Output State Rangkaian Binary Up Counter........................................VIII-19
8.14 Output State Rangkaian Binary Down Counter....................................VIII-20
8.15 Analisa Hasil dua-bit Output State QB dan QA...................................VIII-21
8.16 Analisa Hasil dua-bit Output State QB dan QA...................................VIII-22
8.17 Analisa Hasil empat-bit Output State QB,QA,QC dan QD..................VIII-24
8.18 Analisa Hasil Output State empat-bit QD,QC,QB, dan QA.................VIII-26
8.19 Analisa Hasil Output Rangkaian Binary Up Counter...........................VIII-28

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 DAFTAR RUMUS

1.1 Gerbang EX-OR 2 Input

2.1 Gerbang logika NAND 4 dengan 2 Input
2.2 Gerbang logika NOR 7 dari Input NOR 5 dan NOR 6
2.3 Gerbang logika NOR 8 Input dari Output NOR 7
3.1 Fungsi Half Adder
3.2 Fungsi Boolean untuk s dan Co
3.3 Fungsi Full Adder
3.4 Fungsi Half Substractor
3.5 Fungsi Full Substractor
3.6 Fungsi Aljabarnya Boolean
3.7 Fungsi s pada gerbang EX-OR
3.8 Pada Output nilai s
3.9 Rangkaian Full Adder
3.10 Fungsi Boolean pada Full Adder dan Half Adder
3.11 Rangkaian Half Substractor
3.12 Rangkaian Full Substractor
5.1 Rangkaian Multiplexer 4 ke-1
5.2 Rangkaian Demultiplexer 1 ke-4

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 DAFTAR SIMBOL

 : Penjumlahan x y + x y / fungsi EX-OR

X : Komplemen / lawan
A : Input
B : Input
C : Input
Co : Output
D : Input
J : Input JK Flip – Flop
K : Input JK Flip - Flop
L : Output
Q : Output
R : Input
S : Output / Input
T : Clock / Trigger
Y : Output

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 DAFTAR SINGKATAN

CLK : Clock
CLR : Clear
Demux : Demultiplexer
FA : Full Adder
FS : Full Substractor
HA : Half Adder
HS : Half Substractor
IC : Integrated Circuit
JK : Jump Kill
LSB : Least Significant Bit
ME : Memory Enable
Mux : Multiplexer
PIPO : Paralel Input Paralel Output
PISO : Paralel Input Serial Output
PRE : Preset
Rank. : Rangkaian.
RS : Reset Set
RST : Reset Set Trigger
SIPO : Serial Input Paralel Output
SISO : Serial Input Serial Output
SLR : Shift Left Register
SRR : Shift Right Register

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