SISTEM KOMPUTER APLIKASI KHUSUS

Perhatikan Modul Komputasi sederhana dan diagram komputasinya, seperti ditunjukkan pada
diagram di bawah ini.
-------------------- Model Komputasi Khusus

-----------------------

Y=(AB+CD)*(A+C)
A

t1

X
AB

t2

CD

+
AB+CD

A+C

t3

Y=(AB+CD)*(A+C)
A

t1

t2

AB

X
CD

t3

A+C

+
AB+CD

t4

--------------------------- end of model komputasi -----------------------------

------------------------------------------------------------------------------------------------------------------------------------------------Kuliah: Sistem Komputer Tersemat (514D4102), Dept. Teknik Elektro, Univ. Hasanuddin
Dosen: Dr.-Ing. Faizal Arya Samman

01

10

00

01

A
B
C
D
E
F
G
H
Y

00

00

01

10

00

01

10

00

01

00

01

-------- KODE VHDL--------------------------library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity asip1 is
port( REG_out : out std_logic_vector(23 downto 0);
REG_0
: out std_logic_vector(15 downto 0);
REG_1
: out std_logic_vector(15 downto 0);
REG_2
: out std_logic_vector(7 downto 0);
REG_3
: out std_logic_vector(15 downto 0);
clk
: in std_logic);
end asip1;
architecture perilaku of asip1 is
signal REG_A
: std_logic_vector(7 downto 0) :=
signal REG_B
: std_logic_vector(7 downto 0) :=
signal REG_C
: std_logic_vector(7 downto 0) :=
signal REG_D
: std_logic_vector(7 downto 0) :=
signal REG_E
: std_logic_vector(15 downto 0);
signal REG_F
: std_logic_vector(15 downto 0);
signal REG_G
: std_logic_vector(7 downto 0);
signal REG_H
: std_logic_vector(15 downto 0);

"00000011";
"00000010";
"00000100";
"00000101";

type comp_state is (hitung1, hitung2, hitung3, hitung4);

signal current_comp: comp_state := hitung1;

------------------------------------------------------------------------------------------------------------------------------------------------Kuliah: Sistem Komputer Tersemat (514D4102), Dept. Teknik Elektro, Univ. Hasanuddin
Dosen: Dr.-Ing. Faizal Arya Samman

begin
process(clk)
begin
if rising_edge(clk) then
case(current_comp) is
when hitung1 =>
current_comp <= hitung2;
REG_E <= REG_A * REG_B;
REG_G <= REG_A + REG_C;
when hitung2 =>
current_comp <= hitung3;
REG_F <= REG_C * REG_D;
when hitung3 =>
current_comp <= hitung4;
REG_H <= REG_E + REG_F;
when hitung4 =>
current_comp <= hitung1;
REG_out <= REG_H * REG_G;
when others => null;
end case;
end if;
REG_0 <= REG_E;
REG_1 <= REG_F;
REG_2 <= REG_G;
REG_3 <= REG_H;
end process;
end;
--------------------- end of file -----------------------

------------------------------------------------------------------------------------------------------------------------------------------------Kuliah: Sistem Komputer Tersemat (514D4102), Dept. Teknik Elektro, Univ. Hasanuddin
Dosen: Dr.-Ing. Faizal Arya Samman