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LAPORAN RESMI

PRAKTIKUM VLSI & PERANCANGAN LOGIKA

Disusun Oleh:

YOGA MAHENDRA FIRNANDA

1110171009

3 D4 ELEKTRONIKA A

PROGRAM STUDI D4 TEKNIK ELEKTRONIKA

DEPARTEMEN
1 ELEKTRO

POLITEKNIK ELEKTRONIKA NEGERI SURABAYA

TAHUN AJARAN 2019-2020

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Piranti Terprogram Perancangan TestBench dan

Simulasi

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Perancangan FPGA dengan simulasi (Test Bench)

1. Tujuan
 Membuat simulasi Test Bench VHDL
 Implementasi rancangan pada FPGA devais
 Mampu merancang dan mendemonstrasikan testbench untuk menguji dan
mensimulasikan rangkaian yang dibuat. serta melaporkan hasil
percobaannya

2. Peralatan yang dibutuhkan

 Komputer yang sudah terinstall software XILINX ISE Design Suite 14.7
dan Adept Digilent

 BASYS 2 FPGA board

3. Langkah percobaan

1. Buka software ISE Design Suite 14.7

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2. Klik pada tombol “New Project” untuk membuat project baru.

3. Beri nama project dan letakkan project pada folder yang ditentukan serta Top-level
source type adalah HDL

4. Setting jenis FPGA dan konfigurasi lainnya sesuai gambar dibawah, dimana

Family: Spartan-3E

Device: XC3S100E atau XC3S250E, tergantung jenis chip board anda

Package: CP132

Speed: -4
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Preferred Language: VHDL

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5. Klik Next dan anda akan mendapat konfirmasi konfigurasi yang telah dilakukan.
Selanjutnya klik Finish

6. Selanjutnya buat file VHDL dengan cara klik kanan pada nama project, selanjutnya
pilih New Source

7. Pilih jenis source VHDL Module dan berilah nama, misalnya Counter

8. Selanjutnya langsung klik Next kemudian Finish, karena kita akan membuat port
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secara manual dengan text.

9. Maka anda akan mendapatkan file baru (*.vhd), tetapi tanpa deskripsi port yang akan
digunakan.

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10. Untuk percobaan ini kita akan mensimulasikan Counter 4-bit.

Counter Test Bench

Counter

11. Edit VHDL code menjadi generic couer seperti berikut:

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12. Lakukan pengecekan penulisan,dengan cara RUN Check Syntax sebagaimana

gambar berikut kemudian Synthesize

Lanjutkan ke langkah 13, jika tidak ada error.

13. Pindahkan VIEW: dari Implementation ke Simulation (Posisi di Pojok Kanan

Atas)

14. Selanjutnya buat file Test Bench VHDL dengan cara klik kanan pada nama project,
selanjutnya pilih New Source, dan pilih jenis source VHDL Test Bench

Maka Secara otomatis anda akan medapatkan file untuk simulas.

15. Edit bagian Stimulus Process pada kode VHDL sebagai berikut:
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
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reset <= '0';

wait for clock_period*10;

-- insert stimulus here

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count_en <= '1';

wait;
end process;

16. Run Simulate Behavioral model

17. Anda akan mendapatkan hasil simulasinya.

18. Edit file test bench sebagai berikut.

-----------------------------------------------------------------------

-- Test Bench for counter (ESD figure 2.6)

-- created by Weijun Zhang, 04/2001

-- edite by Arif

-----------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all; use

ieee.std_logic_unsigned.all; use
ieee.std_logic_arith.all;

entity counter_TB is -- entity declaration

end counter_TB;

-----------------------------------------------------------------------

architecture TB of counter_TB is

component counter

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generic(n: natural :=4);
port( clock: in std_logic;

reset: in std_logic;
count_en: in std_logic;

count_out: out std_logic_vector(n-1 downto 0)

);

end component;

signal T_clock: std_logic;

signal T_clear: std_logic;

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signal T_count: std_logic;

signal T_Q: std_logic_vector(3 downto 0);

begin

U_counter: counter port map (clock => T_clock,

reset => T_clear,

count_en => T_count,
count_out => T_Q);

process
begin

T_clock <= '0'; -- clock cycle is 10 ns

wait for 5 ns;

T_clock <= '1';

wait for 5 ns;

end process;

process

variable err_cnt: integer :=0;

begin

T_clear <= '1'; -- start counting

T_count <= '1';

wait for 20 ns;

T_clear <= '0'; -- clear output

-- test case 1
wait for 10 ns;

assert (T_Q=1) report "Failed case 1" severity error;

if (T_Q/=1) then

err_cnt := err_cnt+1;
end if;

-- test case 2
wait for 10 ns;

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assert (T_Q=2) report "Failed case 2" severity error;
if (T_Q/=2) then

err_cnt := err_cnt+1;
end if;

-- test case 3
wait for 10 ns;

assert (T_Q=3) report "Failed case 3" severity error;

if (T_Q/=3) then

err_cnt := err_cnt+1;
end if;

-- test case 4

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wait for 10 ns;

assert (T_Q=4) report "Failed case 4" severity error;

if (T_Q/=4) then

err_cnt := err_cnt+1;
end if;

-- test case 5
wait for 200 ns;
T_clear <= '1';

wait for 10 ns;

assert (T_Q=0) report "Failed case 5" severity error;

if (T_Q/=0) then

err_cnt := err_cnt+1;
end if;

-- summary of all the tests

if (err_cnt=0) then

assert false
report "Testbench of Counter completed successfully!"
severity note;

else
assert true

report "Something wrong, try again"

severity error;

end if;

wait;

end process;

end TB;

----------------------------------------------------------------
configuration CFG_TB of counter_TB is
for TB

end for;
end CFG_TB;

----------------------------------------------------------------

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19. Tugas: Lakukan cara yang sama untuk percobaan counter dan decoder seven segemen
pada percobaan sebelumnya.

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Praktikum VLSI & Perancangan Logika

Selasa, 5 Nopember 2019

Lab. Embedded System

H-102

Nama Anggota Kelompok : Akhmad Tony Adam (1110171008)

Yoga Mahendra Firnanda (1110171009)

Irkham Romadhon (1110171014)

PERCOBAAN 6

Piranti Terprogram Perancangan Test Bench dan Simulasi

1. Perancangan Test Bench dan Simulasi (Prosedur)

#VHDL Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

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entity coba is

generic(n:natural:=4);

port(clock:in std_logic;

reset:in std_logic;

count_en:in std_logic;

count_out:out std_logic_vector(n-1 downto 0)

);

end coba;

architecture behv of coba is

signal sign_counter:std_logic_vector(n-1 downto 0);

begin

process(clock, count_en, reset)

begin

if reset = '1' then

sign_counter <= (others=>'0');

elsif (clock= '1' and clock'event)then

if count_en = '1' then

sign_counter <= sign_counter +1;

end if;

end if;

end process;

count_out <= sign_counter;

end behv;

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#VHDL Simulasi

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

USE ieee.std_logic_arith.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY simulasi1 IS

END simulasi1;

ARCHITECTURE behv OF simulasi1 IS

COMPONENT coba

generic (n: natural :=4);

PORT(

clock : IN std_logic;

reset : IN std_logic;

count_en : IN std_logic;

count_out : OUT std_logic_vector(n-1 downto 0)

);

END COMPONENT;

signal T_clock : std_logic;

signal T_clear : std_logic;

signal T_count : std_logic;

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signal T_Q : std_logic_vector(3 downto 0);

BEGIN

uut: coba PORT MAP (clock => T_clock,

reset => T_clear,

count_en => T_count,

count_out => T_Q);

process

begin

T_clock <= '0'; -- clock cycle is 10 ns

wait for 5 ns;

T_clock <= '1';

wait for 5 ns;

end process;

process

variable err_cnt: integer :=0;

begin

T_clear <= '1'; -- start counting

T_count <= '1';

wait for 20 ns;

T_clear <= '0'; -- clear output

-- case 1

wait for 10 ns;

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assert (T_Q=1) report "failed case 1" severity error;

if(T_Q/=1) then

err_cnt :=err_cnt+1;

end if;

-- case 2

wait for 10 ns;

assert (T_Q=2) report "failed case 2" severity error;

if(T_Q/=2) then

err_cnt :=err_cnt+1;

end if;

-- case 3

wait for 10 ns;

assert (T_Q=3) report "failed case 3" severity error;

if(T_Q/=3) then

err_cnt :=err_cnt+1;

end if;

-- case 4

wait for 10 ns;

assert (T_Q=4) report "failed case 4" severity error;

if(T_Q/=4) then

err_cnt :=err_cnt+1;

end if;

case 5

wait for 200 ns;

T_clear <= '1';

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wait for 10 ns;

assert (T_Q=0) report "failed case 5" severity error;

if(T_Q/=0) then

err_cnt :=err_cnt+1;

end if;

--kumpulan test

if(err_cnt=0)then

assert false

report "testbench of counter completed succesfully!"

severity error;

else

assert true

report "something wrong, try again"

severity error;

end if;

end process;

END;

Hasil Running

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2. Perancangan Test Bench dan Simulasi (Tugas)

#VHDL Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder is

Port ( mclk : in STD_LOGIC;

Switch : in STD_LOGIC_VECTOR (2 downto 0); -- 3-bit input

Seven_Segment : out STD_LOGIC_VECTOR (0 to 6);

Led : out STD_LOGIC_VECTOR (7 downto 0) -- 8-bit output

); -- enable input

end Decoder;
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architecture Behavioral of Decoder is

signal sign_Count_Out : STD_LOGIC_VECTOR(3 downto 0);

signal CE,reset,init : STD_LOGIC;

signal cntDiv: std_logic_vector(23 downto 0); -- general clock div/cnt

begin

-- clock divider, untuk menurunkan frkuensi dari clock input (eksternal)

ckDivider: process(mclk)

begin

if mclk'event and mclk='1' then

cntDiv <= cntDiv + '1';

if cntDiv = X"F00000" then

CE <= '1';

cntDiv <= X"000000";

else

CE <= '0';

end if;

end if;

end process;

-- Seven Segment Decoder

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process (Switch)

begin

case Switch is

when "000" => Led <= "00000001"; ---0

when "001" => Led <= "00000010"; ---1

when "010" => Led <= "00000100"; ---2

when "011" => Led <= "00001000"; ---3

when "100" => Led <= "00010000"; ---4

when "101" => Led <= "00100000"; ---5

when "110" => Led <= "01000000"; ---6

when "111" => Led <= "10000000"; ---7

when others => Led <= "11111111"; ---null

end case;

end process;

end Behavioral;

#VHDL Simulasi

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;
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ENTITY testbench IS

END testbench;

ARCHITECTURE behavior OF testbench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Decoder

PORT(

mclk : IN std_logic;

Switch : IN std_logic_vector(2 downto 0);

Seven_Segment : OUT std_logic_vector(0 to 6);

Led : OUT std_logic_vector(7 downto 0)

);

END COMPONENT;

--Inputs

signal mclk : std_logic := '0';

signal Switch : std_logic_vector(2 downto 0) := (others => '0');

--Outputs

signal Seven_Segment : std_logic_vector(0 to 6);

signal Led : std_logic_vector(7 downto 0);

-- Clock period definitions

constant mclk_period : time := 10 ns;

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BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Decoder PORT MAP (

mclk => mclk,

Switch => Switch,

Seven_Segment => Seven_Segment,

Led => Led

);

-- Clock process definitions

mclk_process :process

begin

mclk <= '0';

wait for mclk_period/2;

mclk <= '1';

wait for mclk_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

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Switch <= "001";

wait for 100 ns;

Switch <= "010";

wait for 100 ns;

Switch <= "011";

wait for 100 ns;

Switch <= "100";

wait for 100 ns;

Switch <= "101";

wait for 100 ns;

Switch <= "110";

wait for 100 ns;

Switch <= "111";

wait for mclk_period*10;

-- insert stimulus here

wait;

end process;

END;

Hasil Running

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ANALISA

Setelah melakukan percobaan ini, dapat di analisa bahwa:

 Saat perancangan testbench dan simulasi (prosedur), didapatkan hasilnya dengan clock cycle
(t_clock) sebesar 10ns dan dibatasi setiap skala 50ns. Kemudian untuk memulai counting nya jika
t_count < “1”, lalu reset (t_clear) akan ON ketika value nya diberi input < “1”, dan akan OFF ketika
value nya < “0”. Waktu perpindahan jika melakukan reset yaitu 20ns.

 Saat perancangan testbench dan simulasi (tugas), didapatkan hasilnya dengan master clock (mclk)
sebesar 10ns dan dibatasi setiap skala 100ns. Parameter input di dalam percobaan ini yaitu master
clock (mclk) dan switch (2 downto 0). Dan parameter output nya dari nyala seven segment (0 to 6)
dan led (7 downto 0).

KESIMPULAN

Setelah melakukan percobaan 6 tentang “Perancangan Testbench dan Simulasi” ini, dapat ditarik
kesimpulan bahwa:

Proses simulasi berfungsi untuk mengetahui sekaligus mengecek apakah rancangan rangkaian
yang telah dibuat mampu berjalan dengan baik atau tidak. Selain itu, lewat proses simulasi dapat
diketahui bagaimana output dari rancangan rangkaian tadi. Selanjutnya, proses simulasi membutuhkan
suatu bentuk stimulus/pemicu. Stimulus ini akan bertindak sebagai input awal bagi rancangan
rangkaian yang hendak diuji. Kemudian, setelah diberikan stimulus maka rancangan rangkaian tersebut
dapat diketahui bagaimana hasil outputnya. Keseluruhan proses simulasi ini dilakukan dengan bantuan
perangkat lunak (software) yang ada.

Pada umumnya, proses simulasi terbagi atas 2 bentuk yakni:

 Bentuk testbench,

 Bentuk timing diagram.

Test bench sederhana akan Instantiate Unit di bawah Test (UUT) dan drive input. Testbench biasanya
ditulis dengan kode bahasa VHDL maupun Verilog. Bentuk testbench ini terbilang lebih sukar
dibandingkan dengan bentuk timing diagram. Hal ini disebabkan karena untuk melakukan testbench,
diperlukan kemampuan untuk menulis dan mengerti kode-kode VHDL maupun Verilog.

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