PERCOBAAN 5

Komunikasi I/O board Spartan 3E Starter Kit

Memanfaatkan 7 Segment
5.1 Tujuan
Peserta praktikum dapat memahami komunikasi I/O pada board spartan
3E dengan memanfaatkan modul peripheral 7 segment.
5.2 Dasar Teori
5.2.1 Seven Segment
Seven segmen adalah salah satu perangkat layar untuk menampilkan
sistem angkadesimal yang merupakan alternatif dari layar dot-matrix.
Layar tujuh segmen ini seringkali digunakan pada jam digital, meteran
elektronik, dan perangkat elektronik lainnya yang menampilkan informasi
numerik. Seven segment sendiri memiliki dua jenis yang berbeda yaitu
commoncatoda dan common anoda.

127

Gambar 5.1 Seven Segment

Dapat dilihat pada gaambar diatas terdapat dua jenis 7 segment yang
berbeda untuk common catoda 7 segment di hubungkan pada ground
sedangkan common anoda dihubungan pada Vcc ( source voltage ). Layar
7 segmen ini terdiri dari 7 buah LED yang membentuk angka 8 dan 1 LED
untuk titik. Angka yang ditampilkan di seven segmen ini dari 0-9. Cara
kerja dari seven segmen disesuaikan dengan LED. LED merupakan
komponen diode yang dapat memancarkan cahaya.kondisi dalam keadaan
ON jika sisi anode mendapatkan sumber positif dari Vcc dan katode
mendapatkan sumber negatif dari ground.
Berdasarkan cara kerjanya, tujuh segmen dibagi menjadi 2 bagian:

Common Katode
Cara kerja dari seven segmen common katode akan aktif pada kondisi
high "1" dan akan off pada kondisi low "0".
Tabel 5.1 Seven Segmen Common Katode
Angka h

0
1
2
3
4
5
6
7
8
9

0
0
1
1
1
1
1
0
1
1

1
0
0
0
1
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
1
1
0
1
1
0
1
1

1
1
0
1
1
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
0
1
1
0
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0

128

129

Tabel 5.2 Pengaktifan Common Catode

C

Anod
Cara
seven
common
akan aktif
kondisi
dan akan
kondisi

ommon

Tabel pengaktifan common katode

Angka
0
1
2
3
4
5
6
7
8
9

h
1
1
1
1
1
1
1
1
1
1

G
1
1
0
0
0
0
0
1
0
0

f
0
1
1
1
0
0
0
1
0
0

e
0
1
0
1
1
1
0
1
0
1

d
0
1
0
0
1
0
0
1
0
0

c
0
0
1
0
0
0
0
0
0
0

b
0
0
0
0
0
1
1
0
0
0

a
0
1
0
0
1
0
0
0
0
0

e
kerja dari
segmen
anode
pada
low

"0"

off

pada

high "1".

5.2.2 IC Decoder BCD

IC Dekoder BCD biasanya digunakan untuk driver rangkaian 7
segment untuk mengubah kode bilangan biner BCD (Binary Coded
Decimal) menjadi data tampilan untuk penampil/display 7 segment.
Decoder BCD ke 7 segment jenis TTL ada beberapa macam diantaranya
keluarga IC TTL 7447 dan keluarga IC TTL 7448. Kedua IC TTL:
tersebut memiliki fungsi yang sama namun peruntukannya berbeda IC
7447 digunakan untuk driver 7 segment common anoda sedangkan IC
7448 digunakan untuk driver dispaly 7 segment common cathode. IC
dekoder BCD ke 7 segment sering juga dikenal sebagai driver display 7
segment karena selalu digunakan untuk memberikan driver sumber
tegangan ke penampil 7 segment.

130

Gambar 5.2 IC Decoder BCD

Dalam aplikasi decoder, ketiga jalur kontorl (LT, RBI dan RBO)
harus diberikan logika HIGH dengan tujuan data input BCD dapat
masuk dan penampil 7 segmen dapat menerima data tampilan sesuai data
BCD yang diberikan pada jalur input.

Gambar 5.3 Tabel Kebenaran

131

Gambar 5.4 Rangkaian IC Decoder BCD

5.3 Alat dan Bahan
1. Board Spartan 3E Starter Kit
2. Source Voltage 5 v
3. Modul 7 segment
4. Jumper

5.4 Langkah percobaan

1. Membuat file .vhd pada xilinx
2. Membuat file .ucf pada xilinx
3. Melakukan compile Synthesize XST, Implement Design, Generate
Programming
4. Masuk pada Manage Configuration Project ( iMPACT )
5. Melakukan proses komunikasi antara board Spartan 3E dengan
komputer
6. Menghubungkan modul 7 segment dengan board Spartan 3E

132

7. List Program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity coba is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0);
segment7 : out std_logic_vector(6 downto 0) );
end coba ;
architecture Behavioral of coba is
begin
process (clk,bcd)
BEGIN
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; -- 'A'
when "1011"=> segment7 <="0000011"; -- 'b'
when "1100"=> segment7 <="0110001"; -- 'c'
when "1101"=> segment7 <="0100001"; -- 'd'
when "1110"=> segment7 <="0000110"; -- 'E'
when others=> segment7 <="0001110"; -- 'F'
end case;
end if;
end process;
end Behavioral;
8. File ucf
NET "bcd[0]" LOC = L13;
NET "bcd[1]" LOC = L14;
NET "bcd[2]" LOC = H18;
NET "bcd[3]" LOC = N17;
NET "clk" LOC = C9;
133

NET "segment7[0]" LOC = B4;

NET "segment7[1]" LOC = A4;
NET "segment7[2]" LOC = D5;
NET "segment7[3]" LOC = C5;
NET "segment7[4]" LOC = A6;
NET "segment7[5]" LOC = B6;
NET "segment7[6]" LOC = E7;
NET "bcd[0]" IOSTANDARD = LVTTL;
NET "bcd[1]" IOSTANDARD = LVTTL;
NET "bcd[2]" IOSTANDARD = LVTTL;
NET "bcd[3]" IOSTANDARD = LVTTL;
NET "clk" IOSTANDARD = LVCMOS33;
NET "segment7[0]" IOSTANDARD = LVTTL;
NET "segment7[1]" IOSTANDARD = LVTTL;
NET "segment7[2]" IOSTANDARD = LVTTL;
NET "segment7[3]" IOSTANDARD = LVTTL;
NET "segment7[4]" IOSTANDARD = LVTTL;
NET "segment7[5]" IOSTANDARD = LVTTL;
NET "segment7[6]" IOSTANDARD = LVTTL;
NET "bcd[0]" DRIVE = 8;
NET "bcd[1]" DRIVE = 8;
NET "bcd[2]" DRIVE = 8;
NET "bcd[3]" DRIVE = 8;
NET "clk" DRIVE = 4;
NET "segment7[0]" DRIVE = 6;
NET "segment7[1]" DRIVE = 6;
NET "segment7[2]" DRIVE = 6;
NET "segment7[3]" DRIVE = 6;
NET "segment7[4]" DRIVE = 6;
NET "segment7[5]" DRIVE = 6;
NET "segment7[6]" DRIVE = 6;
NET "bcd[0]" PULLUP;
NET "bcd[1]" PULLUP;
NET "bcd[2]" PULLUP;
NET "bcd[3]" PULLUP;
9 Wiring Modul

134

Gambar 5.5 Wiring pada Xilink

5.5 Tugas
5.4.1

Counter-Up Ganjil

5.4.1.1 Tabel Kebenaran

Tabel 5.4 Tabel Kebenaran Counter-Up ganjil
INPUT
Clock
Reset

D
0
0
0
0
0
1

C
0
0
0
1
1
0

OUTPUT
B
A
0
0
0
1
1
1
0
1
1
1
0
1

Angka
0
1
3
5
7
9

135

0
0
0

1
1
1

0
1
1

1
0
1

1
1
1

B
D
F

5.4.1.2 RANGKAIAN

Gambar 5.6 Rangkaian Counter-Up ganjil

5.4.1.3 Listing Program
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity counter_up_ganjil is
port( clk : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(2 downto 0));
end counter_up_ganjil;
architecture Behavioral of counter_up_ganjil is
type state is (st1,st2,st3,st4) ;
signal p_state : state;
signal n_state : state;
begin
present_state : process (clk) is
begin
if (rising_edge (clk)) then
p_state <= n_state;
end if;
end process present_state;
136

next_state : process (p_state) is

begin
case (p_state) is
when st1 =>
n_state <= st2;
dout <= "001";
when st2 =>
n_state <= st3;
dout <= "011";
when st3 =>
n_state <= st4;
dout <= "101";
when st4 =>
n_state <= st1;
dout <= "111";
end case;
end process next_state;
end Behavioral;

5.4.1.4 File UCF

NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
# PlanAhead Generated physical constraints
NET "dout[2]" LOC = F12;
NET "dout[1]" LOC = E12;
NET "dout[0]" LOC = E11;
NET "clk" LOC = K17;
# PlanAhead Generated IO constraints
NET "clk" PULLDOWN;
NET "clk" SLEW = FAST;
NET "dout[2]" DRIVE = 8;
NET "dout[1]" DRIVE = 8;
NET "dout[0]" DRIVE = 8;

5.4.1.5 Timing Diagram

137

Gambar 5.7 Timing Diagram Rangkaian Counter-Up ganjil

5.4.1.6 Report File

138

5.4.1.7 Synthesis Report

Release 14.4 - xst P.49d (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.46 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.46 secs
--> Reading design: counter_up_ganjil.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis

139

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
====================================================
=*

Synthesis Options Summary

====================================================
=
---- Source Parameters
Input File Name

: "counter_up_ganjil.prj"

Input Format

: mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name

: "counter_up_ganjil"

Output Format

: NGC

Target Device

: xc3s500e-4-fg320

---- Source Options

Top Module Name

: counter_up_ganjil

Automatic FSM Extraction

: YES

FSM Encoding Algorithm

: Auto

Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Mux Style

: No
: LUT
: Yes
: Auto
: Yes
: Auto
140

Decoder Extraction

: YES

Priority Encoder Extraction

: Yes

Shift Register Extraction

: YES

Logical Shifter Extraction

: YES

XOR Collapsing
ROM Style

: YES
: Auto

Mux Extraction

: Yes

Resource Sharing

: YES

Asynchronous To Synchronous
Multiplier Style

: NO

: Auto

Automatic Register Balancing

: No

---- Target Options

Add IO Buffers

: YES

Global Maximum Fanout

: 100000

Add Generic Clock Buffer(BUFG)

Register Duplication
Slice Packing

: 24

: YES
: YES

Optimize Instantiated Primitives : NO

Use Clock Enable

: Yes

Use Synchronous Set

: Yes

Use Synchronous Reset

: Yes

Pack IO Registers into IOBs

: Auto

Equivalent register Removal

: YES

---- General Options

Optimization Goal

: Speed

Optimization Effort

:1

Keep Hierarchy

: No

Netlist Hierarchy

: As_Optimized

RTL Output
Global Optimization
Read Cores

: Yes
: AllClockNets
: YES
141

Write Timing Constraints

: NO

Cross Clock Analysis

: NO

Hierarchy Separator

:/

Bus Delimiter

: <>

Case Specifier

: Maintain

Slice Utilization Ratio

: 100

BRAM Utilization Ratio

Verilog 2001

: 100
: YES

Auto BRAM Packing

Slice Utilization Ratio Delta

: NO
:5

====================================================
====================================================
==*

HDL Compilation

====================================================
=WARNING:HDLParsers:3607 - Unit work/counter_up_ganjil is now
defined in a different file. It was defined in
"C:/Users/q/Desktop/Percobaan ke 5
fix/percobaan_ke_5/counter_up_ganjil.vhd", and is now defined in
"C:/Users/samila/Desktop/tugas VHDL Fix/Percobaan ke 5
fix/percobaan_ke_5/counter_up_ganjil.vhd".
WARNING:HDLParsers:3607 - Unit work/counter_up_ganjil/Behavioral
is now defined in a different file. It was defined in
"C:/Users/q/Desktop/Percobaan ke 5
fix/percobaan_ke_5/counter_up_ganjil.vhd", and is now defined in
"C:/Users/samila/Desktop/tugas VHDL Fix/Percobaan ke 5
fix/percobaan_ke_5/counter_up_ganjil.vhd".
Compiling vhdl file "C:/Users/samila/Desktop/tugas VHDL
Fix/Percobaan ke 5 fix/percobaan_ke_5/counter_up_ganjil.vhd" in
Library work.
Architecture behavioral of Entity counter_up_ganjil is up to date.

142

====================================================
=*

Design Hierarchy Analysis

Analyzing hierarchy for entity <counter_up_ganjil> in library <work>

(architecture <behavioral>).
====================================================
=*

HDL Analysis

====================================================
=Analyzing Entity <counter_up_ganjil> in library <work> (Architecture
<behavioral>).
Entity <counter_up_ganjil> analyzed. Unit <counter_up_ganjil>
generated.
====================================================
=*

HDL Synthesis

====================================================
=Performing bidirectional port resolution...
Synthesizing Unit <counter_up_ganjil>.
Related source file is "C:/Users/samila/Desktop/tugas VHDL
Fix/Percobaan ke 5 fix/percobaan_ke_5/counter_up_ganjil.vhd".
Found finite state machine <FSM_0> for signal <p_state>.
----------------------------------------------------------------------| States

|4

| Transitions
| Inputs

|4

|0

| Outputs

|3

| Clock

| clk

| Power Up State
| Encoding
| Implementation

|
(rising_edge)

| st1
| automatic
| LUT

|
|
|
|

----------------------------------------------------------------------Summary:
inferred 1 Finite State Machine(s).
143

Unit <counter_up_ganjil> synthesized.

====================================================
=HDL Synthesis Report
Found no macro
====================================================
====================================================
==*

Advanced HDL Synthesis

====================================================
=Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <p_state/FSM> on signal <p_state[1:2]> with user
encoding.
------------------State | Encoding
------------------st1 | 00
st2 | 01
st3 | 10
st4 | 11
------------------====================================================
=Advanced HDL Synthesis Report
Macro Statistics
# FSMs

:1

====================================================
====================================================
==*

Low Level Synthesis

====================================================
=Optimizing unit <counter_up_ganjil> ...
Mapping all equations...
Building and optimizing final netlist ...

144

Found area constraint ratio of 100 (+ 5) on block counter_up_ganjil,

actual ratio is 0.
Final Macro Processing ...
====================================================
=Final Register Report
Macro Statistics
# Registers

:2

Flip-Flops

:2

====================================================
====================================================
==*

Partition Report

====================================================
=Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------====================================================
=*

Final Report

====================================================
=Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: counter_up_ganjil.ngr
: counter_up_ganjil

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: No

Design Statistics
# IOs

:4

Cell Usage :
# BELS

:2

LUT2

:1

VCC

:1
145

# FlipFlops/Latches
#

FD

FDR

:2
:1
:1

# Clock Buffers
#

:1

BUFGP

:1

# IO Buffers

:3

:3

OBUF

====================================================
=Device utilization summary:
--------------------------Selected Device : 3s500efg320-4
Number of Slices:

1 out of 4656

0%

Number of Slice Flip Flops:

2 out of 9312

0%

Number of 4 input LUTs:

1 out of 9312

0%

4 out of

1%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

4
1 out of

232
24

4%

--------------------------Partition Resource Summary:

--------------------------No Partitions were found in this design.
--------------------------====================================================
=TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS
ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO
THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
-----------------146

-----------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
clk

| BUFGP

|2

-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
---------------------------------------No asynchronous control signals found in this design
Timing Summary:
--------------Speed Grade: -4
Minimum period: 2.225ns (Maximum Frequency: 449.438MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.394ns
Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
====================================================
=Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.225ns (frequency: 449.438MHz)
Total number of paths / destination ports: 3 / 2
------------------------------------------------------------------------Delay:
Source:
Destination:
Source Clock:

2.225ns (Levels of Logic = 1)

p_state_FSM_FFd1 (FF)
p_state_FSM_FFd1 (FF)
clk rising

Destination Clock: clk rising

Data Path: p_state_FSM_FFd1 to p_state_FSM_FFd1
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

147

---------------------------------------- -----------FD:C->Q

2 0.591 0.622 p_state_FSM_FFd1

(p_state_FSM_FFd1)
LUT2:I0->O

1 0.704 0.000 p_state_FSM_FFd1-In1

(p_state_FSM_FFd1-In)
FD:D

0.308

p_state_FSM_FFd1

---------------------------------------Total

2.225ns (1.603ns logic, 0.622ns route)

(72.0% logic, 28.0% route)

====================================================
=Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------Offset:
Source:
Destination:
Source Clock:

4.394ns (Levels of Logic = 1)

p_state_FSM_FFd2 (FF)
dout<1> (PAD)
clk rising

Data Path: p_state_FSM_FFd2 to dout<1>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDR:C->Q

3 0.591 0.531 p_state_FSM_FFd2

(p_state_FSM_FFd2)
OBUF:I->O

3.272

dout_1_OBUF (dout<1>)

---------------------------------------Total

4.394ns (3.863ns logic, 0.531ns route)

(87.9% logic, 12.1% route)

====================================================
=Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.65 secs
148

-->
Total memory usage is 199992 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos

: 0 ( 0 filtered)

149

150

151

PENUTUP
Kesimpulan
Setelah

melakukan

keseluruhan

praktikum

ini,

penulis

dapat

menyimpulkan bahwasannya semua praktikum ini sangat penting untuk

menunjang Materi yang diberikan di kelas, disamping itu system komunikasi
juga dapat memudahkan kita untuk menyelesaikan suatu pekerjaan yang besifat
sukar dipecahkan.
Saran
Tingkatkan terus kemampuan asisten dalam mengasistensi laporanlaporan, buat para asisten jangan mengsistimewakan teman-teman dekatnya.
Jangan mempersulit mahasiswa yang akan asistensi, dalam menggoreksi
laporan yang masih terdapat kesalahan beritahukan letak kekurangan pada
laporan semuanya ,agar kami tidak bolak-balik untuk asistensi.
Sekian dan terimakasih untuk perhatianya.

152

DAFTAR PUTAKA

Elektronika, Laboratorium. 2014, Modul VHDL. Laboratorium Elektro :

Malang

Catatan Kuliah

153