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TELEMETRI KETINGGIAN AIR SEBAGAI PENGATUR
MODEL PINTU AIR BERBASIS

MIKROKONTROLER AT89S51 DAN PC
TUGAS AKHIR
Diajukan untuk memenuhi salah satu syarat memperoleh gelar Sarjana Teknik
Program Studi Teknik Elektro
Disusun Oleh :
BRIATMA KURNIA PUTRA PRISTIWADI

NIM : 025114006
PROGRAM STUDI TEKNIK ELEKTRO

JURUSAN TEKNIK ELEKTRO
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
TELEMETRI KETINGGIAN AIR SEBAGAI
PENGATUR MODEL PINTU AIR BERBASIS
MIKROKONTROLER AT89S51 DAN PC
TUGAS AKHIR
Diajukan untuk memenuhi salah satu syarat
memperoleh gelar Sarjana Teknik
Program Studi Teknik Elektro
disusun oleh :
NIM : 025114006
PROGRAM STUDI TEKNIK ELEKTRO

JURUSAN TEKNIK ELEKTRO
FAKULTAS TEKNIK
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2007
i
WATER LEVEL TELEMETRY AS A WATER
GATE MODEL REGULATOR BASED ON
PC AND AT89S51 MICROCONTROLLER
FINAL PROJECT
Presented as Partial Fulfillment of the Requirements
to Obtain the SARJANA TEKNIK Degree
in Electrical Engineering
by :
STUDENT NUMBER : 025114006
ELECTRICAL ENGINEERING DEPARTMENT

ENGINEERING FACULTY
SANATA DHARMA UNIVERSITY
YOGYAKARTA
2007
ii
(WATER LEVEL TELEMETRY AS A WATER GATE MODEL
REGULATOR BASED ON PC AND AT89S51 MICROCONTROLLER)
G
28 Juli
LEMBAR PERNYATAAN KEASLIAN KARYA
“Saya menyatakan dengan sesungguhnya bahwa tugas akhir yang saya tulis ini
tidak memuat karya atau bagian karya orang lain,
kecuali yang telah disebutkan dalam kutipan dan daftar pustaka,
sebagaimana layaknya karya ilmiah.”
Yogyakarta, 23 Juni 2007
Briatma Kurnia Putra Pristiwadi
v
MOTO DAN PERSEMBAHAN
Jenius adalah 1 % inspirasi dan 99 % keringat. Tidak ada yang

dapat menggantikan kerja keras. Keberuntungan adalah sesuatu
yang terjadi ketika kesempatan bertemu dengan kesiapan.
Thomas A. Edison
Yang terpenting dalam Olimpiade bukanlah kemenangan, tetapi
keikutsertaan ...
Baron Pierre De Coubertin
Kupersembahkan Karya ini :

Untuk Tuhan Yesus Kristus
Untuk Ayah dan Ibuku tercinta
Untuk Kakak dan adikku tersayang
Untuk Segenap Keluargaku
Untuk Semua teman dan sahabatku
Terimakasih atas segala dukungan, kasih dan cinta yang selalu diberikan
pada penulis.
vi
INTISARI
Telemetri ketinggian air memberikan kemudahan dalam mengukur ketinggian

air secara jarak jauh. Telemetri ketinggian air dapat diterapkan dalam sungai-sungai,
sehingga pemantauan ketinggian air sungai dapat terus dilakukan dalam tempat yang
aman jika terjadi kondisi alam yang tidak memungkinkan untuk melakukan
pengamatan, misalkan pada malam hari ataupun sewaktu terjadi hujan deras. Dalam
perancangan ini Telemetri ketinggian air akan digunakan untuk mengatur model
pintu air, sehingga nantinya dalam mengatur pintu air tidak lagi di lakukan secara
manual, PC akan secara otomatis mengontrol model pintui air sehingga di dapat
ketinggian air sungai sesuai dengan yang diinginkan oleh user.
Implementasi perancangan peralatan ini menggunakan potensiometer sebagai
sensor ketinggian air, ADC untuk mengubah data analog menjadi data digital,
mikrokontroler sebagai pengubah data pararel menjadi data serial dan sebagai
pengatur motor DC, modem FSK sebagai modulator data analog, pemancar dan
penerima FM sebagai alat transmisi, MAX 232 sebagai pengubah level tegangan, PC
sebagai pengontrol dan memonitor ketinggian air. Hasil pengukuran ketinggian air
pertama-tama dimodulasi secara FSK, kemudian modulasi dilanjutkan secara FM.
Pada penerima hasil pengukuran akan ditampilkan pada PC, data yang ditampilkan
pada PC di olah dan dibandingkan dengan data ketinggian yang dimasukkan oleh
user. Data hasil perbandingan digunakan sebagai acuan untuk mengatur ketinggian air
sungai pada model pintu air.,
Pada tugas akhir ini, perangkat keras dan perangkat lunak Telemetri
Ketinggian Air Sebagai Pengatur Model Pintu Air Berbasis Mikrokontroler AT89S51
dan PC berhasil dibuat. Progam dapat menampilkan hasil pengukuran ketinggian air
sungai, dapat menggatur model pintu air dan dapat memberi peringatan bahwa sungai
meluap.
Kata kunci : ketinggian air, FSK, Visual Basic
vii
ABSTRACT
Water level telemetry provides simple alternative to measure water level on

long distance. Water level telemetry can be used on the rivers, in order to observe
water level continualy at the safety place, wheatear is impossible realm condition to
do it, for examples in the night or the swift raining. In this program, water level
telemetry will be used to regulate the water gate model, so it did not manually
anymore. PC will be control the water gate model automatically until the water level
on the river will be obtained appropriate with the user want to get.
This implementation uses potentiometer as a water level sensor, ADC as an
analogous to digital data converter, microcontroller as a data pararel to serial
converter and DC motor regulator, FSK modem as a analogous modulator, FM
transceiver as a transmitter device, MAX 232 as a voltage level converter , PC as a
water level monitor and controller. At transmitter side, the result of water level
measurement will be modulated to FSK, and transmitted to FM. At receiver side the
result of measuring will be proceed and compared with the water level data that has
been inputted by user.The result comparation data will be used as a reference to
regulate the river water level on the water gate model
On this final task, the hardware and software of the water level telemetry as a
water gate model regulator based on PC and Microcontroller AT89S51 could be
made successfully. The program can display the result of river water level
measurement, regulate the water gate model and provide the warning that the water
was over flow
Key words : water level, FSK, Visual Basic
viii
KATA PENGANTAR
Puji syukur penulis panjatkan kepada Allah Bapa disurga, yang telah
memberikan kasih karunia, anugerah, dan berkat-Nya, sehingga penulis dapat
menyelesaikan penulisan tugas akhir dengan baik.
Penulis menyadari bahwa dalam penulisan tugas akhir ini, penilis
mendapatkan banyak bantuan dan dorongan dari berbagai pihak. Oleh karena itu,
pada kesempatan ini perkenankanlah dengan segala kerendahan hati dan penuh
hormat, penulis mengucapkan terima kasih yang sebesar-besarnya kepada:
1. Romo Ir. Greg. Heliarko SJ.,SS.,BST.,MA.,MSC Selaku Dekan Fakultas
Teknik Universitas Sanata Dharma Yogyakarta.
2. Bapak A. Bayu Primawan, S.T., M.Eng selaku Ketua Jurusan Teknik
Elektro Universitas Sanata Dharma Yogyakarta dan selaku pembimbing II
yang membimbing dan mengarahkan dalam penyusunan tugas akhir ini.
3. Bapak Martanto, S.T, M.T selaku pembimbing I atas segala pemikiran
dalam membimbing dan mengarahkan penulis dari awal hingga akhir.
4. Seluruh dosen di Fakultas Teknik Elektro yang tidak dapat di sebutkan
satu persatu, yang telah mendidik penulis untuk mengetahui lebih dalam
tentang Teknik Elektronika.
5. Seluruh Staf Perpustakaan Universitas Sanata Dharma yang sudah
memberikan layanan dan bantuan selama proses pencarian referensi.
6. Kedua orang tua penulis yang telah memberikan doa, dorongan moril
maupun material, kasih dan kesabaran yang tak pernah putus sehingga
penulis dapat menyelesaikan tugas akhir ini.
ix
7. Mbak Putri, Dik Christa yang telah memberikan doa dan kesabaran karena
ke-Betean ku selama penyusunan tugas akhir ini.
8. Teman-teman teknik Elekro yang sudah membantu : Nango, Hugo, Antin,
Alex, BE”JO”lin (makasih buat pinjaman kabelnya), Ratna, Dwi, Wiryadi,
Eric “Decoy” (thank you buat laptop Vaionya).
9. Teman-teman di “ROSO KANGEN.EO” : Rinto, Gogon, Mbah Oko,
Kecer, Mendrik yang telah membantu dalam memotong aklirik dan
membuat maket pintu airnya, Kuemprut yang membantu beli akrilik ampe
tangan pegel. Mas Bambang makasih atas grendonya, Mas Nata makasih
atas cara pengeleman akliriknya dan Pak Ketua Bp Supangat makasih atas
pinjaman pompa airnya.
10. Rekan-rekan di : NANDI Elektronik and Comp, QUANTUM Elektronik,
Mas Pri di SONY Group Elektronik, CHRISTAMAS Elektronik yang
telah memberikan saran-saran dan bantuan dalam penyusunan tugas akhir
ini. Bengkel bubut SUMBER WIDODO yang telah membuatkan gerigi,
dan mur baut model pintu air.
11. Teman senasib dan sepenanggungan : Mas Teguh tea kapan selesai skripsi,
Heriyanto S.E buat hari-hari yang indah dulu, Yanto ,Aan ,Ali makasih
karna telah mengajari kerasnya hidup. Mbak Getik, Mas Supri dan Mbak
Conie, Putri Imut makasih atas tumpangan tempat buat tidur selama belum
dapat kos. Sandi Man. My Best Friend Bayu S.H makasih telah menjadi
sobatku dari SMU hingga sekarang.
12. Teman-teman kost T-KIP : Ari (Gendut) email mu saru, Dedik kapan
bimbingan Rohani lagi, Agung Bawono, S.T fleksibel aja Mo, Dody
x
Prasetyo P, S.T makasih ya atas segala bantuan pembuatan progam VB
dan Mikronya
13. Marcopolo Team : Bule, Gepenk, Me2t, Plenthong, Koten, Lambezz,
Andex, Ahox yang selalu menjadi sumber inspirasiku dan sumber
senyumku. Jangan selamanya jadi “BATMAN”
14. Laboran teknik elektro : mas Suryono makasih udah ngajari ngetrim
pemancar , mas Mardi buat ijin titip barang-barang, mas Broto yang udah
mau nungguin serta jadi teman sewaktu memperbaiki alat dan mengambil
data, dan mas Yusuf yang udah mau membuka pintu dan menunggu
selama mas Broto cuti.
15. Anak-anak seni UNY : Sintha, Pi2T, Vanti, Rika yang selalu memberikan
senyum di waktu aku BT banget.
16. Anak-anak Tuhan di GKJ Sabda Winedhar Surakarta yang dah jadi teman
dalam satu pelayanan. Makasih atas dukungannya.
17. Regenerasi Motorku : Grand 94, Supra 00, dan Vega R 05 yang selalu
setia menemani perjalanan SOLO – YOGYA, yang rela kehujanan dan
kepanasan waktu cari komponen. Jangan cepet-cepet jadi barang
rongsokan ya ….????????.
18. Kamar kecil 3 x 2.5 bertuliskan “RUANG TEKNIK”, di tempat ini
kutulis semua angan-angan dan harapan hidupku.
19. Teman-teman mahasiswa jurusan Teknik Elekro dan semua pihak yang
tidak dapat disebutkan satu persatu atas setiap bantuannya.
xi
Penulis menyadari bahwa masih banyak kelemahan dan kekurangan dari
penulisan tugas akhir ini. Oleh karena itu segala kritik dan saran yang bersifat
membangun sangat penulis harapkan.
Akhir kata penulis berharap agar skripsi ini dapat bermanfaat bagi
penulis maupun pembaca semuanya.
Yogyakarta, 26 Juli 2007
Penulis
xii
DAFTAR ISI
HALAMAN JUDUL ...................................................................... i
HALAMAN PERSETUJUAN PEMBIMBING............................. iii
HALAMAN PENGESAHAN ........................................................ iv
PERNYATAAN KEASLIAN KARYA................................................ v
MOTO DAN PERSEMBAHAN............................................................. vi
INTISARI...................................................................................................... vii
ABSTRACT ................................................................................................. viii
KATA PENGANTAR ............................................................................... ix
DAFTAR ISI ................................................................................................ xiii
DAFTAR TABEL............................................................................................ xviii
DAFTAR GAMBAR ....................................................................................... xix
DAFTAR LAMPIRAN.................................................................................... xxiii
BAB I. PENDAHULUAN........................................................................ 1
1.1 Judul…………………………………………………………………… 1
1.2 Latar Belakang ....................................................................................... 1
1.3 Tujuan Penelitian ................................................................................... 2
1.4 Manfaat Penelitian ................................................................................. 3
1.5 Pembatasan Masalah.............................................................................. 3
1.6 Metedologi Penelitian ............................................................................ 3
1.7 Sistematika Penulisan ............................................................................ 4
xiii
BAB II. DASAR TEORI........................................................................... 5
2.1 Penguat Inverting ................................................................................... 6
2.2 Penjumlah Tegangan………………………………………………….. 7
2.3 Buffer Tegangan……………………………………………………….. 8
2.4 Rangkaian Pembagi Tegangan………………………………………... 8
2.5 Pengubah Analog ke Digital (ADC)…………………………………. . 8
2.6 Modem FSK…………………………………………………………... 10
2.6.1 Modulator FSK XR-2206…………………………………….. 11
2.6.2 Demodulator FSK XR-2211………………………………… . 12
2.7 Mikrokontroler AT89S51……………………………………………… 14
2.7.1 Komunikasi Serial.................................................................... 15
2.7.2 Reset......................................................................................... 17
2.8 Pengubah Level TTL ke Level Serial .................................................... 17
2.9 Konfigurasi Port Serial .......................................................................... 18
2.10 Motor DC .............................................................................................. 20
BAB III PERANCANGAN ............................................................ 22
3.1 Sensor Ketinggian Air ........................................................................... 23
3.2 Potensio Multi Turn............................................................................... 24
3.3 Pengkondisi Sinyal ................................................................................ 25
3.3.1 Pembagi Tegangan .................................................................. 27
3.3.2 Buffer Tegangan Referensi ...................................................... 28
3.3.3 Penguat Inverting Vsensor ....................................................... 28
3.3.4 Rangkaian Penjumlah Tegangan.............................................. 29
3.4 Pengubah Analog ke Digital (ADC)...................................................... 30
xiv
3.5 Konfigurasi Mikrokontroler AT89S51 Sebagai Pengubah Data Pararel
8 bit Menjadi Data Serial....................................................................... 31
3.6 Pemprograman Mikrokontroler Pengubah Data Pararel Menjadi Serial 33
3.6.1 Rutin Baca ADC ...................................................................... 34
3.6.2 Kirim Data................................................................................ 35
3.7 Modulator FSK...................................................................................... 35
3.8 Pemancar dan Penerima FM.................................................................. 37
3.10 Demodulator FSK.................................................................................. 37
3.11 Mikrokontroler AT89S51 Sebagai Pengatur Arah Putaran Motor DC . 40
3.12 Pengubah Level Tegangan TTL Menjadi RS 232 ................................... 42
3.13 Pemprograman Visual Basic ................................................................. 43
3.13.1 Form Utama ............................................................................. 44
3.13.2 Rutin Olah Data........................................................................ 47
3.13.3 Form Pengaturan Manual......................................................... 48
3.13.4 Atur Ketinggian........................................................................ 50
3.13.5 Menu Bantuan .......................................................................... 50
3.14 Pembalik Putaran Motor DC ................................................................. 52
3.15 Rancangan Pengendali Pintu Air Menggunakan Motor DC ................. 53
3.16 Pembatas Putaran Motor ....................................................................... 55
3.17 Warning Sytem....................................................................................... 56
BAB IV. HASIL PENGAMATAN DAN PEMBAHASAN.......... 57
4.1 Pengamatan Sensor Ketinggian Air ..................................................... 57
4.2 Pengamatan Rangkaian Pengkondisi Sinyal........................................ 62
4.3 Pengamatan Pengubah Analog Ke Digital (ADC0804)....................... 66
xv
4.4 Pengamatan Keluaran Modulator FSK XR-2206 ................................ 68
4.5 Pengamatan Keluaran Demodulator FSK XR-2211 ............................ 71
4.6 Pengamatan RS232 .............................................................................. 73
4.7 Pengamatan Program Mikrokontroler AT89S51……………… ......... 74
4.7.1 Pengamatan Program Mikrokontroler AT89S51 Pada Bagian
Pemancar………......................................................................... 74
4.7.2 Pengamatan Program Mikrokontroler AT89S51 Pada Bagian
Penerima..................................................................................... 75
4.8 Pengamatan Rangkaian Pembalik Putaran Motor DC dan Warning
System L293D ..................................................................................... 75
4.9 Pengamatan Kerja Program Visual Basic ............................................ 77
4.9.1 Pengamatan Form Pengaturan Otomatis.................................... 77
4.9.2 Pengamatan Form Pengaturan Manual ...................................... 80
4.9.3 Pengamatan Form Menu Bantuan Menggunakan Program ....... 81
4.10 Pengamatan Unjuk Kerja Sistem ......................................................... 82
4.10.1 Pengamatan Unjuk Kerja Sistem Menggunakan Media ........
Transmisi Kabel ...................................................................... 82
4.10.2 Pengamatan Unjuk Kerja Sistem Secara Telemetri FM.......... 83
4.10.2.1 Dengan Kecepatan Pengisyaratan Data 1200 bps........ 84
4.10.2.1 Dengan Kecepatan Pengisyaratan Data 1200 bps........ 85
4.10.3 Kerja Sistem Pada Pengaturan Otomatis................................. 88
4.10.4 Kerja Sistem Pada Pengaturan Manual ................................... 91
BAB V. Kesimpulan dan Saran ............................................................... 95
5.1 Kesimpulan ...................................................................................... 95
xvi
5.2 Saran ...................................................................................... 95
DAFTAR PUSTAKA
LAMPIRAN
xvii
DAFTAR TABEL
1. Tabel 2.1 Standar FSK...................................................................... 14
2. Tabel 2.2 Konfigurasi kaki-kai DB-9 .............................................. 20
3. Tabel 3.1 Penskalaan tegangan......................................................... 26
4. Tabel 3.2 Tabel kebenaran pembalik putaran motor DC.................. 53
5. Tabel 4.1 Tabel perbandingan data praktek dan perhitungan teori ..
rangkaian pengkondisi sinyal.............................................................. 61
6. Tabel 4.2 Tabel perbandingan data praktek dan teori ADC0804 ..... 67
7. Tabel 4.3 Tabel keluaran modulator FSK XR-2206......................... 69
8. Tabel 4.4 Tabel keluaran demodulator FSK XR-2211..................... 72
9. Tabel 4.5 Tabel pengamatan P1 Mikrokontroler AT89S51 pada.....
bagian penerima................................................................................... 76
10. Tabel 4.6 Tabel pengamatan IC L293D ........................................... 77
11. Tabel 4.7 Tabel pengamatan ketinggian air sungai yang .................
tertampil pada PC dengan media transmisi kabel ............................... 83
12. Tabel 4.8 Tabel perbandingan ketinggian air sungai sebenarnya ....
dengan yang Yang tertampil pada PC menggunakan .........................
transmisi pemancar FM....................................................................... 84
13. Tabel 4.9 Tabel pengamtan ketinggian air sungai yang tertampil....
pada PC dengan kecepatan pengisyaratan data 300 bps ..................... 86
14. Tabel 4.10 Pengamatan kerja system pengaturan manual .................. 91
xviii
DAFTAR GAMBAR
1. Gambar 2.1 Konfigurasi penguat inverting ...................................... 7
2. Gambar 2.2 Konfigurasi penjumlah tegangan .................................. 7
3. Gambar 2.3 Konfigurasi buffer tegangn ........................................... 8
4. Gambar 2.4 Konfigurasi pembagi tegangan ..................................... 9
5. Gambar 2.5 Konfigurasi typical ADC 0804 ..................................... 10
6. Gambar 2.6 Sistem modulasi FSK biner .......................................... 11
7. Gambar 2.7 Sinusoidal FSK generator ............................................. 11
8. Gambar 2.8 Rangkaian demodulator FSK........................................ 13
9. Gambar 2.9 Tracking Bandwidth XRr-2211..................................... 14
10. Gambar 2.10 Konfigurasi tombol reset ............................................... 17
11. Gambar 2.11 Level tegangan TTL dan RS232 pada pengiriman
huruf “A” tanpa bit paritas..................................................................... 18
12. Gambar 2.12 Konektor DB-9 ............................................................. 19
13. Gambar 3.1 Blok diagram pengirim ................................................. 22
14. Gambar 3.2 Blok diagram penerima................................................. 22
15. Gambar 3.3 Skema telemetri ketinggian air sebagai pengatur
model pintu air ...................................................................................... 22
16. Gambar 3.4 Potensio sebagai rangkaian pembagi tegangan............. 23
17. Gambar 3.5 Rancangan sensor ketinggian air sungai ....................... 23
18. Gambar 3.6 Pembagi tegangan menggunakan potensiometer .......... 28
19. Gambar 3.7 Buffer tegangn referensi ............................................... 28
20. Gambar 3.8 Penguat inverting Vsensor ............................................ 29
21. Gambar 3.9 Rangkaian penjumlah V1 dan V2 ................................. 29
37. Gambar 3.10 Konfigurasi ADC 0804 ................................................. 30
xix
38. Gambar 3.11 Pengubah data pararel menjadi serial menggunakan
AT89S51 ...................................................................................... 32
39. Gambar 3.12 Diagram alir pemprograman Mikrokontroler ............... 33
40. Gambar 3.13 Diagram alir pembacaan ADC...................................... 35
41. Gambar 3.14 Modulator FSK XR-2206 ............................................. 36
42. Gambar 3.15 Demodulator FSK XR-2211 ......................................... 40
43. Gambar 3.16 Mikrokontroler AT89S51 sebagai pengontrol arah
putaran motor DC .................................................................................. 41
44. Gambar 3.17 Diagram alir pengontrol arah putaranmotor DC........... 41
44. Gambar 3.18 Pengubah aras tegangan................................................ 42
45 Gambar 3.19 Rancangan form utama pengatur pintu air.................... 44
46. Gambar 3.20 Diagram alir form utama............................................... 45
47. Gambar 3.21 Pesan pemberitahu sungai meluap ................................ 46
48. Gambar 3.22 Pesan pemberitahu sungai kering ................................. 46
49. Gambar 3.23 Diagram alir olah data ketinggian air............................ 47
50. Gambar 3.24 Rancangan form pengaturan manual ............................ 48
51. Gambar 3.25 Gambar diagram alir pengaturan manual...................... 49
52. Gambar 3.26 Tampilan atur ketinggian air........................................ 50
53. Gambar 3.27 Diagram alir menu bantuan........................................... 51
54. Gambar 3.28 Rancangan tampilan menu Tentang.............................. 51
55. Gambar 3.29 Rancangan tampilan menu Menggunakan Program ..... 52
56. Gambar 3.30 Rangkaian pembalik putaran motor .............................. 52
57. Gambar 3.31 Model pintu air.............................................................. 54
58. Gambar 3.32 Pembatas putaran motor DC ......................................... 55
59. Gambar 3.33 Rangkaian pembatas putaran motor DC ....................... 55
xx
60. Gambar 3.34 Rangkaian warning system............................................ 57
61. Gambar 4.1a Gambar Vsensor potensio multi turn saat air naik........ 58
62 Gambar 4.1b Gambar Vsensor potensio multi turn saat air turun ...... 58
63 Gambar 4.2 Gambar sensor ketinggian sistem lengan...................... 49
64 Gambar 4.3 Gambar rangkaian pengkondisi sinyal revisi................ 61
65. Gambar 4.4a Vo sensor ketinggian potensio linear sistem lengan .....
saat air sungai naik................................................................................. 61
66. Gambar 4.4b Vo sensor ketinggian potensio linear sistem lengan .....
saat air sungai naik................................................................................. 62
67. Gambar 4.5 Bentuk gelombang keluaran Modulator XR-2206........ 70
68. Gambar 4.6 Bentuk keluaran gelombang XR-2206 dengan input ...
data serial 01010111b ........................................................................... 71
69. Gambar 4.7 Gambar output modem FSK ........................................ 73
70. Gambar 4.8 Pengubahan level tegangan TTL menjadi level tegangan
RS232.………........................................................................................ 74
71. Gambar 4.9a P2.1 berlogika 0 ............................................................ 75
72. Gambar 4.9.b P2.0 berlogika 0 ............................................................ 75
73. Gambar 4.9c P2.2 berlogika 0 ............................................................ 75
74. Gambar 4.10 Instruksi untuk mengisi ketinggian air yang akan di atur 78
75. Gambar 4.11a Menu pemberitahu nilai yang dimasukkan melebihi ba-
tas yang seharusnya ............................................................................... 78
76. Gambar 4.11b Menu Pemberitahu bila ketinggian air yang akan di
atur belum diisi ...................................................................................... 78
77. Gambar 4.12 Tampilan program Pengaturan Otomatis ...................... 79
78. Gambar 4.13 Gambar tampilan utama pengaturan manual ................ 81
xxi
79. Gambar 4.14 Menu Bantuan Menggunakan program ........................ 81
80. Gambar 4.15 Pengguanaan kabel sebagai media transmisi ................ 82
81. Gambar 4.16 Kesalahan proses demodulasi data FSK ....................... 85
82. Gambar 4.17 Output modem FSK dengan kecepatan ........................
Pengisyaratan data 300 bps.................................................................... 87
83. Gambar 4.18 Gambar grafik perubahan waktu ..................................
terhadap ketinggian air yang diatur........................................................ 89
83. Gambar 4.19 Tampilan peringatan sungai meluap ............................. 90
84. Gambar 4.20 Tampilan sungai kering ................................................ 90
85. Gambar 4.21 Pesan pemberitahu pintu sedang di buka ...................... 93
86. Gambar 4.22 Pesan pemberitahu pintu sedang di tutup ..................... 93
87. Gambar 4.23 Pesan pemberitahu pintu tidak dapat di buka lagi ........ 94
88. Gambar 4.24 Pesan pemberitahu pintu tidak dapat di tutup lagi ........ 94
xxii
DAFTAR LAMPIRAN
A. Gambar Rangkaian...................................................................................... L1
B. Listing program Visual Basic 6.0................................................................ L3
B.1. Listing program pengaturan otomatis ............................................ L3
B.2. Listing program pengaturan manual .............................................. L10
C. Listing program Mikrokontroler AT89S51................................................. L17
C.1. Listing program bagian pemancar................................................. L17
C.2. Listing program bagian penerima .................................................. L2
D. Foto Alat.. .................................................................................................. L22
E. Data Sheets.................................................................................................. L25
E.1. Motor DC........................................................................................ L25
E.2. CA3140........................................................................................... L26
E.3. ADC0804........................................................................................ L36
E.4. AT89S51......................................................................................... L50
E.5. XR-2206 ......................................................................................... L67
E.6. XR-2211 ......................................................................................... L79
E.7. L293D............................................................................................. L89
E.8. MAX232......................................................................................... L97
xxiii
BAB I
PENDAHULUAN
1.1. Judul
Telemetri Ketinggian Air Sebagai Pengatur Model Pintu Air Berbasis
Mikrokontroler AT89C51 dan PC (Water Level Telemetry As Flood Gate Regulator
Model Based On PC and AT89S51 Microcontroller)
1.2. Latar Belakang Masalah
Dewasa ini perkembangan elektronika sudah maju sedemikian pesatnya. Salah
satu perkembangannya adalah banyaknya peralatan elektronika yang membantu dan
berpengaruh di dalam kehidupan sehari–hari. Perkembangan tersebut menuntut segala
sesuatunya bergerak cepat, praktis, dan serba instan, tidak hanya di perkotaan saja,
tetapi juga hingga ke pelosok desa. Masyarakat di kota maupun di desa saat ini sudah
dapat menikmati berbagai kemudahan dan kenyamanan dari beraneka ragam peralatan
elektronis yang ada, misalnya kipas angin yang diberi timer untuk mengatur kapan
harus berhenti berputar, pompa air yang diberi sensor sehingga pompa akan berhenti
ketika air di bak penampungan sudah penuh, lampu taman yang akan menyala sendiri
ketika hari sudah mulai gelap, dan masih banyak lagi. Semakin banyaknya sensor–
sensor elektronik yang ada, menuntut diciptakannya alat–alat baru dengan
mengaplikasikan sensor-sensor elektronik untuk mengontrol sesuatu yang bertujuan
untuk membantu di dalam mempermudah kerja manusia.
Sungai – sungai irigasi persawahan sekarang ini untuk mengatur ketinggian
airnya masih banyak dilakukan secara manual. Ada berapa orang yang bertugas untuk
2
mengawasi dan mengatur pintu air supaya air sungai tidak sampai meluap atau supaya
tidak terjadi kekurangan pasokan air.
Dari hal di atas akan timbul suatu permasalahan bila harus bekerja pada waktu
malam hari, karena air yang dikontrol tidak sepenuhnya kelihatan, atau harus
mengatur pintu air di waktu kondisi hujan, di mana air sungai yang akan dikontrol
ketinggiannya akan selalu berubah tergantung curah hujan sehingga diperlukan
pengawasan ekstra yang terus menerus.
Untuk mengatasi permasalahan – permasalahan tersebut maka diharapkan ada
suatu alat yang dapat untuk mengatur pintu air sesuai dengan ketinggian air sungai
yang diinginkan dengan perawatan dan penggunaan yang mudah, serta hasil
ketinggian air yang mudah dibaca.
1.3. Tujuan
Dalam penelitian ini, peneliti mempunyai beberapa tujuan yang hendak di capai,
yaitu :
1. Membuat perangkat keras yang dapat mengukur ketinggian air sungai dan
mengirimkan data ketinggian air sungai ke komputer melalui komunikasi serial
yang termodulasi frekuensi
2. Membuat program pemantau ketinggian air sungai, menampilkannya dan
kemudian dipergunakan untuk mengatur model pintu air.
3. Mengaplikasikan pemprograman mikrokontroler AT89S51 dan pemprograman
Visual Basic.
4. Mengaplikasikan sistem komunikasi termodulasi frekuensi.

3
1.4. Manfaat
Mengacu dari beberapa tujuan yang akan dicapai, diharapkan penalitian ini
dapat memberikan manfaat :
1. Penelitian ini diharapkan dapat dijadikan acuan dalam mengembangkan model
pengendalian pintu air yang sesungguhnya.
2. Mempermudah seseorang di dalam melakukan pemantauan dan pengaturan
ketinggian air sungai
1.5. Batasan Masalah
Batasan pada alat yang dibuat yaitu:
1. Ketinggian air maksimum yang dapat terukur oleh sensor adalah 20 cm.
2. Sensor Ketinggian air menggunakan Potensiometer.
3. Komunikasi antara sensor ketinggian air dan motor DC dengan komputer
mengunakan Serial Communication (COM), dan pemprograman Visual Basic.
4. Telemetri ketinggian air menggunakan sinyal termodulasi frekuensi (FM).
5. Pemancar dan penerima FM tidak termasuk di dalam perancangan.
1.6 Metodologi Penelitian
Agar dapat melakukan perancangan alat dengan baik, maka penulis
membutuhkan masukan serta referensi yang didapatkan dengan metode :
1. Studi kepustakaan yang mencakup literatur-literatur, gambar-gambar dan manual.
2. Perancangan hardware dan software.
3. Pembuatan hardware dan software berdasar hasil perancangan.
4. Pengujian hardware dan software.

4
5. Pengambilan data dari hardware dan software yang telah dibuat.
6. Memberikan kesimpulan.
1.7 Sistematika Penulisan
Sistematika penulisan terdiri dari lima bab, yaitu :
Bab I membahas tentang latar belakang, tujuan penelitian, manfaat,
pembatasan masalah, metedologi penelitian dan sistematika penulisan.
Bab II membahas dasar teori yang mendukung penelitian, yaitu tentang
Mikrokontroler AT89S51, Op-Amp, ADC 0804, RS232, modem FSK, Pemancar dan
penerima FM.
Bab III membahas tentang perancangan perangkat keras berupa sensor
ketinggian air, pengondisi sinyal, pengubah data dari analog ke digital (ADC),
konfigurasi mikrokontroler, konfigurasi Modem FSK, RS232, pembalik putaran
motor dengan IC L293D. Perangkat lunak berupa pemrograman mikrokontroler dan
pemrograman komputer dengan program Visual Basic.
Bab IV membahas tentang pengamatan kerja dari perangkat keras dan
perangkat lunak yang telah dibuat.
Bab V berisi kesimpulan dan saran.

BAB II
DASAR TEORI
Pengatur pintu air dibuat untuk mengendalikan debit air yang akan dialirkan
ke sungai, dengan cara membandingkan ketinggian air sungai yang dipantau dengan
ketinggian air yang diinginkan. Pemantauan ketinggian air dilakukan secara telemetri,
yakni dengan meletakkan sensor ketinggian air pada suatu tempat yang hendak kita
atur ketinggiannya, kemudian data hasil pemantuan di kirim secara termodulasi
frekuensi. Data hasil pemantauan yang diterima kemudian ditampilkan di PC.
Software pengatur model pintu air di buat dengan program Visual basic. Adapun cara
kerja program tersebut adalah sebagai berikut :
1. Data ketinggian yang ditampilkan berupa angka
2. Pada pengaturan otomatis user akan di minta untuk memasukkan nilai
ketinggian yang akan diatur.
3. Nilai ketinggian yang di masukkan user akan dipakai PC untuk mengatur
model pintu air, dengan cara membandingkan antara data yang di isi user
dengan data yang di hasilkan sensor air, sehingga didapat ketinggian air sesuai
dengan yang diinginkan user.
4. Pada pengaturan manual user dapat mengatur model pintu air untuk membuka
atau menutup secara manual, yakni dengan cara menekan tombol buka atau
tutup sehingga pintu air akan membuka atau menutup sampai tombol stop
ditekan.
5. Bila ketinggian air melebihi 18 cm, maka akan diberi peringatan berupa bunyi
Buzzer.
6
Untuk membangun sistem tersebut dibutuhkan rangkaian untuk memantau
ketinggian air yang disusun oleh rangkaian Op-Amp yang berupa rangkaian
pengondisi sinyal. Data yang telah dikondisikan akan diubah menjadi data digital oleh
rangkaian ADC. Data digital dari ADC dibah menjadi data serial oleh
mikrokontroler, dimodulasikan secara FSK menggunakan XR-2206, ditransmisikan
menggunakan pemancar FM, data diterima kembali menggunakan penerima FM, di
demodulasikan menjadi data semula menggunakan XR-2211, kemudian dikirim ke
komputer dengan perantara RS232, komputer melakukan perintah-perintah untuk
mengatur pintu air. Komponen telemetri ketinggian air sebagai pengatur model pintu
air dapat dijelaskan sebagai berikut.
2.1 Penguat Inverting
Tegangan masukan Vin menggerakkan masukan pembalik melalui resistor
RA seperti pada gambar 2.1. Ini akan menghasilkan tegangan masukan pembalik
V1. Tegangan masukan diperkuat oleh perolehan tegangan kalang terbuka untuk
menghasilkan tegangan keluaran yang dibalikkan. Tegangan keluaran kemudian
diumpan balikkan ke masukan melalui resisitor umpan balik RB. Ini menghasilkan
umpan balik negatif karena keluarannya berbeda 1800 dengan masukan. Dengan
kata lain, setiap perubahan pada V1 dihasilkan oleh tegangan masukan yang
berlawanan dengan sinyal keluaran
Tegangan keluaran penguat inverting ditunjukan pada persamaan 2.1.
RB
VO = − × Vin …………………….…………………………… (2.1)
RA
7
RB
Vee
4
8
1
RA
2 -
V1 6
3 +
Vin Vo
CA3130
U1
7
5
Vcc
Gambar 2.1 Konfigurasi penguat inverting
2.2 Penjumlah Tegangan
Rangkaian penjumlah berfungsi untuk menggabungkan dua sinyal analog
atau lebih menjadi satu keluaran. Konfigurasi penjumlah tegangan seperti pada
gambar 2.2.
RF
R1
Vee
V1
R2
4
8
1
2 -
V2 R3 6
Vo
3 +
V3 Rn U1
7
5
Vn
Vcc
Gambar 2.2 Konfigurasi penjumlah tegangan
Rangkaian penjumlah mengkombinasikan semua sinyal yang diperkuat menjadi
sebuah keluaran tunggal, ditentukan oleh :
⎛R ⎞ ⎛R ⎞ ⎛R ⎞ ⎛R ⎞
VO = − ⎜⎜ F × V1 ⎟⎟ − ⎜⎜ F × V2 ⎟⎟ − ⎜⎜ F × V3 ⎟⎟ − ... − ⎜⎜ F × Vn ⎟⎟ ……… (2.2)
⎝ R1 ⎠ ⎝ R2 ⎠ ⎝ R3 ⎠ ⎝ Rn ⎠
Dengan menggunakan harga R yang sama maka :
VO = − V1 − V2 − V3 − ... − Vn ……………………………………….… (2.3)
VO = − (V1 + V2 + V3 + ... + Vn ) ……………………………………….. (2.4)

8
2.3 Buffer Tegangan
Buffer tegangan berfungsi untuk mempertahankan tegangan output agar tidak
terbebani oleh beban. Tegangan keluaran yang dihasilkan rangkaian buffer tegangan
persis sama dengan tegangan masukan. Konfigurasi buffer tegangan seperti pada
gambar 2.3.
Vee
4
8
1
2 -
6
3 +
Vo
CA3130
Vin
U1
7
5
Vcc
Gambar 2.3 Konfigurasi buffer tegangan
2.4 Rangkaian Pembagi tegangan
Rangkaian pembagi tegangan merupakan rangkaian yang terdiri dari
resistor yang dikonfigurasikan seperti pada gambar 2.4. Vout ditentukan dengan
persamaan 2.5
R2
Vout = xVCC …………………………………………….….. (2.5)
R 1 + R2
VCC
R1
Vout
R2
Gambar 2.4 Konfigurasi pembagi tegangan

9
2.5 Pengubah Analog Ke Digital (ADC)
Pengubah analog ke digital, berfungsi untuk mengubah tegangan
analog menjadi data digital. Data digital yang dihasilkan dinyatakan dalam kode biner
dengan menggunakan dua nilai tegangan yaitu 5 volt, yang dinyatakan dengan
lambang ‘1’ dan 0 volt dengan lambang ‘0’. Bilangan biner merupakan kombinasi
dari sederetan kode 1 dan 0.
Frekuensi clock dengan konfigurasi typical pada datasheet seperti Gambar
2.5 adalah
1
f clock = …………………………………………………... (2.6)
1,1 x R x C
Resolusi ADC dinyatakan dengan persamaan 2.6.
Vref( + ) - Vref(-)
Resolusi = …………………………………………... (2.7)
255
Resolusi = Ketelitian ADC
Vref(+) = Referensi tegangan atas
Vref(-) = Referensi tegangan bawah
Vreff
Sesuai dengan penggunaan typical ADC 0804 dengan =2,5 volt, maka
2
5-0
Resolusi =
255
Resolusi = 19,6 mv
Perubahan ADC tiap bit dinyatakan dengan persamaan 2.8.
Tegangan konversi
Level = …………………………………………. (2.8)
Resolusi ADC
Tegangan konfersi = Level x Resousi ADC ……………………….. (2.9)

10
VCC = 5 v olt
U5
20
Data Digital
6 18
VC C /VR EF
Input +IN DB0
9 17
Rev erensi VREF/2 DB1 16
C R DB2 15
150pF 10K DB3 14
19 DB4 13
CLKR DB5 12
4 DB6 11
0 CLKIN DB7
1
Mengaktif kan ADC CS
2
SOC RD
3
Baca ADC WR
5
GN D
GN D
EOC INTR
-IN
ADC0804/SO
10
8
7
0
Gambar 2.5 Konfigurasi typical ADC 0804
2.6 Modem FSK
Modem ( modulator demodulator) digunakan untuk mengubah bit-bit digital
menjadi frekuensi-frekuensi tertentu supaya dapat dimodulasikan dengan gelombang
radio, sehingga dapat ditransmisikan melalui gelombang radio untuk jarak jauh. Pada
penelitian ini menggunakan modem FSK (Frequency Shift Keying), yakni modem
yang menggunakan frekuensi tertentu untuk menyandikan nilai bit-bit digital. Bit 1
yang disebut frekunsi mark dan bit 0 yang disebut dengan frekuensi space.. Seperti
terlihat pada gambar 2.6. FSK sendiri hanya efektif bila di pakai pada frekuensi audio.
11
Gambar 2.6 Sistem modulasi FSK biner
2.6.1 Modulator FSK XR-2206
Untuk menyandikan data digital menjadi frekunsi tertentu digunakan suatu
rangkaian demodulator FSK. Pada rangkaian modulator FSK XR-2206, seprti yang
ditunjukan pada gambar 2.7 untuk menghitung f1 yang disebut dengan frekuensi mark
dan f2 yang disebut dengan frekuensi space, di rumuskan :
1
f1 = ………………………………………………...... (2,10)
R1 × C
1
f2 = ………………………………………………….. (2,11)
R2 × C
Gambar 2.7 Sinusoidal FSK Generator

12
2.6.2 Demodulator FSK XR-2211
Untuk mendapatkan data yang telah di modulasi oleh modulator FSK menjadi
data kembali seperti semula, maka dibutuhkan rangkaian demodulator FSK. Untuk
dipakai sebagai demodulator FSK, diperlukan beberapa komponen tambahan, seperti
yang ditunjukkan pada gambar 2.8. Adapun langkah-langkah untuk mencari
komponen tersebut adalah sebagai berikut :
1. Hitung frekuensi tengah PLL, yang dirumuskan :
fo = f 1 × f 2 ……………………………………………… (2.12)
Dimana : f1 = ferkuensi mark
f2 = frekuensi space
2. tentukan nilai timing resistor RO, nilainya harus berada diantara 10 KΩ sampai
100 KΩ. Disarankan nilai RO = 20 KΩ. Nilai akhir RO biasanya hasil seri
dengan potensiometer RX untuk memperbaiki hasil VCO.
RX
RO = RO + ……………………………..………………. (2.13)
2
3. Hitung nilai CO dengan rumusan :
1
CO = ………………………………………………... (2.14)
RO × f o
4. Hitung nilai R1 , untuk menentukan bandwidth, yang dirumuskan :
RO × f O
R1 = × 2 …………………………………………... (2.15)
( f1 − f 2 )
5. Hitung nilai C1, untuk menentukan loop damping
1250 × C O
C1 = ……………………………………………..… (2.16)
R1 × ς 2
Direkomendasikan nilai ς = 0,5

13
6. Hitung kapasitor filter data CF,
RF = 5 x R1 ……………………………………………..……. (2.17)
RB = 5 x RF ………………………………………………….. (2.18)
(R F + R 1 ) × R B
RSUM = ……………………………………… (2.19)
(R 1 + R F + R B )
0,25
CF = ……………………………………. (2.20)
(R SUM × Baud Rate )
Gambar 2.8 Rangkaian demodulator FSK
Tracking bandwidth (frekuensi maksimum dan minimum yang masih
diperkenankan supaya frekuensi dapat di demodulasi ulang) seperti pada gambar 2.9,
mempunyai rumusan ;
Δf
Bandwidth, ± = . ………………………………………... (2.21)
f0
Δf R
= 0 …………………………………………………… . (2.22)
f0 R1
14
Gambar 2.9 Tracking Bandwidth XR-2211
Untuk menetapkan frekuensi mark dan space berdasar baud rate yang
digunakan, standar pada tabel 2.1 dapat digunakan sebagai acuan, dimana pada
penelitian ini di pakai standar BELL 202.
Tabel 2.1 Standar FSK
Frekuensi yang di pakai

Standar Baud Rate
F Mark F Space
1200 bps 1300 Hz 2100 Hz
CCIT.V23 600 bps 1300 Hz 1700 Hz
75 bps 390 Hz 450 Hz
1200 bps 1200 Hz 2200 Hz
BELL 202 150 bps 387 Hz 487 Hz
5 bps 387 Hz 0 Hz
2.7 Mikrokontroler AT89S51
Mikrokontroler AT89S51 merupakan mikrokontroler yang kompatibel
dengan Mikrokontroler 8051 buatan Intel dan mendukung komunikasi serial

15
2.7.1 Komunikasi Serial
Ada dua macam cara pengiriman (transmisi) secara serial yaitu komunikasi
sinkron dan komunikasi asinkron. Pada komunikasi sinkron sinyal detak dikirim
bersama-sama dengan data serial. Selanjutnya dalam transmisi data serial secara
asinkron, detak tidak dikirim bersama data serial.
Port serial pada AT89S51 bersifat duplex penuh atau full-duplex, artinya
port serial bisa menerima dan mengirim data pada waktu bersamaan. Port serial
memiliki penyangga penerima yaitu serial buffer (SBUF). Port serial dapat
menerima byte yang kedua sebelum byte yang pertama dibaca oleh register
penerima, melalui register SBUF. SBUF selalu berhubungan dengan akumulator
dalam mengisi dan menerima data.
Port serial pada AT89S51 bisa digunakan dalam empat mode kerja. Dari ke-
empat mode tersebut, 1 mode diantaranya bekerja secara sinkron dan tiga mode
lainnya bekerja secara asinkron. Semua mode dapat diatur melalui register kontrol
serial (SCON). Keempat mode kerja tersebut adalah :
Mode 0 Mode ini bekerja secara sinkron, data serial dikirim dan diterima melalui
kaki P3.0 (RxD), sedangkan kaki P3.1 (TxD) dipakai untuk menyalurkan
detak pendorong data serial yang dibangkitkan AT89S51. Data
dikirim/diterima 8 bit sekaligus, dimulai dari bit yang bobotnya paling
kecil atau LSB (bit 0), diakhiri dengan bit yang bobotnya paling besar
atau MSB (bit 7). Kecepatan pengiriman data (baudrate) adalah 1/12
frekuensi kristal yang digunakan.
Mode 1 Pada mode ini, data dikirim melalui kaki P3.1 (TxD) dan diterima
melalui kaki P3.0 (RxD) secara sinkron (begitu juga mode 2 dan 3).
Pada mode ini, data dikirim/diterima 10 bit sekaligus, diawali dengan 1

16
bit start, disusul 8 bit data yang dimulai dari bit yang bobotnya paling
kecil (bit 0), diakhiri dengan 1 bit stop. Pada AT89S51 yang berfungsi
sebagai penerima bit stop adalah RB8 dalam register Serial Control
(SCON). Kecepatan pengiriman data (baudrate) bisa diatur sesuai
dengan keperluan. Mode inilah (mode 2 dan juga mode 3) yang umum
dikenal sebagai UART atau Universal Asynchronous
Receiver/Trasmitter.
Mode 2 Data dikirim 11 bit, diawali dengan 1 bit start, kemudian 8 bit data. Bit
ke-9 yang dapat diatur lebih lanjut dan diakhiri dengan 1 bit stop. Pada
AT89S51 yang berfungsi sebagai pengirim bit 9 tersebut berasal dari bit
TB8 dalam register SCON. Pada AT89S51 yang berfungsi sebagai
penerima bit 9 ditampung pada bit RB8 dalam register SCON,
sedangkan bit stop diabaikan dan tidak ditampung. Kecepatan
pengiriman data (baudrate) bisa dipilih antara 1/32 atau 1/64 frekuensi
kristal yang digunakan.
Mode 3 Mode ini sama dengan mode 2, hanya saja kecepatan pengiriman data
(baudrate) bisa diatur sesuai keperluan, seperti halnya pada mode
asinkron (mode 1, mode 2, mode 3).
Nilai baudrate pada komunikasi serial ditentukan oleh kristal yang
digunakan, karena berpengaruh pada jumlah limpahan timer. Perhitungan baudrate
sesuai dengan persamaan 2.1.
2SMOD
baudrate = × Laju Limpahan timer 1 ………………….… (2.23)
32
17
2.7.2 Reset
Gambar 2.10 menunjukkan konfigurasi tombol reset. Reset akan aktif bila pin
RST diberikan logika high selama 2 µs.
VCC
RST
R C
0
1 2
SW1
Gambar 2.10 Konfigurasi tombol reset
Bila tombol reset tidak ditekan, maka pin RST akan mendapat input logika
low, sehingga mikrokontroler akan bekerja normal. Resistor dan kapasitor digunakan
untuk memperoleh waktu pengosongan kapasitor. Waktu pengosongan kapasitor
dapat dihitung sebagai:
T = R × C ……………………………………………….…………...… (2.24)
2.8 Pengubah Level TTL ke Level Serial
Standar komunikasi serial yang banyak digunakan adalah standar RS232
yang dikembangkan oleh Electronic Industry Association and the
Telecommunications Industry Association (EIA/TIA) yang pertama kali
dipublikasikan pada tahun 1962. Ini terjadi jauh sebelum IC TTL populer sehingga
sinyal ini tidak ada hubungan sama sekali dengan level tegangan IC TTL. Standar
ini hanya menyangkut komunikasi data antara komputer DTE dengan alat-alat
pelengkap komputer DCE. Standar RS232 inilah yang biasa digunakan pada port
serial IBM kompatibel.

18
Standar sinyal serial RS232 memiliki ketentuan level tegangan sebagai
berikut:
1. Logika ‘1’ disebut ‘mark’ terletak antara -3 Volt hingga -25 Volt.
1. Logika ‘0’ disebut ‘space’ terletak antara +3 Volt hingga +25 Volt
2. Daerah tegangan antara -3 Volt hingga +3 Volt adalah invalid level, yaitu
daerah tegangan yang tidak memiliki level logika pasti sehingga harus
dihindari. Demikian juga, level tegangan lebih negatif dari -25 Volt atau
lebih positif dari +25 Volt juga harus dihindari karena tegangan tersebut
dapat merusak line driver pada saluran RS232.
Gambar 2.11 adalah contoh level tegangan RS232 pada pengiriman huruf
‘A’ dalam format ASCII tanpa bit paritas pada level TTL dan level RS232.
Rangkaian pengubah level tegangan TTL menjadi level tegangan RS232
menggunakan rangkaian voltage doubler atau rangkaian pengganda tegangan dan
rangkaian voltage inverter atau rangkaian pembalik tegangan.
Level TTL
Level RS232
Gambar 2.11 Level tegangan TTL dan RS232 pada pengiriman
huruf ‘A’ tanpa bit paritas.
2.9 Konfigurasi Port Serial

Gambar 2.12 merupakan gambar konektor port serial DB-9 pada bagian
belakang CPU. Pada komputer IBM PC kompatibel terdapat konektor serial DB-9
yang dinamai COM1 dan atau COM2. Standar RS232 menyangkut komunikasi data
19
antara komputer (Data Terminal Equipment/DTE) dengan alat-alat pelengkap
komputer (Data Circuit-Terminating Equipment/DCE).
Gambar 2.12 Konektor DB-9
Tabel 2.2 menunjukkan konfigurasi kaki-kaki dan nama sinyal konektor
serial DB-9. Keterangan mengenai fungsi saluran RS 232 pada konektor DB-9
adalah sebagai berikut :
• Received Line Signal Detect. Dengan saluran ini DCE memberitahukan ke
DTE bahwa pada terminal input ada data masuk.
• Received Data, digunakan DTE menerima data dari DCE.
• Transmit Data, digunakan DTE mengirim data ke DCE.
• Data Terminal Ready, pada saluran ini DTE memberitahukan terminal
siap.
• Signal Ground, saluran ground.
• Ring Indikator. Pada saluran ini DCE memberitahukan ke DTE bahwa
sebuah stasiun menghendaki hubungan dengannya.
• Clear To Send. Dengan saluran ini DCE memberitahukan bahwa DTE
memulai mengirim data.

20
• Request To Send. Dengan saluran ini DCE diminta mengirim data oleh
DTE.
• DCE Ready. Sinyal aktif pada saluran ini menunjukkan bahwa DCE sudah
siap.
Untuk dapat menggunakan port serial perlu diketahui alamatnya. Tersedia
dua port serial pada CPU, yaitu COM1 dan COM2. Base address COM1 adalah
1016 (3F8H0) dan COM2 adalah 760 (2F8h). Alamat tersebut adalah alamat yang
biasa digunakan. Tepatnya pada peta memori tempat menyimpan alamat tersebut,
yaitu memori 0000 0400H untuk base address COM1 dan memori 0000 0402H
untuk base address COM2.
Tabel 2.2 Konfigurasi kaki-kaki DB-9
Nomor Nama Sinyal Direction Keterangan

1 DCD In Data carrier detect/Received Line
2 RxD In Received Data
3 TxD Out Transmit Data
4 DTR Out Data Terminal Ready
5 GND - Ground
6 DSR In Data Set Ready
7 RST Out Request to Send
8 CTS In Clear to Send
9 RI In Ring Indikator
2.10 Motor DC
Motor DC adalah motor yang memiliki dua bagian dasar, bagian yang berputar
di sebut rotor dan bagian yang tidak berputar di sebut stator. Motor DC bekerja
berdasarkan medan magnet yang dihasilkan oleh kumparan yang terdapat pada rotor.
Semakin besar arus yang melalui kumparan motor, maka semakin besar cepat putaran
21
motor. Arah putaran dapat dikendalikan dengan mengatur arah putaran arus yang
melalui kumparan.
BAB III
PERANCANGAN
Telemetri ketinggian air sebagai pengatur model pintu air terdiri dari dua
bagian, yakni bagian pengirim dan penerima. Sehingga di dalam perancangan
dibutuhkan hal-hal sebagai berikut, di bagian pengirim terdiri dari sensor ketinggian
air, pengkondisi sinyal, pengubah analog ke digital (ADC), mikrokontroler sebagai
pengubah data pararel menjadi data digital, modulator FSK, dan pemancar FM seperti
yang ditunjukkan pada gambar 3.1. sedangkan pada bagian penerima terdiri dari
penerima FM, RS 232, PC, mikrokontroler sebagai pengatur arah putaran motor DC,
dan motor DC seperti yang ditunjukkan pada gambar 3.2. Peletakan sensor seperti
pada gambar 3.3.
Sensor Pengkondisi Modulator Pemancar

ADC Mikrokontroler
Ketinggian air Sinyal FSK FM
Gambar 3.1 Blok diagram pengirim
Pintu
Motor DC
Air
Demodulator
Penerima FM RS 232 PC Mikrokontroler
FSK
Buzer
Gambar 3.2 Blok diagram penerima

Ruang
kontrol Antena penerima
Antena Pemancar
Pintu air
Sensor
Ketinggian air
DAM AIR Aliran air
Model Sungai
Gambar 3.3 Skema telemetri ketinggian air sebagai pengatur model pintu air
23
3.1 Sensor Ketinggian Air Sungai
Untuk mengetahui perubahan ketinggian air digunakan potensio multi turn
dengan diberi roda gigi. Potensio multi turn dirangkai sebagai rangkaian pembagi
tegangan, seperti pada gambar 3.4. Didalam sungai terdapat sebuah pelampung yang
dihubungkan dengan batang bergerigi yang berfungsi untuk memutar roda gigi pada
potensio mulit turn. Sehingga potensio akan berputar mengikuti perubahan ketinggian
air sungai yang akan di ukur. Seperti terlihat pada gambar 3.5
VCC
Vout
POT
Gambar 3.4 Potensio sebagai rangkaian pembagi tegangan
Roda gigi pemutar

Potensio meter
tuas bergerigi naik turun
penggerak roda gigi
pelampung
model sungai
Gambar 3.5 Rancangan sensor ketinggian air sungai
Karena yang dikontrol merupakan model pintu air, maka dalam perancangan
ini dirancang dengan skala 1 : 10, dan sensor dirancang untuk kedalaman sungai 20
cm.
24
3.2 Potensio Multi Turn
Potensio multi turn dalam perancangan ini mempunyai hambatan total 31
KΩ dengan jumlah putaran sebanyak 38 putaran, dengan nilai hambatan sebesar
815,79 Ω untuk satu putaran. Gigi roda yang akan dipakai untuk memutar potensio
memiliki keliling 3,1 cm dan jumlah gigi 10 gigi. Karena kedalaman maksimum air
sungai yang akan diukur 20 cm maka banyak putaran yang diperlukan potensiometer
sebesar :
20 cm
Banyak putaran =
3,1 cm
= 6,45
≈ 6,5 putaran
Dengan besar hambatan maksimum yang digunakan = 6,5 x 815,79 Ω
= 5302,63 Ω
Karena perubahan hambatan pada potensiometer akan mulai stabil pada
hambatan 5 KΩ, maka sensor diset pada hambatan awal bukan 0 Ω tetapi pada 5
KΩ. sehingga resistansi yang dipakai pada potensiometer adalah antara 5 KΩ sampai
10302,63 Ω. Bila potensio diberi masukan tegangan sebesar 5 Volt maka dapat
dihitung tegangan Vo minimum dan Vo maksimum, mengacu pada persamaan 2.5 :
5000 10302,63
Vo min = ×5 Vo max = ×5
31000 31000
= 0,806 Volt = 1,662 Volt
Bila ketinggian air yang akan ditampilkan mempunyai interval perubahan tiap 1 cm,
maka setiap intervalnya potensio multi turn akan menghasilkan perubahan tegangan
sebesar
( 1,662 V - 0,806 V)
V interval = × 1 cm
20 cm
25
= 0,0428 V
Dengan jumlah total interval 20
3.3 Pengkondisi Sinyal
Pengkondisi tegangan ini diperlukan supaya pengubah ADC mengenali
perubahan ketinggian air sungai setiap 1 cm atau setiap 42,8 mV. Pengubah ADC
0804 mempunyai resolusi 19,6 mV pada tegangan catuan 5 V seperti yang dijelaskan
pada BAB II, atau dengan kata lain output ADC 0804 akan berubah nilainya bila ada
perubahan tegangan sebesar 19,6 mV pada kaki inputnya. Berdasar pada karakter
yang dapat diterima program Visual Basic yakni karakter yang mewakili bilangan
biner 32 sampai 127, maka pada pengkondisi sinyal dirancang setiap kenaikan /
penurunan air sungai 1 cm maka bilangan biner output ADC akan naik / turun 4.
Karena ketinggian maksimum air sungai adalah 20 cm dan sensor dirancang untuk
perubahan ketinggian air sungai tiap 1 cm maka total interval ketinggian air sungai
adalah 20 dan total interval ADC yang diperlukan adalah 20 x 4 = 80 interval.
Bila ketinggian air 0 cm diwakili bilangan biner 33, maka untuk ketinggian
maksimum air sungai sebesar 20 cm diwakili bilangn biner 113. Bila ADC
mempunyai resolusi 19,6 mV maka besarnya tegangan yang dibutuhkan ADC untuk
menghasilkan nilai biner tersebut menurut persamaan 2.9 adalah sebagai berikut :
Vin ADC = Level x Resolusi ADC
Untuk bilangan biner 33 : Untuk bilangn biner 113 :
Vin ADC = 33 x 19,6 mV Vin ADC = 113 x 19,6 mV
Vin ADC = 0,647 V Vin ADC = 2,215 V

26
Sehingga interval ADC adalah :
Interval ADC =
(2.215 V - 0.647 V ) × 4
80
= 0,0784 V
Hubungan tegangan antara output sensor yang harus disesuaikan dengan ADC adalah
seperti pada tabel 3.1
Tabel 3.1 Penskalaan tegangan
Ketinggian Sensor ketinggian air Tegangan input ADC Bilangan Biner

air sungai (Vo) (Vi) ADC
0 cm 0,806 Volt 0,647 Volt 00100001b
20 cm 1,662 Volt 2,215 Volt 01110001b
Sesuai dengan tabel 3.1 bentuk persamaannya yaitu :
Vi = b.Vo + a ……………………………………. (3.1)
a = bilangan penjumlah tegangan input
b = bilangan penyesuai interval
Vi = tegangan yang dipakai untuk input ADC 0804
Vo = tegangan hasil dari sensor ketinggian air
Dimana interval ADC 0804 = 78 mV dan interval sensor ketinggian air = 42,8
mV, maka supaya intervalnya menjadi sama di pakai persamaan 3.2 :
Interval ADC
b= ………………………… (3.2)
Interval sensor air
78,4 mV
b=
42,8 mV
b = 1,832
maka persamaan 3.1 menjadi :
Vi = ( 1,832 x Vo ) + a ………………………….. (3.3)

27
Untuk mencari nilai a maka di ambil salah satu data yakni Vi = 0,647 Volt
0,647 = (1,832 x 0,806) + a
a = - 0,829
sehingga persamaannya menjadi :
Vi = ( 1,832 x Vo ) – 0,829 ……………………… (3.4)
Untuk memudahkan dalam perancangan maka persamaan 3.3 menjadi :
Vi = -((- 1,832 x Vo) + ( 0,829)) ………………….… (3.5)
Pada perancangan pengkondisi sinyal op-amp yang dipakai adalah tipe CA3140
3.3.1 Pembagi Tegangan
Untuk mendapatkan tegangan penjumlah sesuai dengan persamaan 3.5, di
pakai rangkaian pembagi tegangan, sehingga nilai resistor dapat di hitung dengan
mengacu pada persamaan 2.5 dan gambar 2.4.
Untuk mendapatkan Vref sebesar 0,829 Volt pada tegangan catuan 5 Volt maka nilai
R1 dan R2 :
R2
Vreff = × Vcc
R1 + R 2
R2
0,829 Volt = × (5 Volt)
R1 + R 2
R2
0,1658 =
R1 + R 2
Bila nilai R2 ditentukan 1 KΩ, maka nilai R1 adalah 5,031 KΩ. Karena nilai R1 tidak
ada dipasaran maka di pakai potensiometer dengan nilai 10 KΩ, sehingga
rangkaiannya menjadi seperti gambar 3.6

28
VCC = 5 V
R1
5.031K
Vref = 0.829 V
R2
1K
Gambar 3.6 Pembagi tegangan menggunakan potensiometer
3.3.2 Buffer Tegangan Referensi
Supaya tidak terbebani maka tegangan Vref sebesar 0,829 V perlu di buffer.
Konfigurasi buffer tegangan seperti pada gambar 3.7, dimana nilai V1 = Vref
Vcc = 5 V
Vee = -5V
5.031 k
R1
4
8
1
2 -
6
3 +
V1
CA3130
U1
7
5
R2
1K Vcc = 5V
Gambar 3.7 Buffer tegangan referensi
3.3.3 Penguat Inverting Vsensor
Menurut persamaan 3.5 Vsensor perlu dikalikan dengan – 0,832, maka
digunakan rangkaian penguat inverting dengan penguatan 0,832. mengacu pada
persamaan 2.1 dan gambar 3.8 maka nilai R3 dan R4 dapat dicari yakni :
V2 = - Acl x Vsensor ……………………………… (3.6)
V2 = - 1,832 x Vsensor
29
R4
= 1,832
R3
Bila R3 ditentukan 10 KΩ maka nilai R4 =18.32 KΩ

R4
18.32 k
Vee = -5V
4
8
1
R3
2 -
6
V2
10K 3 +
Vsensor
U1
7
5
Vcc = 5V
Gambar 3.8 Penguat Inverting Vsensor
3.3.4 Rangkaian Penjumlah Tegangan
Mengacu pada persamaan 3.5 diperlukan rangkaian penjumlah, sesuai
dengan gambar 3.8 dan persamaan 2.2 :
R7 R
V3 = - ( V1 + 7 V2 )
R5 R6
Supaya didapat nilai V3 = - (V1 + V2), maka nilai R5 = R6 = R7 ditentukan sebesar
10 KΩ
R7
10k
Vee = -5V
R5
4
8
1
10k
V1
2 -
6
R6 V3
3 +
CA3130
10k U1
7
5
V2
Vcc = 5V
Gambar 3.10 Rangkaian Penjumlah V1 dan V2

30
3.4 Pengubah Analog ke Digital (ADC)
ADC pada perancangan ini digunakan untuk mengubah masukan
analog keluaran pengkondisi sinyal menjadi data digital 8 bit. Gambar 3.10
menunjukkan konfigurasi rangkaian ADC 0804 dengan mode operasi Hand-Shaking,
yakni dengan menghubungkan pin CS ke ground dan pin kontrol yang lain ke
mikrokontroler AT89S51. Bila menggunakan R10 =10 KΩ dan C1 = 150 pF seperti
yang digunakan dalam data sheet, maka sesuai persamaan 2.6 fclock dapat dihitung
besarnya :
1
f clock =
1,1 × R 10 × C1
1
fclock =
1,1 × 10 KΩ × 150 pF
fclock = 606 KHz
VCC = 5V
2.2K 2.2K
U3
20
P1 mikronkontroler
9 18
VC C /VR EF
VREF/2 DB0 17
1 DB1 16
CS DB2 15
DB3
8 bit data
14 digital
6 DB4 13
Vout pengkondisi sinyal +IN DB5 12
19 DB6 11
CLKR DB7
C1 R10 4
CLKIN
150 pf 10K 2
GN D
GN D
3 RD 5
-IN
WR INTR EOC
SOC
10
ADC0804
7
8
Baca ADC
Gambar 3.10 Konfigurasi ADC 0804
Input ADC berupa tegangan DC yang berasal dari pengkondisi sinyal,
dimana nilainya berkisar antara 0,647 Volt sampai dengan 2,215 Volt. Kontrol-
kontrol ADC yang meliputi RD, WR dan INT akan aktif bila diberikan logika
rendah. Pin-pin kontrol di hubungkan dengan Mikrokontroler AT89S51 pada

31
kaki P2.2, P2.1 dan P2.0, seperti terlihat pada Gambar 3.12. Output ADC yang
berupa data digital dihubungkan dengan mikrokontroler pada port 1. Kaki DB7
pada ADC 0804 dihubungkan pada kaki P1.7 sebagai MSB (Most Significant Bit)
dan pada kaki DB0 sebagai LSB (Least Significant Bit) di hubungkan dengan kaki
P1.0 pada mikrokontroler. Vreff didapat dari dua buah resistor bernilai 2,2 kΩ
yang dirangkai pembagi tegangan Vcc.
3.5 Konfigurasi Mikrokontroler AT89S51 Sebagai Pengubah Data
Pararel 8 Bit menjadi Data Serial
Untuk mengubah data hasil ADC 0804 yang berupa data pararel 8 bit
menjadi data serial digunakan Mikrokontroler AT89S51 yang dikonfigurasi seperti
Gambar 3.10. Pin reset dihubungkan dengan saklar tekan, sebuah hambatan dan
kapasitor.
VCC
U1
40
31
39 21
EA/VPP
VCC
P0.0/AD0 P2.0/A8 EOC

38 22
P0.1/AD1 P2.1/A9 BACA ADC
37 23
P0.2/AD2 P2.2/A10 SOC
36 24
35 P0.3/AD3 P2.3/A11 25
34 P0.4/AD4 P2.4/A12 26
33 P0.5/AD5 P2.5/A13 27
32 P0.6/AD6 P2.6/A14 28
P0.7/AD7 P2.7/A15
ADC 0804
1 10
2 P1.0 P3.0/RXD 11
P1.1 P3.1/TXD DATA SERIAL OUT
3 12
4 P1.2 P3.2/INTO 13
5 P1.3 P3.3/INT1 14
6 P1.4 P3.4/TO 15
C3 7 P1.5 P3.5/T1 16
30 pF 8 P1.6 P3.6/WR 17
P1.7 P3.7/RD
19 29
18 XTAL1 PSEN
11.0592Mhz 9 XTAL2 30
RST ALE/PROG
GND
C4
30 pF
20
AT89C51
C2 VCC
R11 10uF
10 K
SW PUSHBUTTON
SW1
Gambar 3.11 Pengubah data pararel menjadi serial

Menggunakan AT 89S51
32
Pada perancangan, waktu pengosongan dipilih sebesar 100 ms dengan asumsi
waktu reset telah lebih dari 2 µs, sesuai dengan persamaan 2.22. Bila nilai R11
dipilih 10 kΩ, maka nilai C2 adalah
0,1 = 10.000 × C 2
C2 = 10 uF
Kristal sebagai sumber detak (clock) dipilih sebesar 11,0592 MHz agar dalam
perhitungan baud rate dapat mudah dihitung yang sesuai dengan persamaan 2.21. Bila
11,0592 MHz
menggunakan kristal 11,0592 MHz, maka timer 1 didetak dengan laju
12
yaitu sebesar 921,6 kHz. Pada persamaan 2.21 timer melimpah dengan laju limpahan
sebesar 32 x Baud rate. Bila menggunakan kristal 11,0592 Mhz didapatkan hasil
limpahan timer secara bulat. Jika menggunakan baud rate 1200 bps, maka laju
limpahan timer 1 sebesar:
Laju Limpahan timer1 = 32 × 1200

Laju Limpahan timer1 = 38400kali/detik
Limpahan timer dengan kristal 11,0592 MHz membutuhkan detakan sebesar:
Waktu Instruksi
detak =
Laju Limpahan timer1
921600
detak =
38400
detak = 24 kali
Pin EA/VPP dihubungkan dengan sumber VCC +5 Volt agar mikrokontroler
mengakses program internal dari PEROM. Jika dihubungkan dengan ground, maka
mikrokontroler akan mengeksekusi program eksternal. PIN PSEN dan ALE/PROG
tidak digunakan.
33
Port 3, yakni P3.1 sebagai kaki TxD akan dikonfigurasikan sebagai penghasil
output data serial secara asinkron yang akan di modulasi oleh XR-2206. Pin kontrol
untuk ADC 0804 dihubungkan dengan kaki pada port 2.
3.6 Pemprograman Mikrokontroler Pengubah Data Pararel Menjadi
Data Serial
Pemrograman mikrokontroler digunakan untuk membaca data dari ADC. Data
dari ADC berupa data paralel yang kemudian diolah menjadi data serial dan
dikirimkan ke modulator FSK untuk selanjutnya ditransmisikan.
Adapun program yang digunakan mikrokontroler AT 89S51 dalam mengubah
data pararel menjadi data serial terdiri dari beberapa langkah yakni : pembacaan
ADC, dan pengiriman data serial, seperti yang ditunjukan gambar 3.12.
MULAI
INISIALISASI
PORT DAN
AKTIFKAN
KONTROL
ADC
BACA ADC
KIRIM DATA
SELESAI
Gambar 3.12 Diagram Alir Pemprograman Mikrokontroler

34
Mula-mula program akan melakukan inisialisasi antara lain
1. Melakukan set pin yang digunakan sebagai kontrol ADC, yaitu pin P2.2, P2.1 dan
P2.0.
2. Melakukan pengaturan timer, sebagai penentu baudrate komunikasi serial, yaitu
1200 bit per second.
3.6.1 Rutin Baca ADC
Dalam melakukan konversi data analog menjadi digital, ADC 0804
membutuhkan beberapa kontrol. Adapun kontrol ADC yang diperlukan antara lain:
1. Start of Convertion (SOC), ADC mulai konversi, bila pin SOC di berikan logika
rendah.
2. End of Convertion (EOC), pemberitahuan keluar ADC, bahwa ADC telah selesai
mengkonversi. Tanda EOC merupakan logika rendah.
3. Read (RD), proses pengambilan data pada ADC.
Pertama rutin baca ADC dimulai dengan mengirimkan sinyal SOC, dengan
memberikan logika rendah pada pin SOC agar ADC mulai mengkonversi. Proses
kedua yaitu menunggu sinyal balasan dari ADC yang berupa logika rendah pada pin
EOC, yang berarti ADC selesai konversi. Proses ketiga yaitu dikirimkan sinyal RD,
agar data digital dapat keluar melalui output ADC menuju port 1.
Proses pembacaan ADC diteruskan dengan menyalin isi port 1 ke
akumulator yang nantinya akan di rubah menjadi data serial. Pengambilan data akan
dilakukan sebanyak dua kali tiap detiknya dengan cara memberikan tunda waktu
selama 0,5 detik setiap akan mengirim sinyal SOC. Gambar 3.13 merupakan gambar
diagram alir pembacaan ADC.

35
MULAI
KIRIM SINYAL
SOC
SINYAL EOC TUNGGU ADA

DITERIMA ? SINYAL EOC
TIDAK
YA
KIRIM SINYAL
BACA (RD)
BACA ADC DAN

SIMPAN KE ACC
SELESAI
Gambar 3.13 Diagram alir pembacaan ADC
3.6.2 Kirim Data
Pengiriman data serial melibatkan register serial buffer dan
akumulator. Dimana data pada akumulator akan disalin ke serial buffer (Sbuf).
Pengiriman data serial dimulai dengan mengirim bit start, satu bit kemudian data pada
akumualor akan di kirim dengan cara mengeser kedelapan bit data di mulai dari LSB
sampai MSB, setelah bit kedelapan (MSB) dikirimkan bit stop akan dikirim sebagai
tanda pengiriman data telah selesai.
3.7 Modulator FSK
Untuk mengirimkan bit-bit digital maka diperlukan suatu sistem modulasi
digital yang dapat mengkonversi bit-bit tersebut ke dalam bentuk sinyal analog.
Modulasi digital yang dipakai ialah sistem FSK dengan menggunakan rangkaian
36
terintegrasi tipe XR-2206, yang disarankan pada data sheet seperti pada gambar
3.14.
Bila menggunakan baud rate 1200 bps, maka frekuensi space yang dipakai
adalah 2200 Hz dan frekuensi mark adalah 1200 Hz. Dari nilai tersebut maka
berdasarkan persamaan 2.10 dan persaman 2.11 dapat dicari nilai R12 dan R13,
VCC=12V
C6
1uF
4
U1 XR 2206
1 16
Vcc
5 AMSI SY MA2 15
C5 TC1 SY MA1 14
0.022uF WAVEA2
6 13
TC2 WAVEA1
9 R16
FSK IN FSK I
7 200
TR1 2
STO FSK OUT
R13
38 K 11
8 SY NCO
BIAS
GND
TR2
MO
R12
22 K
10
12
3
1
C7
1uF 50K
2
C8
10uF
3
VCC=12V
R14 R15
5.1K 5.1K
Gambar 3.14 Modulator FSK XR-2206
Bila C5 ditentukan sebesar 0,022 uF, dengan asumsi nilai tersebut masih berada
diantara range 1000pF sampai 100 uF yang diijinkan pada data sheet. Maka nilai R12
dan R13 :
1
f1 =
R 13 × C5
37
dimana f1 adalah frekuensi mark, sehingga nilai R13 :
1
R13 =
1200 Hz × 0,022 uF
R13 = 37.878,78 Ω
Supaya ada dipasaran R13 = 38 KΩ
1
f2 =
R 12 × C5
dimana f2 adalah frekuensi space, sehingga nilai R12 :
1
R12 =
2200 Hz × 0,022 uF
R12 = 20.661,16 Ω
Supaya ada dipasaran R12 = 22 KΩ
3.8 Pemancar dan Penerima FM
Untuk transmisi jarak jauh menggunakan modulasi frekuensi (FM). Pemancar
dan Penerima FM yang digunakan dalam penelitian ini adalah rangkaian yang sudah
ada dan dijual dipasaran. Adapun pemancar FM yang dipilih adalah buatan RONICA
dengan nama Pemancar Mini FM 88-108 MHz, dan penerimanya adalah penerima
FM dengan merk dagang RONICA. Pemancar ini dapat memancarkan sampai dengan
jarak kurang lebih 10 m. Pemancar dan penerima ditala pada frekuensi 106 Mhz,
dikarenakan pada frekuensi ini tidak digunakan oleh stasiun pemancar lain sehingga
diharapkan data yang di hasilkan akan bagus. Karena berdaya rendah maka pemancar
tersebut sangat riskan terhadap derau.
3.10 Demodulator FSK
Untuk mengubah data yang diterima menjadi bentuk data semula dipakai
demodulator FSK XR-2211, dengan bentuk rangkaian seperti pada data sheet
38
(gambar 3.15). Bila menggunakan baud rate 1200 dengan frekuensi mark 1200
Hz dan frekuensi space 2200 Hz maka dapat dicari nilai komponen pendukungnya
sesuai data sheet dengan langkah sebagai berikut :
1. Sesuai dengan persamaan 2.12 nilai fo :
f O = f1 × f 2 dimana f1 adalah frekuensi mark dan f2 adalah frekuensi space
Sehinga f O = 1200 × 2200 = 1624 Hz
2. Sesuai dengan persamaan 2.13 nilai RO :
RO sebagai resisitor timing nilainya harus berada dalam range 10KΩ sampai
100KΩ. Nilai yang disarankan data sheet adalah 20KΩ. Nilai RO adalah resistor
10 KΩ di seri dengan potensiometer, yang berfungsi untuk meperbaiki hasil
keluaran VCO. Bila diseri dengan potensiometer (RX) 20 KΩ maka nilai RO:
RX
RO = RO +
2
20 KΩ
RO = 10 KΩ +
2
RO = 20 KΩ
3. Sesuai dengan persamaan 2.14 nilai CO :
1
CO =
R O + fO
1
CO =
20000 × 1624
CO = 33 nF
4. Sesuai dengan persamaan 2.15 nilai R1:
R O × fO
R1 = ×2
(f1 - f 2 )
20 × 1624
R1 = ×2
(2200 - 1200)
39
R1 = 65 KΩ
5. Sesuai dengan persamaan 2.16 nilai C1
1250 × CO
C1 = dengan ς = 0,5
R1 × ς 2
1250 × 41 nF
C1 =
65 KΩ × 0,25
C1 = 0,0024 uF
6. Sesuai dengan persamaan 2.17 nilai RF
RF = R1 x 5
RF = 65 KΩ x 5
RF = 325 KΩ
7. Sesuai dengan persamaan 2.18 nilai RB
RB = RF x 5
RB = 325 KΩ x 5
RB = 1,6 MΩ
8. Sesuai dengan persamaan 2.19 nilai RSUM
RSUM =
(R F + R1 ) × R B
(R1 + R F + R B )
RSUM =
(325KΩ + 65KΩ ) × 1.6MΩ
(65KΩ + 325KΩ + 1.6MΩ )
RSUM = 312 KΩ
9. Sesuai dengan persamaan 2.20 nilai CF
0,25
CF =
(R SUM × Baud Rate )
0,25
CF =
(312 KΩ × 1200)
CF = 0,66 nF
40
U1 XR-2211
5 14
LDOQN COMP 1
CO
2 13 33n
Siny al In INP NC
0.1u 3
LDF 10
4 TIM R
GND 0.1u
9
6 TIM C2
LDO
2
Vcc = 12 V 12 1 3
1 VREF
Vcc RO 10K
TIM C1
10K
LDO
DO
11
R1
7
8
65K
RL
DATA OUT
5.1K
RB RF
1.6M 325K
CF C1
0.66n 2.4p
Gambar 3.15 Demodulator FSK XR-2211
3.11 Mikrokontroler AT89S51 Sebagai Pengontrol Arah Putaran
Motor DC
Pada bagian penerima Mikrokontroler AT89S51 akan digunakan sebagai
pengontrol arah putaran motor DC. Mikrokontroler akan menerima instruksi dari PC
yang berupa data serial. Instruksi-instruksi yang dikirim akan diolah untuk
mengontrol apakah motor akan berputar CW atau CCW, dan juga memberikan
perintah untuk membunyikan buzer. Adapun rangkaian

2,4 nF Mikrokontroler AT89S51
sebagai pengontrol arah putaran motor DC ditunjukkan pada gambar 3.16, dan
langkah kerjanya seperti yang ditunjukkan pada gambar 3.17.

41
VCC
U1
40
31
39 21
EA/VPP
VCC
38 P0.0/AD0 P2.0/A8 22
37 P0.1/AD1 P2.1/A9 23
36 P0.2/AD2 P2.2/A10 24
35 P0.3/AD3 P2.3/A11 25
34 P0.4/AD4 P2.4/A12 26
33 P0.5/AD5 P2.5/A13 27
32 P0.6/AD6 P2.6/A14 28
P0.7/AD7 P2.7/A15
1 10
PIN 1A IC L293D P1.0 P3.0/RXD
2 11
PIN 2A IC L293D P1.1 P3.1/TXD DATA SERIAL IN DARI IC MAX232
3 12
PIN 4A IC L293D P1.2 P3.2/INTO
4 13
5 P1.3 P3.3/INT1 14
6 P1.4 P3.4/TO 15
C3 7 P1.5 P3.5/T1 16
30 pF 8 P1.6 P3.6/WR 17
P1.7 P3.7/RD
19 29
18 XTAL1 PSEN
11.0592Mhz 9 XTAL2 30
RST ALE/PROG
GND
C4
30 pF
20
AT89C51
C2 VCC
R11 10uF
10 K
SW PUSHBUTTON
SW1
Gambar 3.16 Mikrokontroler AT89S51 sebagai pengontrol arah putaran motor DC
M U LAI
IN IS IA L IS A S I
PORT
APAKAH T ID A K
R 1=1 ?
YA
B A C A IN S T R U K S I
Y A N G D IT E R IM A
In s tru k s i P u ta r YA J a d ik a n P 1 . 0 b e r lo g ik a r e n d a h
m o to r C W d a n p 1 . 1 b e r lo g ik a t in g g i
T ID A K
SELESAI
In s tru k s i P u ta r YA J a d ik a n P 1 . 0 b e r lo g ik a t in g g i
m o to r C C W d a n p 1 .1 b e r lo g ik a r e n d a h
T ID A K SELESAI
I n s t r u k s i B u n y ik a n YA
J a d ik a n P 1 . 2 b e r lo g ik a t in g g i
buzer
T ID A K
SELESAI
J a d ik a n P 1 b e r lo g ik a r e n d a h
SELESAI
Gambar 3.17 Diagram alir pengontrol arah putaran motor DC

42
3.12 Pengubah Level Tegangan TTL Menjadi Level RS232
Level tegangan dari demodulator FSK supaya dapat diterima oleh PC maka
perlu diubah level tegangannya menjadi level RS232. Pengubahan level tegangan
TTL dari Demodulator FSK menjadi tegangan dengan level RS232 dengan
menggunakan IC Max 232. Rancangan pengubah level tegangan TTL menjadi
tegangan RS232 ini mengikuti konfigurasi dari data sheet RS232. Input TTL pada
RS232 ada dua yaitu T1IN dan T2IN yang pada perancangan dipilih T2IN sebagai
input tegangan TTL dari demodulator FSK. Sedangkan output yang terhubung dengan
port serial dihubungkan dengan pin T2OUT. Sedangkan pin R2IN sebagai input dari
port serial dan R2OUT sebagai output yang terhubung ke mikrokontroler adalah pin
R2OUT. Ground rangkaian dengan ground pada bagian komputer dihubungkan agar
referensi tegangan antar kedua perangkat sama sehingga data dapat diterima dan
dikirim dengan acuan yang sama. Gambar 3.18 menunjukkan konfigurasi RS232.
VCC 5 V
C12
1uF
16
U1
2 12
VCC
9 V+ R1OUT 14
Mikrokontroler RX P1
10 R2OUT T1OUT 1
Demodulator FSK T2IN
CONNECTOR DB9
6
7 2
1 T2OUT 7
3 C+ 8 3
C13 4 C1- R2IN 8
1uf 5 C2+ 4
C2- 13 9
GN D
6 R1IN 11 5
C14 V- T1IN
1uF MAX232
15
C15
1uF
Gambar 3.18 Pengubah aras tegangan

43
Fungsi kapasitor pada rangkaian pengubah level tegangan TTL ke level
tegangan RS232 yaitu sebagai kapasitor eksternal untuk Voltage Doubler. Masing-
masing kapasitor digunakan sebagai berikut :
a. C13+ sebagai kapasitor “+” internal Voltage Doubler.
b. C13- sebagai kapasitor “-“ internal Voltage Doubler.
c. C14+ sebagai kapasitor “+” internal Voltage Inverter.
d. C14- sebagai kapasitor “-“ internal Voltage Inverter.
Nilai-nilai kapasitor yang digunakan sesuai dengan nilai-nilai yang tertera
pada data sheet MAX232. Bila nilai C13 dan C14 dinaikkan, maka akan mengurangi
nilai impedansi input rangkaian voltage doubler dan inverter. Bila nilai C12 dan C15
dinaikkan, maka akan mengurangi riak catu daya.
3.13 Pemprograman Visual Basic
Tampilan pada pemrograman Visual Basic berupa ketinggian air, batas
ketinggian air yang diatur, dan menu pelengkap program. Menu tambahan berupa
Bantuan agar pengguna dapat mengetahui cara menggunakan program melalui
menu Bantuan yang disertakan, sehingga pengguna dapat lebih mengenal program
pengendali pintu air pintu air.
Program akan melakulan inisialisasi kontrol, sesaat setelah program
dieksekusi. Inisialisasi kontrol yakni pengaturan kecepatan baud rate. Setelah
dilakukan inisialisasi, program akan menampilkan perintah untuk mengisi
ketinggian air yang akan diatur, setelah diisi program akan menampilkan penunjuk
waktu dan menu-menu pelengkap. Ketinggian air ditampilkan dengan cara
membandingkan karakter yang diterima dengan data inisialisasi, dan pengaturan
pintu air dilakukan dengan mengirimkan instruksi menggerakkan motor melalui port
44
serial, berdasarkan perbandingan antara data ketinggian yang di isi oleh user dengan
data ketinggian yang di kirim sensor.
3.13.1 Form Utama
Form utama berfungsi menampilkan ketinggian air, ketinggian yang akan diatur serta
menu-menu program. Gambar rancangan tampilan form utama seperti Gambar 3.19.
Tombol-tombol pada form utama, bila dipilih akan menuju pilihan atau eksekusi
tertentu seperti ditunjukkan pada diagram alir Gambar 3.20. Data serial ditampilkan
dalam bentuk angka yang mewakili tinggi air sungai. Form utama juga menampilkan
pesan sungai kering saat data 33 diterima dan sungai meluap saat data 113 diterima.
Rancangan pemberitahuan sungai meluap diperlihatkan pada gambar 3.21, dan
rancangan sungai kering diperlihatkan pada gambar 3.22.
Pengaturan otomatis
Bantuan INPUT USER
Ketinggian air sungai yang akan diatur XX cm

Ketinggian air sungai saat ini XX cm
HASIL SENSOR
KETINGGIAN AIR
ATUR PENGATURAN
KELUAR
KETINGGIAN MANUAL
rGambar 3.19 Rancangan form utama pengatur pintu ai

45
MULAI
Aktifkan COM, set baud rate

1200bps,
Tampilkan Atur
Ketinggian air A
Tampilkan form
utama
YA
Tombol Pengaturan
Manual ditekan
Tampilkan form
Pengaturan
Manual TIDAK
SELESAI
Tombol Atur
A
YA Ketinggian ditekan
TIDAK
Menu
Bantuan
TIDAK
Tombol Keluar
Olah Data
ditekan?
YA
A
SELESAI
Gambar 3.20 Diagram alir form utama

46
Pengaturan otomatis
Bantuan

SUNGAI MELUAP
ATUR PENGATURAN
KELUAR
KETINGGIAN MANUAL
Gambar 3.21 Pesan pemberitahu sungai meluap
Pengaturan otomatis
Bantuan

SUNGAI KERING
ATUR PENGATURAN
KELUAR
KETINGGIAN MANUAL
Gambar 3.22 Pesan pemberitahu sungai kering

47
3.13.2 Rutin Olah Data
Pada rutin olah data, data ketinggian air yang diterima dibandingkan
dengan data ketinggian air yang diisi user. Hasil data yang dibandingkan dipakai
sebagai acuan untuk mengatur pintu air, seperti pada diagram alir pada gambar 3.23.
bila ketinggian air > dari ketinggian yang isi user maka pintu air akan bergerak
menutup, dan sebaliknya bila ketinggian air < ketinggian yang di isi user maka pintu
air akan bergerak membuka sampai didapat nilai ketinggian air sesuai dengan
ketinggian yang di isi user ( bila ketinggian air = ketinggian yang di isi user). Dan bila
data yang diterima < biner dari 37 (mengindikasikan tidak ada aliran air), akan
ditampilkan pesan sungai kering. Sedang bila data yang diterima > biner dari 105
(mengindikasikan air sungai melebihi batas ketinggian), akan ditampilkan pesan
sungai meluap dan buzzer peringatan akan di bunyikan.
M u la i
YA T a m p ilk a n p e s a n S u n g a i
D a ta y a n g d i te rim a > d a ta
D a ta y a n g d i te rim a = 1 0 5 M e lu a p d a n b u n y ik a n
y a n g d i is i
buzzer
YA
P u ta r M o to r C W
T ID A K
T ID A K P u ta r M o to r C W
S e le s a i
S e le s a i
YA
D a ta y a n g d i te rim a < T a m p ilk a n p e s a n S u n g a i
D a ta y a n g d i te rim a = 3 7
d a ta y a n g d i is i K e rin g
YA
P u ta r M o to r C C W
T ID A K
T ID A K
P u ta r M o to r C C W
S e le s a i
M o to r B e r h e n ti B e rp u ta r
S e le s a i
S e le s a i
Gambar 3.23 Diagram alir olah data ketinggian air

48
3.13.3 Form Pengaturan Manual
Pengaturan manual digunakan bila user menginginkan pintu air diatur secara manual,
yakni dengan menekan tombol buka dan tutup. Seperti pada rancangan gambar 3.24.
Pengaturan Manual
Tempat menampilkan Pesan
BUKA
TUTUP Hasil sensor

ketinggian air
Pengaturan
Keluar
Otomatis
Gambar 3.24 Rancangan form pengaturan manual
Cara kerja pengaturan manual adalah sebagai berikut :
1. Bila tombol buka ditekan maka motor akan berputar CCW, dan
ditampilkan pesan “ Pintu air membuka”
2. Bila tombol tutup ditekan maka motor akan berputar CW, dan
ditampilkan pesan “ Pintu air menutup”
3. Bila tidak ditekan tombol apapun maka motor tidak akan berputar
4. Bila ketinggian air > 18 cm maka buzzer peringatan akan berbunyi,
ditampilkan pesan “ Sungai meluap” dan tombol buka tidak akan
berfungsi
49
5. Bila tombol pengaturan otomatis ditekan maka akan kembali ke
form utama.
6. Bila tombol keluar ditekan maka akan keluar dari program.
Cara kerja pengaturan manual ditunjukkan pada diagram alir gambar 3.25.
Mulai
Bunyikan buzzer dan

Ketinggian air > YA tampilkan pesan “Sungai Selesai
18 cm
meluap”
TIDAK
TIDAK Putar motor CCW

Tombol BUKA YA Ketinggian air = dan tampilkan
di tekan 18 cm pesan “Membuka
pintu air”
YA
TIDAK Selesai
Motor berhenti berputar,
bunyikan buzzer dan
tampilkan pesan “Sungai
meluap”
Selesai
Putar motor CW
Tombol TUTUP YA dan tampilkan
di tekan pesan “Menutup
pintu air”
TIDAK
Selesai
Tombol
Tampilkan form YA Pengaturan
utama otomatis
ditekan
Selesai TIDAK
Tombol Keluar
B
di tekan
YA
Selesai
Gambar 3.25 gambar diagram alir pengaturan manual

50
3.13.4 Atur Ketinggian
Tombol ‘Atur Ketinggian’ digunakan user untuk mengisi batas ketinggian
maksimum air sungai yang akan diatur. Adapun rencana tampilan ‘Atur Ketinggian’
seperti pada gambar 3.26
Masukan nilai ketinggian air sungai

yang ingin diatur
Gambar 3.26 Tampilan atur ketinggian air
3.13.6 Menu Bantuan
Menu Bantuan akan menampilkan pilihan menu ‘Tentang’, ‘Menggunakan
Program’. Bila menu ‘Tentang’ dipilih, pesan tentang pembuat program akan
ditampilkan, gambar tampilan ditunjukkan pada Gambar 3..28. Bila menu
‘Menggunakan Program’ dipilih, program akan memunculkan pesan yang
berhubungan dengan penggunaan program. Gambar tampilan pesan Menggunakan
Program ditunjukkan pada Gambar 3.29. Tombol tutup pada masing-masing menu
bila dipilih, akan menutup pesan. Diagram alir lengkap menu bantuan ditunjukkan
pada Gambar 3.27.

51
Mulai
Menu bantuan TIDAK Tam pilkan form

ditekan? Utm a
Selesai
C
YA
Tampilkan form bantuan

dengan pilihan:Tentang ,
m enggunakan program
Menggunakan TIDAK
Tentang TIDAK Program C
C
ditekan? ditekan?
YA
YA
Tam pilkan pesan

Tam pilkan pesan mengenai cara
inform asi tentang
m enggunakan program
pem buat program & & tom bol SELESAI
tom bol SELESAI
Tom bol TIDAK

Tom bol TIDAK SELESAI
SELESAI ditekan?
ditekan?
YA
YA
Tam pilkan form Utm a

Tam pilkan form Utm a
Selesai
Selesai
Gambar 3.27 Diagram alir menu bantuan
Tentang
Gambar 3.28 Rancangan tampilan menu Tentang

52
Menggunakan Program
Gambar 3.29 Rancangan tampilan menu Menggunakan Program
3.14 Pembalik Putaran Motor DC
Supaya motor dapat menggerakkan pintu air naik atau turun maka diperlukan
suatu rangkaian yang dapat membalik putaran motor. Pada perancangan ini dipakai
motor driver tipe L293D sebagai rangkaian pembalik putaran motor. Karena pada seri
L293D dioda sudah terdapat di dalam IC maka untuk dipakai sebagai pembalik
putaran motor DC maka L293D di rangkai seperti pada gambar 3.30 yang disarankan
pada data sheet dengan menghilangkan diodanya.
VCC1
U1
1 16
1,2EN VCC1
2 15
1A 1A 4A
1
3 14
1Y 4Y
4 13
GND GND
VCC2 5 12
MOTOR DC GND GND
6 11
2Y 3Y
7 10
2
2A 2A 3A
8 9
VCC2 3,4EN
L293 D
Gambar 3.30 Rangkaian pembalik putaran motor

53
Cara kerja rangkaian pembalik putaran motor pada gambar diatas menurut tabel
kebenaran pada tabel 3.2 :
1. Supaya rangkaian terus bekerja maka pin enable harus diberi logika tinggi,
maka pada perancangan pin enable dihubungkan ke Vcc
2. Bila kaki 1A mendapat logika tinggi dan kaki 2A mendapat logika rendah
dari mikrokontroler AT89S51 maka motor DC akan berputar CCW
3. Bila kaki 1A mendapat logika rendah dan kaki 2A mendapat logika tinggi
dari mikrokontroler AT89S51 maka motor DC akan berputar CW
4. Bila kaki 1A dan kaki2A mendapat logika yang sama maka motor DC
tidak akan berputar
Tabel 3.2 Tabel kebenaran pembalik putaran motor DC

Enable 1A 2A Arah Putaran Motor
H H L CCW
H L H CW
H H H Tidak berputar
H L L Tidak Berputar
L X X Tidak Berputar
3.15 Rancangan Pengendali Pintu Air Menggunakan Motor DC
Motor DC yang digunakan untuk memutar ulir pada model pintu air adalah
tipe GH12-164OY, yang mempunyai spesifikasi :
Tegangan catuan : 4.5V - 24V
Arus yang dibutuhkan : 120 mA
Kecepatan maksimum : 220 RPM

54
Motor ini mempunyai karakteristik semakin besar arus yang diberikan maka akan
semakin cepat pula perputarannya, motor ini juga mempunyai torque yang besar
sehingga cukup untuk menggerakkan ulir pada model pintu air. Motor DC diberi
catuan 12V pada Vcc1 dan Vcc2 rangkaian driver pengendali arah putaran motor.
Adapun rencana bentuk kontrol pintu air adalah seperti gambar 3.31.
ULIR PENGGERAK
NAIK/TURUN
PENAHAN ULIR
MOTOR DC
LINTASAN NAIK/TURUN
42 Cm
PINTU AIR
12 cm ALIRAN AIR
Gambar 3.31 Model pintu air
3.16 Pembatas Putaran Motor
Supaya motor DC berhenti berputar ketika pintu air sudah berada pada posisi
menutup atau pada posisi terbuka penuh, maka ditambahkan limited switches (LS)
seperti pada gambar 3.32. LS dirangkai sebagai penghubung antara port pararel
dengan input logika rangkaian pembalik putaran motor, seperti pada gambar 3.33.
55
LS A
TUAS PENEKAN LS
MOTOR DC
LS B
PINTU AIR
Gambar 3.32 Pembatas Putaran Motor DC
VCC1
U1
2 1 1 16
P1.0 mikrokontroler 1,2EN VCC1
LS A 2 15
1A 4A
3 14
1Y 4Y
1
4 13
GND GND
5 12
GND GND
MOTOR DC 6 11
2Y 3Y
7 10
2A 3A
2
2 1 8 9
P1.1 mikrokontroler VCC2 3,4EN
LS B
L293 D
Gambar 3.33 Rangkaian pembatas putaran motor DC

56
Fungsi pembats putaran motor DC adalah untuk mencegah supaya motor tidak
terus berputar ketika pintu air sudah tertutup atau terbuka maksimal, yang pada
akhirnya bisa mengakibatkan kerusakan baik pada motor DC maupun pada model
pintu air. Cara kerja dari rangkaian pembatas putaran motor DC adalah sebagai
berikut :
1. LS yang di pakai adalah LS normally closed (NC), LS pada kondisi normal
akan short sedang bila di tekan akan berubah kondisi mejadi open.
2. LS A akan tertekan tuas penekan bila pintu air dalam kondisi terbuka penuh.
3. Bila LS A di tekan maka kondisi yang semula short berubah menjadi open,
yang mengakibatkan instruksi untuk memutar motor DC secara CCW tidak
akan sampai ke IC L93D sehingga motor akan berhenti berputar atau hanya
bisa mendapat instruksi untuk berputar CW.
4. LS B akan tertekan tuas penekan bila pintu air dalam kondisi tertutup total.
5. Bila LS B di tekan maka kondisi yang semula short berubah menjadi open¸
yang mengakibatkan instruksi untuk memutar motor DC secara CW tidak akan
sampai ke IC L293D sehingga motor akan berhenti berputar atau hanya bisa
mendapat instruksi untuk berputar CCW.
3.17 Warning System
Warning sistem digunakan untuk memberi peringatan bila air sungai melebihi
kapasitas (tinggi air sungai >18 cm), cara kerja warning sistem adalah bila ketinggian
air sungai > 18 cm maka mikrokontroler AT89S51 pada P1.2 yang dihubungkan
dengan pin 4A IC L293D akan berlogika tinggi, yang mengakibatkan buzzer
berbunyi. Begitu sebaliknya, bila air sungai < 19 cm maka logika rendah yang akan
57
dikirim, sehingga buzzer tidak akan berbunyi.. Rangkaian warning sistem ditunjukkan
pada gambar 3.34.
VCC1
U1 P1.2 mikrokontroler
1 16
1,2EN VCC1
2 15
1A 4A
3 14
1Y 4Y
2
4 13 LS1
GND GND
5 12 BUZZER
GND GND
6 11
2Y 3Y
1
7 10
2A 3A
8 9
VCC2 3,4EN
VCC2
L293 D
Gambar 3.34 Rangkaian warning system

BAB IV
HASIL PENGAMATAN DAN PEMBAHASAN
Bab ini membahas perihal pengamatan atas rancangan telemetri ketinggian air
sebagai pengatur model pintu air berbasis mikrontroler AT89S51 dan program Visual
Basic, yang berupa pengujian perangkat keras maupun pengamatan perangkat lunak.
Pengamatan perangkat keras meliputi pengamatan sensor ketinggian air sungai,
pengondisi sinyal, modulator FSK, demodulator FSK, arah perputaran motor DC dan
pengamatan perangkat lunak berupa pengamatan program Visual basic.
Pengujian, pengamatan dan pengambilan data dengan menggunakan multimeter
digital dengan nama dagang SANWA, osiloscop digital, Audio Function Generator,
komputer dengan spesifikasi : Pentium 3 550 MHz, RAM 128 MB, Hardisk 4 Gb,
dengan operating system Micosoft Windows XP Profesional Version 2002 SP1.
4.1 Pengamatan Sensor Ketinggian air
Pengamatan sensor ketinggian air dilakukan dengan mengukur tegangan hasil
keluaran potensiometer multi turn yang dirangkai sebagai rangkaian pembagi
tegangan sesuai dengan tingkat ketinggian air. Dari hasil pengamatan dapat
digambarkan grafik hubungan antara ketinggian sungai dengan Voutput sensor
seperti pada gambar 4.1.

59
1.800
1.600
1.400
1.200
Vsensor
1.000
0.800
0.600
0.400
0.200
0.000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Ketinggian Air
Vperanc Vpercb1 Vpercb2 Vpercb3 Vpercb4
Gambar 4.1a Gambar Vsensor potensio multi turn saat air naik
1.800
1.600
1.400
1.200
Vsensor
1.000
0.800
0.600
0.400
0.200
0.000
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ketinggian Air
Vperanc Vpercb1 Vpercb2 Vpercb3 Vpercb4
Gambar 4.1b Gambar Vsensor potensio multi turn saat air turun
Ternyata dari hasil pengamatan pada waktu air sungai naik di dapat data yang
bagus (mendekati nilai perancangan) tetapi pada saat ketinggian air turun didapat data
yang tidak sempurna. Hal ini dikarenakan adanya perbedaan tekanan pada pelampung
60
sensor ketika bergerak keatas dengan ketika pelampung bergerak kebawah. Ketika
pelampung bergerak keatas maka diperlukan tekanan yang besar sehinga pelampung
akan berada dalam kondisi tenggelam sebagian, mengakibatkan potensio yang
seharusanya sudah berputar belum mau berputar. Sedangkan ketika pelampung dalam
keadaan turun kebawah tekanan yang terjadi pada pelampung lebih kecil sehinga
mengakibatkan pelampung akan mengambang dipermukaan air. Perbedaan inilah
yang mengakibatkan terjadinya kesalahan pada proses pengukuran sensor ketinggian
air di mana nantinya hal tersebut akan sangat fatal akibatnya, yakni ketinggian air
sungai yang tertampil pada PC akan berbeda dengan dengan ketinggian air sungai
yang sebenarnya dan hal ini akan mempengaruhi kinerja sistem secara keseluruhan .
Untuk mengatasi hal tersebut di atas maka pada perancangan sensor ketingian
di rubah mengunakan sistem lengan seperti pada gambar 4.2, untuk mengurangi efek
dari perbedaan gaya tekan yang timbul. Adapun sensor yang dipakai adalah
mengunakan potensio linear bernilai 49 KΩ.
Potensio Linear
20 cm Lengan
ayun
Pelampung
Gambar 4.2 Gambar sensor ketinggian sistem lengan
Bila panjang lengan yang digunakan adalah 28 cm, dengan ketinggian
maksimum air sungai 20 cm, dan R sensor untuk ketinggian air sungai 0 cm di set
61
pada 5 KΩ (potensio mulai bernilai stabil bila Rpotensio > 2 KΩ) maka berdasarkan
percobaan yang dilakukan di dapat besar hambatan maksimum dan minimum, yakni
sebesar ;
Rsensor minimum (ketinggian air sungai 0 cm) = 5 KΩ
Rsensor maksimum (ketinggian air sungai 20 cm) = 8,33 KΩ
Dari hasil percobaan terhadap potensio linear, dengan hambatan awal 5 KΩ
mengacu pada persamaan 2.5 maka dapat dihitung Vo sensor yang baru, yakni :
5.000 8.330
VO min = × 5V VO max = × 5V
49.000 49.000
= 0,510 Volt = 0.85 Volt
Dengan VO diatas maka Vinterval sensor yang baru adalah :
(0,85 V - 0,51 V)
Vinterval = × 1cm
20cm
Vinterval = 17 mV
Dengan interval diatas maka perubahan juga terjadi pada rangkaian
pengkondisi sinyal. Adapun persamaan pengkondisi sinyal yang baru dengan
mengacu pada persamaan 3.1 maka didapat persamaan yang baru yakni :
Vi = ( 4,612 x Vo ) + 1,705 ….. …………………… (4.1)
Dimana: Vi = tegangan keluaran pengkondisi sinyal (Input ADC)
Vo = tegangan keluaran sensor ketinggian air.
Dari persamaan diatas maka dibangun rangkaian pengkondisi sinyal yang baru seperti
pada gambar 4.3

62
5 Volt
Vee = -5 V
4
1.932K
2 -
1
3 +
V o1 = 1.705 V
10K
1K
8
Vee = -5 V
Vcc = 5 V 10K
4
2 -
10K 1
46.120 K 3 +
Vo3
Vee = -5 V Ke ADC
8
Vee = -5 V 08004
Vcc = 5V
4
4
2 - 10K
1 2 -
3 + 1
3 +
V o2 = Vs e ns or x 4.612
V s e ns or
8
Vcc = 5 V
Vcc = 5 V
Gambar 4.3 Gambar rangkaian pengkondisi sinyal revisi
Dengan sensor potensio linear maka dari pengamatan didapat data yang lebih
baik, seperti yang ditunjukkan pada gambar 4.4
1.000
0.900
0.800
0.700
0.600
Vsensor
0.500
0.400
0.300
0.200
0.100
0.000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Ketinggian air sungai
Vpercb3 Vpercb1 Vpercb2 Vperanc
Gambar 4.4a Vo sensor ketinggian potensio linear sistem lengan saat air sungai naik
63
1.000
0.900
0.800
0.700
0.600
Vsensor
0.500
0.400
0.300
0.200
0.100
0.000
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ketinggian Air
Vpercb3 Vpercb1 Vpercb2 Vperanc
Gambar 4.4b Vo sensor ketinggian potensio linear sistem lengan saat air sungai turun
Dari gambar 4.4 di atas dapat terlihat bahwa sensor potensio sistem lengan
bekerja lebih baik dari pada sensor potensio sistem batang bergerigi (perancangan
awal). Nilai Voutput sensor mendekati nilai pada perancangan baik pada waktu air
sungai bergerak naik maupun pada waktu air sungai bergerak turun. Dari hal trsebut
maka disimpulkan bahwa sensor ketingian dapat beroperasi dengan benar.
4.2 Pengamatan Rangkaian Pengkondisi Sinyal
Pengamatan dan pengambilan data pada rangkaian pengkondisi sinyal
dilakukan dengan cara melakukan pengukuran sebanyak empat kali pada Voutput
pengkondisi sinyal tiap 1 cm kenaikan air sungai. Hasil pengukuran tersebut
kemudian di rata-rata dan akan dibandingkan dengan perancangan untuk melihat
apakah rangkaian pengkondisi sinyal sudah dapat bekerja dengan baik. Hasil
64
pengamatan pada rangkaian pengkondisi sinyal seperti pada tabel 4.1 dengan
perhitungan galat dirumuskan sebagai berikut :
⎛ Nilai Perancangan - Data Praktek ⎞

Perbedaan = ⎜⎜ ⎟⎟ × 100%
⎝ Nilai Perancangan ⎠
Sebagai contoh perhitungan diambil data percobaan rata-rata pada ketinggian
0 cm. Dimana Vout praktek rata-rata = 0,645 V. Dan Vout perancangan = 0,647 V.
maka dapat dihitung :
⎛ 0,647 - 0,645 ⎞
Perbedaan = ⎜ ⎟ × 100%
⎝ 0,647 ⎠
Perbedaan = 0,309 %
Tabel 4.1 Tabel perbandingan data praktek dan perhitungan teori

rangkaian pengkondisi sinyal
Ketinggian Air Vout percobaan Vout rata-rata Vout Galat
(cm) (V) Percobaan (V) perancangan (%)
0,640
0,640 0,645 0,647
0 0,309
0,644
0,650
0,665
0,665 0,675 0,725 6.957
1
0,679
0,690 .
0,860
2 0,860 0,822 0,804 2.290
0,798
0,770
0,920
3 0,951 0,937 0,882 6.179
0,924
0,951
65
Lajutan Tabel 4.1 Tabel perbandingan data praktek dan perhitungan teori
0,987
4 0,991 0,981 0,961 2.145
0,973
0,973 .
1,080
5 1,068 1,062 1,039 2.185
1,058
1,040
1,192
1,148
6 1,157 1,117 3.518
1,127
1,159
1,216
1,253 1,230 1,196 2.856
7
1,203
1,247
1,330
1,338 1,323 1,274 3.807
8
1,303
1,322
1,386
1,398
9 1,389 1,353 2.725
1,380
1,393
1,484
1,470 1,478 1,431 3.316
10
1,470
1,489
1,557
1,557 1,552 1,509 2.819
11
1,550
1,543
1,645
1,647 1,634 1,588 2.891
12
1,630
1,612
66
Lanjutan Tabel 4.1 Tabel perbandingan data praktek dan perhitungan teori
1,726
1,727 1,719 1,666 3.166
13
1,710
1,712
1,811
1,804 1,806 1,745 3.503
14
1,800
1,807
1,903
1,881 1,881 1,823 3.165
15
1,850
1,888
1,955
1,958 1,958 1,901 2.974
16
1,950
1,968
2,010
2,030 2,030 1,980 2.546
17
2,020
2,060
2,180
2,100 2,120 2,058 3.013
18
2,102
2,100
2,240
2,180 2,193 2,137 2.626
19
2,184
2,170
2,280
2,280 2,248 2,215 1.476
20
2,220
2,210
Output pengkondisi sinyal diperlukan untuk memberi masukan data ke ADC
yang akan dikonversikan ke dalam bentuk digital. Output digital hasil ADC masih
bisa ditolerir kebenarannya bila melompat dua angka binernya, sebagai contoh bila
untuk ketinggian 0 cm di wakili oleh data biner 33, maka bila output ADC berupa
67
data biner 35 hasil output ADC tersebut pada PC masih akan ditampilkan data
ketingian 0 cm (data biner 35 masih dianggap benar untuk ketinggian 0 cm). dari hal
tersebut maka dapat dihitung besarnya galat yang masih di tolerir, yakni ;
Misalkan dengan mengambil contoh seperti diatas ;
Vinput ADC untuk biner 33 = 0,647 V
Vinput ADC untuk biner 35 = 0,686 V
⎛ 0,647 − 0,686 ⎞
Galat maksimum = ⎜ ⎟ × 100 %
⎝ 0,647 ⎠
= 6,027 %
Galat rata-rata table 4.1 = 3,07 %
Maka dengan melihat table 4.1 dapat terlihat bahwa galat rata-rata
nilainya < galat maksimum yang di ijinkan. Maka dapat disimpulkan bahwa
rangkaian pengkondisi sinyal sudah dapat bekerja dengan baik, karena meskipun
outputnya tidak benar-benar tepat seperti pada perancangan namun masih pada batas
yang masih bisa di tolerir,
4.3 Pengamatan Pengubah Analog ke Digital (ADC 0804)
Pengamatan pada bagian ini dengan cara memberi led pada keluaran ADC
0804, sehingga berdasar tegangan input rangkaian pengkondisi sinyal akan diketahui
bilangan biner hasil konversi keluaran ADC 0804. dan bila dihitung perbedaan antara
nilai teori dengan hasil praktek dengan rumus :
⎛ Bilangan Desimal Teori - Bilangan Desimal Data Praktek ⎞

Perbedaan = ⎜⎜ ⎟⎟ × 100%
⎝ Bilangan Desimal Teori ⎠
Maka di dapat nilai seperti yang ditunjukkan pada tabel 4.2

68
Sebagai contoh diambil Vinput = 0.647 V
Bilangan biner data praktek = 00100001 b = 33 (decimal)
Bilangan biner teori = 00100001.b = 33 (decimal)
⎛ 33 - 33 ⎞
Perbedaan = ⎜ ⎟ × 100%
⎝ 33 ⎠
Perbedaan = 0%
Tabel 4.2 Tabel perbandingan data praktek dan teori

ADC 0804
No Vinput Biner Output Bentuk Biner Output Bentuk Perbedaan
ADC (V) ADC Praktek Desimal ADC teori Desimal (%)
0 0.647 00100001 33 00100001b 33 0.00
1 0.725 00100100 36 00100101b 37 2.70
2 0.804 00101000 40 00101001b 41 2.44
3 0.882 00101101 45 00101101b 45 0.00
4 0.961 00110000 48 00110001b 49 2.04
5 1.039 00110110 54 00110101b 53 1.89
6 1.117 00111001 57 00111001b 57 0.00
7 1.196 00111101 61 00111101b 61 0.00
8 1.274 01000001 65 01000001b 65 0.00
9 1.353 01000101 69 01000101b 69 0.00
10 1.431 01001001 73 01001001b 73 0.00
11 1.509 01001101 77 01001101b 77 0.00
12 1.509 01010010 82 01010001b 81 1.23
13 1.588 01010101 85 01010101b 85 0.00
14 1.666 01011000 88 01011001b 89 1.12

69
Lanjutan tabel 4.2 Tabel perbandingan data praktek dan teori

ADC 0804
No Vinput Biner Output Bentuk Biner Output Bentuk Perbedaan
ADC (V) ADC Praktek Desimal ADC teori Desimal (%)
15 1.745 01011101 93 01011101b 93 0.00
16 1.823 01100010 98 01100001b 97 1.03
17 1.901 01100100 100 01100101b 101 0.99
18 2.058 01101011 107 01101001b 105 1.90
19 2.137 01101110 110 01101101b 109 0.92
20 2.215 01110001 113 01110001b 113 0.00
Dari tabel dapat terlihat hampir sebagian besar besar nilai output ADC
mendekati nilai pada perancangan (dasar teori). Dengan demikian dapat di katakan
bahwa rangkaian ADC0804 pada hasil perancangan BAB III dapat bekerja dengan
baik pada sistem rangkaian.
4.4 Pengamatan Keluaran Modulator FSK XR-2206
Hasil keluaran Modulator FSK berupa gelombang sinus dengan frekuensi yang
tertentu, yang bergantung pada input masukan. Bila di beri input logika 1 maka akan
dihasilkan suatu frekuensi yang disebut f mark, dan bila di beri input logika 0 maka
akan dihasilkan suatu frekuensi yang di sebut f space. Seperti perancangan pada BAB
III sebelumnya bila menggunakan R1 = 38 KΩ dan R2 = 22 KΩ, maka sesuai
persamaan 2.10 dan 2.11 dapat di hitung ulang untuk nilai fmark dan f space nya
sebesar ;
1
f mark =
0.022 uF × 38 KΩ
f mark = 1,196KHz
70
1
f space =
0.022 uF × 22 KΩ
f space = 2,066 KHz
Keluaran modulator FSK XR-2206 diamati dengan memberikan input
tegangan 5 V (logika 1) untuk mengamati frekuensi mark, dan memberikan tegangan
0 V atau dihubungkan ke ground (logika 0) untuk mengamati frekuensi space. Dari
hasil percobaan didapatkan nilai frekuensi mark dan space seperti dalam tabel 4.4
Tabel 4.3 Tabel Keluaran Modulator FSK XR-2206

Input Frekuensi output Frekuensi output Perbedaan
Tegangan Percobaan (Hz) Perancangan (Hz) (%)
5 Volt 1.149 Hz 1.196 Hz 3,91
0 Volt 2.041 Hz 2.066 Hz 1,21
Bila pada demodulator FSK XR-2211 pada perancangan menggunakan R0 total
= 30 KΩ, dan R1 = 65 KΩ, dengan mengacu persamaan 2.22, maka tracking
bandwidth dapat di hitung sebagai berikut ;
f 0 × R0
Δf =
R1
1624 Hz × 30 KΩ
Δf =
65KΩ
Δf = 749,5Hz
Dari hasil perhitungan dan gambar 4.5 di atas maka demodulator XR-2211
mempunyai tracking bandwidth sebesar 749,5 Hz x 2 = 1499 Hz
Dengana demikian, fmark dan fspace supaya masih dapat di demodulasi
ulang maka besarnya frekuensi harus berada di dalam nilai tracking badwidth diatas.
Dimana untuk ;
71
fmark nilainya harus berkisar di antara f0 – 749,5 sampai f0 Hz ( 874,5 Hz
sampai 1.624 Hz) , pada hasil percbaan fmark = 1.149 Hz
fspace nilainya harus berkisar di antara f0 sampai f0 + 749,5 Hz ( 1.624 Hz
sampai 2.373,5 Hz), pada hasil percobaan fmark = 2.066 Hz
karena output modulator FSK mempunyai nilai yang besarnya masih di dalam
tracking bandwidth demodulator, maka dapat di simpulkan bahwa frekuensi yang
dihasilkan Modulator FSK XR-2206 pada hasil percobaan akan dapat
didemodulasikan ulang dengan baik pada rangkaian Demodulator FSK XR-221, atau
dengan kata lain rangkaian Modulator XR-2206 sudah dapat bekrja dengan baik untuk
memodulasikan data-data digital menjadi sinyal-sinyal analog. Hal tersebut dapat
dibuktikan dalam pengamatan rangkaian Demodulator FSK pada tabel 4.4.
Bentuk gelombang hasil keluaran modulaor FSK XR-2206 dengan di beri
input masukan berupa gelombang kotak logika TTL dari audio frekuensi generator
dengan frekuensi 600 Hz (untuk mewakili baudrate 1200bps), akan tampak seperti
pada gambar 4.5
fmark fspace
Gambar 4.5 Bentuk gelombang keluaran Modulator XR-2206

72
Dari hasil percobaan pada gambar 4.5, di dapat untuk setiap logika 0 di wakili
oleh dua buah gelombang dengan frekuensi 1,149 KHz dan logika 1 di wakili satu
buah gelombang dengan frekuensi 2,041 KHz.
Jadi dapat di simpulkan bahwa Modulator FSK XR -2206 pada hasil
perancangan dapat bekerja dengan baik pada baudrate 1200bps. Sebagai contoh bila
mikrokontroler mengirim data 01010111b, maka bentuk gelombang keluaran dari
Modulator XR-2206 seperti ditunjukkan pada gambar 4.6, yakni bila ada data logika 1
maka output XR-2206 berupa gelombang sinus dengan frekuensi 1,141 KHz, dan bila
ada logika 0 Output XR-2206 berupa gelombang sinus dengan frekuensi 2,041 KHz .
Start Stop
8 Bit Data
Bit Bit
Data serial
0 1 1 1 0 1 0 1 0 1 Out
Output Modulator
XR2206
Gambar 4.6 Bentuk keluaran gelombang XR-2206 dengan input

data serial 01010111b
4.5 Pengamatan Keluaran Demodulator FSK XR-2211
Hasil keluaran Demodulator FSK XR-2211 berupa gelombang kotak dengan nilai
amplitudo yang tertentu. Dimana besarnya amplitudo bergantung dari input masukan
yang berupa gelombang sinus dengan frekuensi tertentu. Pengamatan hasil keluaran
demodulator FSK ini dilakukan dengan cara memberikan masukan yang berupa
73
gelombang sinus pada kaki input IC XR-2211 dengan nilai frekuensi yang tertentu,
seperti yang ditunjukkan pada tabel 4.5.
Tabel 4.4 Tabel keluaran demodulator FSK XR-2211

No Frekuensi masukan Tegangan keluaran
1. 600 Hz 0.09 V
2. 800 Hz 11.97 V
3. 1.000 Hz 11.97 V
4. 1.200 Hz 11.97 V
5. 1.300 Hz 11.97 V
6. 1.400 Hz 11.97 V
7. 2.000 Hz 0.09 V
8. 2.100 Hz 0.09 V
9. 2.200 Hz 0.09 V
10. 2.300 Hz 0.09 V
11. 2.400 Hz 0.09 V
12. 2.500 Hz 0.09 V
Dari hasil data percobaan, maka meskipun pada rangkaian modulator FSK
frekuensi mark dan space tidak bernilai tepat seperti pada perancangan (di mana
fmark =1,149 KHz dan fspace = 2,041 MHz) namun bila masih berada dalam tracking
badwith rangkaian demodulator FSK, tetap akan menghasilkan output sesuai dengan
logika pada input modulator FSK. Sebagai contohnya bila mikrokontroler AT89S51
mengirimkan data serial 01100010b maka output modulator akan menghasilkan
output yang serupa, seperti ditunjukkan pada gambar 4.7.
Dari gambar 4.7 terlihat meskipun output demodulator mempunyai bentuk
yang sama dengan input. Adapun gelombang kotak keluaran demodulator FSK XR-
2211 dari hasil percobaan didapatkan nilai tegangan untuk logika 1 sebesar 10,4 V
dan untuk logika 0 sebesar 0,09 V. Bila berdasarkan data sheet untuk mengubah level
tegangan TTL menjadi level RS232 input IC MAX232 membutuhkan High-level

74
input Voltage min = 2 V dan Low-level input voltage max = 0,8 V, maka dengan nilai
tegangan untuk logika 1 dan 0 hasil percobaan dapat dipakai sebagai input voltage IC
MAX232.
S t a r t b it S to p b it
0 0 1 0 0 0 1 1 0 1
O u t p u t D e m o d u la t o r
F S K X R -2 2 1 1
In p u t M o d u la t o r
F S K X R -2 2 0 6
Gambar 4.7 Gamabar output Modem FSK
Karena rangkaian demodulator FSK XR-2211 dapat menghasilkan bentuk
gelombang yang sama dengan input modulator FSK XR-2206, maka dapat
disimpulkan bahwa rangkaian modem FSK dapat bekerja dengan baik pada baudrate
1200 bps.
4.6 Pengamatan RS232
RS232 difungsikan sebagai rangkaian yang menjembatani logika TTL dan
RS232. Gambar 4.8 menunjukkan hasil pengubahan logika TTL menjadi logika
RS232.
Dari gambar 4.8 terlihat bahwa rangkaian pengubah level teganagn TTL
menjadi level tegangan RS232 bekerja dengan benar. Dimana logika 1 Level tegangan
TTL (10,4 V) pada output IC MAX232 di rubah level teganganya menjadi level
75
RS232 yakni sebesar -8,8 V, dan begitu sebaliknya untuk logika 0 ( 0,09 V) dirubah
level tegangannya menjadi sebesar 9,6 V. Hal ini sesuai dengan standar sinyal serial
RS 232 yang telah dijelaskan pada BAB II, yakni untuk logika 1 terletak antara -3 V
sampai -25 V, dan logika 0 terletak diantara +3 V sampai +25 V.
10,4 V
0,09 V
9,8 V
- 8,8 V
Gambar 4.8 Pengubahan level tegangan TTL menjadi level tegangan RS232
4.7 Pengamatan Program Mikrokontroler AT89S51
Pengamatan program mikrokontroler dengan menggunakan simulasi pada
program pinnacle. Ada dua macam program yang diamati, yakni program
mikrokontroler AT80S51 pada bagian pemancar (pengubah data pararel manjadi data
serial) dan pada bagian penerima (pengendali putaran motor DC dan buzzer)
4.7.1 Pengamatan Program Mikrokontroler AT 89S51 Pada Bagian Pemancar
Pada bagian ini pengamatan pada program pinancle berupa output pin kontrol
ADC .Pertama diaktifkan mikrokontroler akan mengirimkan sinyal tulis pada pin
P2.1, seperti ditunjukkan pada Gambar 4.9a. Bila ADC telah selesai mengkonversi
data, maka akan mengirimkan sinyal EOC pada pin P2.0, seperti ditunjukkan pada
76
Gambar 4.9b. Setelah sinyal EOC diterima mikrokontroler, mikrokontroler akan
mengirimkan sinyal baca pada P2.2, output P2.2 seperti Gambar 4.9.
Gambar 4.9a P2.1 berlogika 0 Gambar 4.9b P2.0 berlogika 0
Gambar 4.9c P2.2 berlogika 0
4.7.2 Pengamatan Program Mikrokontroler AT 89S51 Pada Bagian Penerima
.Pada bagian ini diamati hasil keluaran P1.0, P1.1, dan P1.2 pada
mikrokontroler AT 89S51. Pengamatan dilakukan dengan cara memberikan instruksi
memutar motor dan membunyikan warning system melalui program Visual Basic 6
dan melakukan pengukuran pada P1.0, P1.1, dan P1.2 dengan menggunakan
multimeter digital sesuai dengan instruksi yang diberikan. Dimana hasil keluaran akan
berupa tegangan yang mengindikasikan logika keluaran, yang akan dipakai untuk
mengontrol arah putaran motor DC dan membunyikan buzzer. Hasil percobaan seperti
pada tabel 4.5.

77
Tabel 4.5 Tabel pengamatan P1 Mikrokontroler AT89S51

pada bagian penerima
Instruksi yang diberikan Tegangan P1.0 Tegangan P1.1 Teganan P1.2
Putar motor CCW 4,98 V 0,05 V 0,05 V
Putar motor CW 0,05 V 4,98 V 0,05 V
Motor berhenti berputar 0,05 V 0,05 V 0,05 V
Bunyikan buzzer 0,05 V 0,05 V 4,98 V
Matikan buzzer 0,05 V 0,05 V 0,05 V
Dari tabel pengamatan 4.5 maka dapat disimpulkan ;
1. untuk logika 1 mempunyai level tegangan sebesar 4,98 V, untuk logika 0
mempunyai level tegangan = 0,05 V
2. bila berdasar pada data sheet IC L293D untuk logika 1 level tegangan
input harus > 2,3 V dan untuk logika 0 level tegangan input harus < 1,5 V,
maka berdasar tabel 4.5 dapat disimpulkan bahwa mikrokontroler dapat
bekerja dengan baik pada sistem rangkaian sebagai driver IC L293D.
4.8 Pengamatan Rangkaian Pembalik Putaran Motor DC dan Warning System
L293D
Pengamatan pada rangkaian ini dilakukan dengan memberikan input tegangan
pada kaki input IC l293D sesuai dengan level tegangan output mikrokontroler, yakni
0,05 V (logika 0) atau 4,98 V (logika 1). Dimana pin 2 dan 7 sebagai pin input
pengatur putaran motor DC, dan pin 15 sebagai input pengatur buzzer. Hasil
pengamatn ditunjukan pada tabel 4.6.

78
Tabel 4.6 Tabel pengamatan IC L293D

LOGIKA
Output
Pin 2 Pin 7 Pin 15
1 0 - Motor berputar CCW
0 1 - Motor berputar CW
0 0 - Motor tidak berputar
1 1 - Motor tidak berputar
- - 1 Buzer berbunyi
- - 0 Buzer tidak bebunyi
Dari data yang diperoleh pada tabel 4.6, membuktikan bahwa level tegangan
output pada mikrokontroler AT89S51 dapat berfungsi sebagai diver IC L293D dan
ICL293D sendiri dapat bekerja dengan baik pada sistem rangkaian sebagai rangkaian
pembalik putaran motor DC dan warning system sesuai dengan perancangan pada
BAB III.
4.9 Pengamatan Kerja Program Visual Basic 6.0

Pengamatan kerja program Visual Basic berupa pengamatan proses kerja
program untuk mengetahui ketingian air sungai dan menampilkannya, serta bentuk
tampilan tiap formnya.
4.9.1 Pengamatan Form Pengaturan Otomatis
Pertama kali program Pengaturan Pintu Air di jalankan akan ditampilkan
menu perintah untuk mengisi ketingian air yang akan diatur, seperti pada gambar
4.10. Bila ketinggian air yang di isi tidak sesuai ketentuan maka akan ditampilkan
menu pemberitahuan seperti yang ditunjukan pada gambar 4.11.

79
Setelah nilai ketinggian air yang akan di atur telah di isi sesuai dengan
ketentuan, form utama pengaturan otomatis akan ditampilkan seperti yang ditunjukan
pada gambar 4.12.
Gambar 4.10 Instruksi untuk mengisi ketinggian air yang akan diatur
Gambar 4.11a Menu Pemberitahu nilai yang dimasukan

melebihi batas yang seharusnya
Gambar 4.11b Menu pemberitahu bila ketinggian air

yang akan di atur belum di isi
Pada pengaturan otomatis terdapat beberapa menu dan fungsinya, adapun fungsi
dari menu dan tombol tersebut antara lain :
1. Tombol “Atur ketinggian” : tombol yang digunakan untuk merubah
ketinggian air sungai yang telah di isi user sewaktu pertama kali membuka
80
program. Bila tombol ini di tekan maka akan muncul tampilan untuk mengisi
ketinggian air sungai yang akan di atur seperti pada gambar 4.10.
2. Tombol “Pengaturan Manual”: tombol yang digunakan untuk berpindah dari
sistem pengaturan otomatis ke pengaturan manual. Bila tombol ini ditekan
maka form pengaturan otomatis akan berganti menjadi form pengaturan
manual seperti yang ditunjukkan pada gambar 4.13.
3. Tombol “Keluar” : tombol keluar digunakan bila hendak keluar dari program
menu “Bantuan” : menu bantuan di pakai untuk memberi pengetahuan tentang seluk
beluk program tersebut, baik tentang profil pembuatnya maupun tentang cara
menggunakan program.
Ketinggian air yang

Menu untuk di masukan user
mengakses menu
bantuan
Ketinggian air yang

sebenarnya
Tombol Untuk Tombol untuk

merubah ketinggian keluar dari
yang akan diatur progam
Tombol untuk
berpindah ke sistem
pengaturan manual
Gambar 4.12 Tampilan program Pengaturan Otomatis

81
Pada program Visual Basic 6.0 baik pada pengaturan otomatis dan pengaturan
manual untuk mengakses data serial digunakan instruksi sebagai berikut :
masuk = Comm1.Input
untuk mengirim data serial digunakan instruksi :
Comm1.Output = "data yang akan dikirm"
4.9.2 Pengamatan Form Pengaturan Manual
Form manual di pilih bila akan mengatur ketinggian air sungai secara manual.
Tampilan form pengaturan manual seperti pada gambar 4.13. Pada form ini terdapat
tampilan ketinggian air sungai hasil sensor ketinggian air, dan beberapa tombol
perintah diantaranya tombol Buka, Tutup, Pengaturan Otomatis, Keluar. Adapun
fungsi dari tombol perintah tersebut adalah sebagai berikut ;
1. Tombol “Buka” : tombol buka digunakan untuk membuka pintu air. Bila
tombol ini di tekan maka akan di kirim instruksi putar motor CCW yang
berarti pintu air akan begerak terbuka keatas.
2. Tombol “Tutup” : tombol tutup digunakan untuk menutup pintu air. Bila
tombol ini di tekan maka akan di kirim instruksi putar motor CW yang berarti
pintu air akan bergerak menutup ke bawah.
3. Tombol “Pengaturan Otomatis” : tombol ini berfungsi untuk berpindah dari
pengaturan manula ke pengaturan otomatis. Bila ditekan maka form
pengaturan manual akan berganti menjadi form pengaturan otomatis.
4. Tombol “Keluar” : tombol ini di pakai untuk keluar dari program.

82
Tombol untuk
membuka pintu air
Tombol untuk
menutup pintu air
Ketinggian air
sungai
Tombol untuk Tombol untuk

berpindah ke keluar program
pengaturan otomatis
Gambar 4.13 Gambar tampilan utama pengaturan manual
4.9.3 Pengamatan Form Menu Bantuan Menggunakan Program
Menu bantuan digunakan sebagai media informasi tentang seluk beluk
program. Didalamnya terdapat menu tentang profil pembuat program dan menu cara
pemakaian program seperti yang ditunjukkan pada gambar 4.14 .
Gambar 4.14 Menu bantuan Menggunakan Program

83
4.10 Pengamatan Unjuk Kerja Sistem
Pengamatan ini dilakukan untuk mengamati sejauh mana alat tersebut bekerja.
Pengamatan ini dilakukan dengan membandingkan antara ketinggian air yang terukur
dengan ketinggian air yang tertampil pada PC, dan pengamatan dari kerja program
secara keseluruhan.
4.10.1 Pengamatan Unjuk Kerja Sistem Menggunakan Media Transmisi Kabel
Untuk mengetahui apakah modem FSK sudah bekerja dengan baik maka
dilakukan pengamatan dengan cara menghubungkan antara output modulator FSK
dengan input demodulator FSK menggunakan media transmisi kabel seperti yang
ditunjukan pada gambar 4.15, dengan kecepatan pengisyaratan data 1200 bps,
kemudian dibandingkan antara ketinggian air yang terukur dengan ketinggian air yang
tertampil pada PC
Pemancar Penerima
FM FM
Kabel Penghubung
Modulator FSK Demodulator FSK
Gambar 4.15 Penggunaan kabel sebagai media transmisi
Dari hasil percobaan seperti pada gambar 4.15 diatas, didapatkan tampilan
ketinggian air hasil pengukuran sensor pada program Visual Basic 6.0 seperti pada
tabel 4.7.
84
Tabel 4.7 Tabel pengamatan ketinggian air sungai

yang tertampil pada PC dengan media transmisi kabel
Ketinggian Air Yang Ketinggian Yang

Terukur (cm) Tertampil di PC (cm)
0 0
1 0
2 2
3 4
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
Dari hasil pengamatan pada table 4.7, PC dapat menampilkan ketinggian air
sungai yang terukur dengan baik. Dari hasil percobaan ini dapat disimpulkan bahwa
modem dapat bekerja dengan baik pada kecepatan pengisyaratan data 1200 bps.
4.10.2 Pengamatan Unjuk Kerja Sistem Telemetri Secara FM
Setelah dilakukan percobaan dengan media transmisi kabel dan modem
dinyatakan bekerja dengan baik, percobaan dilanjutkan dengan mentransmisikan data
secara termodulasi frekuensi, untuk melihat tingkat keberhasilan kerja sistem secara
telemetri.
85
4.10.2.1 Dengan Kecepatan Pengisyaratan Data 1200 bps
Dari hasil percobaan menggunakan kecepatan pengisyaratan data sebesar 1200
bps, di dapat data seperti pada tabel 4.8 (dengan hanya mengambil beberapa data
saja).
Tabel 4.8 Tabel perbandingan ketinggian air sungai sebenarnya dengan yang
tertampil pada PC menggunakan transmisi pemancar FM
Ketinggian sebenarnya Ketingian Tertampil pada PC
0 cm
0 cm Tidak tertampil
6 cm
Tidak tertampil
3 cm
5 cm 9 cm
Tidak tertampil
5 cm
10 cm
10 cm 15 cm
20 cm
10 cm
Tidak tertampil
15 cm 7 cm
13 cm
Tidak tertampil
20 cm
20 cm 16 cm
14 cm
Tidak tetampil
Dari hasil pengamatan pada tabel 4.8 terlihat bahwa terjadi banyak kesalahan
dalam penampilan ketinggian air. Tidak tertampilnya ketinggian air sungai pada PC
mengindikasikan bahwa data biner yang di akses program Visual Basic 6.0 melampui
atau kurang dari data yang di ijinkan masuk, dimana data yang di ijinkan masuk di
antara biner 00100000b sampai 01110011b. Bila data yang di akses tidak berada
dalam range tersebut maka Program tidak akan menampilkan ketinggian air sungai.
Penyebab dari pemasalahan tersebut adalah karena pemancar FM yang digunakan
tidak berkualitas bagus dan daya pancar yang tidak terlalu kuat maka pentransmisian
86
data rentan sekali tehadap intererensi. Dari gambar 4.6 dapat terlihat bahwa fmark
hasil output modulator hanya terdiri dari 1 gelombang sinus, dan fspace terdiri dari 2
gelombang sinus, maka fmark dengan jumlah gelombang yang sedikit akan rentan
sekali terjadi interferensi yang nantinya akan mengakibatkan terjadinya kesalahan
pada proses demodulasi. Kesalahan proses demodulasi seperti ditunjukkan pada
gambar 4.16.
D a ta y a n g
d im o d u la s ik a n
D a ta h a s il
d e m o d u la s i
Gambar 4.16
Kesalahan proses demodulasi data FSK
Dari gambar 4.16 data hasil demodulasi berbeda jauh dengan data yang
dimodulasikan di mana pada contoh di atas data yang di demodulasi adalah
00101011b (desimalnya 43 mewakili ketinggian 2 cm), ternyata output demodulasi
berubah menjadi 00100011b (desimalnya 35 mewakili ketinggian 0 cm).
4.10.2.2 Dengan Kecepatan Pengisyaratan Data 300 bps
Untuk mengatasi hal tersebut maka penulis melakukan percobaan dengan
menurunkan kecepatan pengisyaratan data dari yang semula 1200 bps menjadi 300
bps. Dari hasil percobaan tersebut di dapat data pengamatan seperti yang ditunjukkan
pada tabel 4.9.

87
Tabel 4.9 Tabel pengamatan ketinggian air sungai yang

tertampil pada PC dengan kecepatan pengisyaratan data 300 bps
Ketinggian Air Yang Ketinggian Yang

Terukur (cm) Tertampil di PC (cm)
0 0
1 2
2 3
3 4
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
19 19
20 20
Dari tabel 4.9 dapat disimpulkan bahwa sistem bekerja baik dengan
menggunakan kecepatan pengisyaratan data 300 bps. Hal tersebut di karenakan bila
menggunakan kecepatan pengisyaratan data 300 bps maka jumlah gelombang baik
pada fmark dan fspace akan menjadi lebih banyak (seperti pada gambar 4.17)
sehingga bila terjadi interferensi tidak akan berpengaruh besar pada proses
demodulasi (demodulator FSK masih dapat mengidentifikasi dengan baik fmark dan
fspace)..
88
O u tp u t M o d u la to r F S K
fm a rk fs p a c e
O u tp u t D e m o d u la to r F S K
Gambar 4.17 Ouput Modem FSK dengan kecepatan pengisyaratan data 300 bps
Dari hasil pengamatan pada tabel 4.7 di atas dapat di simpulkan bahwa
perancangan ini mempunyai kelemahan yakni bila di pakai untuk pengukuran
ketinggian air dibawah 5 cm. Untuk ketinggian dibawah 5 cm di dapat hasil
pengukuran yang tidak benar-benar tepat, atau dengan kata lain sensor ketinggian
mempunyai gerak yang tidak stabil pada ketinggian yang rendah.
4.10.3 Kerja Sistem Pada Pengaturan Otomatis
Pada pengaturan otomatis data yang dimasukan oleh user di pakai sebagai
pembanding untuk menentukan apakah pintu air harus menutup, membuka atau diam.
Pada pengamatan ini dilakukan dengan cara memberikan masukan input ketinggian
yang akan diatur, dimana diambil ketinggian yang akan di atur adalah 6 cm.
Pengamatan di lakukan pada kondisi awal model sungai dalam keadaan kering
(ketinggian 0 cm) dan di amati dalam rentang waktu tertentu. Dari hasil pengamatan
dapat digambarkan grafik perubahan waktu terhadap ketinggian air sungai hasil
pengaturan seperti yang ditunjukkan pada gambar 4.18.

89
ketinggian air yang diatur 6 cm
6
Ketinggian air sungai
0
0 20 40 60 80 100 120
Waktu ( detik ) Ketinggian air sungai
Gambar 4.18 Gambar grafik perubahan waktu

terhadap ketinggian air yang diatur
Dari gambar 4.18 pengaturan secara otomatis dalam mengatur ketinggian air
masih terjadi overshoot terhadap batas ketinggian yang ditentukan. Hal ini
dikarenakan sangat sulitnya membuat model pintu air sungai yang mendekati kondisi
sebenarnya. Sehingga ketika pintu air membuka sedikit saja air langsung naik dengan
cepat, sehingga mengakibatkan terjadinya overshoot.
Pada pengturan pengaturan otomatis juga terdapat beberapa pesan
pemberitahu seperti yang ditunjukkan pada gambar 4.19 dan 4.20. Bila ketinggian air
sungai > 18 cm maka akan tertampil peringatan bahwa sungai meluasp, dan warning
system akan aktif dengan di tandai berbunyinya buzzer. Sedangkan bila ketinggian
sungai kurang dari 1 cm maka pada form pengaturan otomatis tertampil pesan sungai
kering seperti yang ditunjukkan pada gambar 4.20.

90
Ketinggian
> 18 cm
Pesan
pemberitahu
sungai meluap
Gambar 4.19 Tampilan peringatan sungai meluap
Ketinggian
air <1 cm
Pesan sungai
kering
gambar 4.20 Tampilan sungai kering

91
4.10.4 Kerja Sistem Pada Pengaturan Manual
Pada sistem pengaturan manual user melakukan perintah untuk membuka atau
menutup pintu air secara manual, yakni dengan menekan tombol “Buka” atau “Tutup’
yang terdapat pada form pengaturan manual. Pengamatan dilakukan dengan cara
memberikan perintah membuka atau menutup pintu air, dan berdasarkan data
ketinggian air yang di terima di amati kerja sistem pada pengaturan manual.
Dari hasil pengamatan yang dilakukan maka di buat tabel hasil pengamatan
seperti yang ditunjukan pada tabel 4.10
Tabel 4.10 Pengamatan kerja sistem

pengaturan manual
Lama memberi Tinggi pintu air

Instruksi
Instruksi (detik) Membuka (cm)
0 0
10 2,2
Tombol 20 4,3
“ BUKA “ di 30 6,1
tekan 40 8
50 9,7
60 10.5
0 10
10 8,6
Tombol 20 6,1
“TUTUP” di 30 4,8
tekan 40 2,5
50 0,9
60 0
92
Lanjutan Tabel 4.11 Pengamatan kerja sistem

pengaturan manual
Lama memberi Tinggi pintu air

Instruksi
Instruksi (detik) Membuka (cm)
0 0
10 0
Tidak ditekan
20 0
tombol apapun
30 0
40 0
50 0
60 0
Dari tabel pengamatan diatas maka dapat disimpulkan bahwa sistem
pengaturan manual sudah bekerja dengan baik sebagaimana mestinya.
Pada form pengaturan manual tedapat beberapa pesan pemberitahu,
diantaranya pesan pemberitahu apakah user sedang membuka atau menutup pintu air
(seperti pada gambar 4.21 dan gambar 4.22), pesan pemberitahu bahwa pintu tidak
dapat di buka lagi karena air sungai berada pada ketinggian di atas 18 cm (seperti
pada gambar 4.23), dan pesan pemberitahu bahwa pintu air tidak dapat di tutup lagi
karena air sungai berada pada ketinggian 0 (seperti pada gambar 4.24).
93
Instruksi yang
Pesan pemberitahu
dilakukan
instruksi yang
dilakukan
Ketinggian air
sungai
Gambar 4.21 Pesan pemberitahu pintu sedang di buka
Pesan pemberitahu
instruksi yang
dilakukan
Instruksi yang
dilakukan
Ketinggian air
sungai
Gambar 4.22 Pesan pemberitahu pintu sedang di tutup

94
Pesan
Gambar pemberitahu
Instruksi yang
dilakukan
Pesan
peringatan
Ketinggian air
sungai
4.23 Pesan pemberitahu pintu tidak dapat di buka lagi
Pesan
pemberitahu
Pesan
peringatan Instruksi yang
dilakukan
Ketinggian air
sungai
Gambar 4.24 Pesan pemberitahu pintu tidak dapat di tutup lagi

BAB V
KESIMPULAN DAN SARAN
5.1 Kesimpulan
Berdasarkan perancangan dan pengujian telemetri ketinggian air sebagai pengatur
model pintu air dengan MCS-51 dan program Visual Basic dapat diambil kesimpulan
sebagai berikut :
1. Program dapat menampilkan hasil pengukuran ketinggian air sungai, dapat
menggatur model pintu air dan dapat memberi peringatan bahwa sungai meluap
2. Sensor ketinggian air mempunyai hasil pengukuran yang kurang baik untuk
ketinggian di bawah 5 cm.
3. Hasil perancangan ini mempunyai kelemahan pada pengaturan otomatisnya, yakni
hasil dari pengaturan ketinggian air tidak benar-benar tepat seperti yang
dimasukkan user, tetapi masih terjadi overshoot terhadap ketinggian yang di atur.
5.2 Saran
1. Pengukuran ketinggian air dapat di buat lebih teliti, yakni dengan memperkecil
skala ketinggian (dalam mili meter)
2. Telemetri ketinggian air sebagai pengatur model pintu air dapat dikembangkan
untuk sistem operasi yang berbasis open source seperti pada linux.
96
3. Telemetri ketinggian air sebagai pengatur model pintu air dapat dikembangkan
dengan penampil berupa LCD dan pengontrol mengunakan keypad untuk
penghematan biaya.
4. Perancangan telemetri ketinggian air sebagai pengatur model pintu air dapat
dikembangkan bukan hanya sebatas model melainkan kedalam bentuk yang
nyata.
DAFTAR PUSTAKA
[1] Albert Paul Malvino, Prinsip-prinsip Elektronika, Jakarta:Penerbit Erlangga,
1986.
[2] http://pdf1.alldatasheet.com/datasheet-pdf/view/66283/INTERSIL/ADC0804.html
[3] http://www.elektro.undip.ac.id/transmisi/des05/sukiswodes05.PDF
[4] http://www.ortodoxism.ro/datasheets/exar/XR2206v103.pdf
[5] http://www.jaycar.com.au/images_uploaded/XR2211V3.PDF
[6] Agfianto Eko Putra, Belajar Mikrokontoler AT89C51/52/55 (Teori dan Aplikasi),
Yogyakarta:Penerbit Gava Media, 2004.
[7] Retna Prasetia dan Catur Edi Widodo, Interfacing Port Paralel dan Port Serial
Komputer dengan Visual Basic 6.0, Yogyakarta: Penerbit Andi, 2004.
[8] Eko Pamuji, Komunikasi Full Duplex dengan Modulasi Frekuensi, Jurusan
Teknik elektro, Universitas Sanata Dharma, 2002.
[9] http://en.wikipedia.org/wiki/DC_motor
[10] http://focus.ti.com/lit/ds/symlink/l293.pdf
96
LAMPIRAN
RANGKAIAN TELEMETRI BAGIAN PEMANCAR
VCC 5V VCC 12V

5 Volt
Vee = -5 V
1
R4 C6
40
31
1.932 K 2 1uF
4
39 21
EA/VPP
VC C
2 - 38 P0.0/AD0 P2.0/A8 22
6 37 P0.1/AD1 P2.1/A9 23
P0.2/AD2 P2.2/A10
4
3 + R11 R12 VCC = 5V 36 24
U3 R8 2.2 K 2.2 K 35 P0.3/AD3 P2.3/A11 25 1 16
3
VC C
CA3140 10 K 34 P0.4/AD4 P2.4/A12 26 5 AMSI SYMA2 15
R5 33 P0.5/AD5 P2.5/A13 27 TC1 SYMA1 14
8
1K 32 P0.6/AD6 P2.6/A14 28 C5 WAVEA2
20
R6 Vee = -5 V P0.7/AD7 P2.7/A15 0.022 uF 6 R16 200
Vcc = 5 V 10 K 9 18 1 10 9 TC2 13
VC C /VR EF
VREF/2 DB0 17 2 P1.0 P3.0/RXD 11 FSKI WAVEA1
1 DB1 16 3 P1.1 P3.1/TXD 12 2
CS DB2 P1.2 P3.2/INTO STO PEMANCAR FM
4
15 4 13 7
2 - DB3 14 5 P1.3 P3.3/INT1 14 TR1
R3 6 6 DB4 13 6 P1.4 P3.4/TO 15 R14 38K 11
46.120K 3 R9 10K +IN DB5 12 7 P1.5 P3.5/T1 16 8 SYNCO
BIAS
GN D
+
DB6 P1.6 P3.6/WR TR2
MO
U4 19 11 C3 8 17
R7 CA3140 CLKR DB7 30 pF P1.7 P3.7/RD R15 22K U7
Vee = -5 V 10 K 4 19 29 XR-2206
8
CLKIN XTAL1 PSEN
10
12
Vee = -5 V 150 pf 18
3
C1 2 11.0592Mhz 9 XTAL2 30
GND
GND
6 Volt Vcc = 5V 3 RD 5 RST ALE/PROG
-IN
GN D
WR INTR R19
4
R2
1
1
R1 2 - 10k C4 C7 50 K
10
6 2 U5 30 pF 1uF Vee -5V
7
8
-
20
SENSOR 2 3 + 6 ADC0804 U6 2
CA3140 3 + C2 VCC AT89S51
U2
U1 CA3140
8
R13 10uF C8
8
10 K 10 uF
3
3
Vcc = 5 V
Vcc = 5 V R17 R18
SW PUSHBUTTON
VCC 12V
SW1
5.1K 5.1K
Title
TELEMETRI KETINGGIAN AIR SEBAGAI PENGATUR MODEL PINTU AIR
Size Document Number Rev

Custom PEMANCAR <Rev Code>
Date: Friday , June 15, 2007 Sheet 1 of 1
L1
VCC = 5V
RANGKAIAN TELEMETRI BAGIAN PENERIMA
40
31
39 21
E A /V P P
VC C
38 P0.0/AD0 P2.0/A8 22 VCC = 12V VCC = 12V
37 P0.1/AD1 P2.1/A9 23
36 P0.2/AD2 P2.2/A10 24
35 P0.3/AD3 P2.3/A11 25 2 1 1 16
34 P0.4/AD4 P2.4/A12 26 1,2EN VCC1
33 P0.5/AD5 P2.5/A13 27 LS A 2 15
32 P0.6/AD6 P2.6/A14 28 1A 4A
P0.7/AD7 P2.7/A15 3 14
1Y 4Y
2
1 10
2 P1.0 P3.0/RXD 11 4 13 LS1
3 P1.1 P3.1/TXD 12 GND GND
5 14 4 P1.2 P3.2/INTO 13 MOTOR DC 5 12 BUZZER
LDOQN COMP 1 C6 5 P1.3 P3.3/INT1 14 GND GND
C1 C4 30 pF 6 P1.4 P3.4/TO 15 6 11
2 13 33n 7 P1.5 P3.5/T1 16 2Y 3Y
PENERIMA FM
1
INP NC 8 P1.6 P3.6/WR 17 7 10
3 P1.7 P3.7/RD 2A 3A
2
0.1 u LDF 10 19 29 2 1 8 9
4 TIM R 11.0592Mhz 18 XTAL1 PSEN VCC2 3,4EN
GND C5 9 XTAL2 30 LS B
9 0.1 u RST ALE/PROG U4
GND
6 TIM C2 L293 D
LDO C7 VCC = 12V
30 pF
20
U2
Vcc = 12 V 12 1 3 AT89S51
1 VREF
Vcc R5 10K C8 VCC = 5 V
T IM C 1
10K
LD O
U1
DO
XR-2211 R6 10uF
10 K
11
R4
7
65K
R1 SW PUSHBUTTON
5.1K SW1
R2 R3 VCC 5 V
1.6M 325K
C2 C3 C9
0.66n 2.4n 1uF
16
2 12
VC C
9 V+ R1OUT 14
P1
10 R2OUT T1OUT 1
T2IN
C ON N EC T OR D B9
6
7 2
1 T2OUT 7
3 C+ 8 3
C10 4 C1- R2IN 8
1uf 5 C2+ 4
C2- 13 9
GN D
6 R1IN 11 5
C11 V- T1IN
1uF
15
U3
MAX232
C12
1uF
Title
TELEMETRI KETINGGIAN AIR SEBAGAI PENGATUR MODEL PINTU AIR
Size Document Number Rev

CustomBAGIAN PENERIMA <Rev Code>
Date: Friday , June 15, 2007 Sheet 1 of 1
L2
PRORAM VISUAL BASIC :
PROGRAM PENGATURAN OTOMATIS :

,-----------------------------------------------------------------------------------------------------------
‘Setting komunikasi serial
‘-----------------------------------------------------------------------------------------------------------
Private Sub Form_Load()
Dim a As String
a = masukan.Caption
Comm1.CommPort = 1
Comm1.Settings = "300,n,8,1"
Comm1.InputLen = 1
Comm1.PortOpen = True
End Sub
‘-----------------------------------------------------------------------------------------------------------
‘Perintah memasukan ketinggian yang akan di atur
‘-----------------------------------------------------------------------------------------------------------
Private Sub Form_Activate()
If masukan.Caption = "" Then
GoTo nilai
Else: GoTo akir
End If
nilai:
masukan.Caption = InputBox("Masukkan nilai ketinggian air sungai yang ingin di atur
(dalam rentang 0 - 20 cm)")
a = masukan.Caption
If Val(a) > 20 Then
MsgBox ("Maaf nilai yang anda masukan melebihi batas. Silahkan ulangi kembali ")
GoTo nilai
End If
If a = "" Then
MsgBox ("Anda belum memasukan nilai ketinggian yang akan diatur. Masukkan nilai
ketinggian air sungai yang ingin anda atur ")
GoTo nilai
End If
If Asc(a) < 48 Then GoTo nilai
If Asc(a) > 57 Then GoTo nilai
akir:
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Merubah ketinggian air yang akan di atur
‘-----------------------------------------------------------------------------------------------------------
Private Sub atur_MouseDown(Button As Integer, Shift As Integer, X As Single, Y As
Single)
nilai:
L3
masukan.Caption = InputBox("Masukkan nilai ketinggian air sungai yang ingin di atur
(dalam rentang 0 - 20 cm)")
a = masukan.Caption
If Val(a) > 20 Then
MsgBox ("Maaf nilai yang anda masukan melebihi batas. Silahkan ulangi kembali ")
GoTo nilai
End If
If a = "" Then
MsgBox ("Anda belum memasukan nilai ketinggian yang akan diatur. Masukkan nilai
ketinggian air sungai yang ingin anda atur ")
GoTo nilai
End If
If Asc(a) < 48 Then GoTo nilai
If Asc(a) > 57 Then GoTo nilai
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Berpindah kepengaturan manual
‘-----------------------------------------------------------------------------------------------------------
Private Sub manual_Click()
Comm1.Output = "S"
Timer1.Enabled = False
pengatotomatis.Comm1.PortOpen = False
pengaturanmanual.Visible = True
pengatotomatis.Visible = False
pengaturanmanual.Comm1.PortOpen = True
pengaturanmanual.Timera.Enabled = True
pengaturanmanual.Timerb.Enabled = True
pengaturanmanual.Timerc.Enabled = True
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Deklarasi ketinggian air
------------------------------------------------------------------------------------------------------------
Private Sub Timer1_Timer()
Dim tinggi, Text2 As Integer
Dim masuk As String
masuk = Comm1.Input
If masuk = "!" Then

tinggi = 0
ElseIf masuk = "#" Then
tinggi = 0
ElseIf masuk = "$" Then
tinggi = 1
L4
ElseIf masuk = "%" Then
tinggi = 1
ElseIf masuk = "&" Then
tinggi = 1
ElseIf masuk = "'" Then
tinggi = 1
ElseIf masuk = "(" Then
tinggi = 2
ElseIf masuk = ")" Then
tinggi = 2
ElseIf masuk = "*" Then
tinggi = 2
ElseIf masuk = "+" Then
tinggi = 2
ElseIf masuk = "," Then
tinggi = 3
ElseIf masuk = "-" Then
tinggi = 3
ElseIf masuk = "." Then
tinggi = 3
ElseIf masuk = "/" Then
tinggi = 3
ElseIf masuk = "0" Then
tinggi = 4
tinggi = 4
tinggi = 4
tinggi = 4
tinggi = 5
tinggi = 5
tinggi = 5
tinggi = 5
tinggi = 6
tinggi = 6
ElseIf masuk = ":" Then
tinggi = 6
ElseIf masuk = ";" Then
tinggi = 6
L5
ElseIf masuk = "<" Then
tinggi = 7
ElseIf masuk = "=" Then
tinggi = 7
ElseIf masuk = ">" Then
tinggi = 7
ElseIf masuk = "@" Then
tinggi = 8
ElseIf masuk = "A" Then
tinggi = 8
ElseIf masuk = "B" Then
tinggi = 8
ElseIf masuk = "C" Then
tinggi = 8
ElseIf masuk = "D" Then
tinggi = 9
ElseIf masuk = "E" Then
tinggi = 9
ElseIf masuk = "F" Then
tinggi = 9
ElseIf masuk = "G" Then
tinggi = 9
ElseIf masuk = "H" Then
tinggi = 10
ElseIf masuk = "I" Then
tinggi = 10
ElseIf masuk = "J" Then
tinggi = 10
ElseIf masuk = "K" Then
tinggi = 10
ElseIf masuk = "L" Then
tinggi = 11
ElseIf masuk = "M" Then
tinggi = 11
ElseIf masuk = "N" Then
tinggi = 11
ElseIf masuk = "O" Then
tinggi = 11
ElseIf masuk = "P" Then
tinggi = 12
ElseIf masuk = "Q" Then
tinggi = 12
ElseIf masuk = "R" Then
tinggi = 12
ElseIf masuk = "S" Then
tinggi = 12
L6
ElseIf masuk = "T" Then
tinggi = 13
ElseIf masuk = "U" Then
tinggi = 13
ElseIf masuk = "V" Then
tinggi = 13
ElseIf masuk = "W" Then
tinggi = 13
ElseIf masuk = "X" Then
tinggi = 14
ElseIf masuk = "Y" Then
tinggi = 14
ElseIf masuk = "Z" Then
tinggi = 14
ElseIf masuk = "[" Then
tinggi = 14
ElseIf masuk = "\" Then
tinggi = 15
ElseIf masuk = "]" Then
tinggi = 15
ElseIf masuk = "^" Then
tinggi = 15
ElseIf masuk = "_" Then
tinggi = 15
ElseIf masuk = "`" Then
tinggi = 16
ElseIf masuk = "a" Then
tinggi = 16
ElseIf masuk = "b" Then
tinggi = 16
ElseIf masuk = "c" Then
tinggi = 17
ElseIf masuk = "d" Then
tinggi = 17
ElseIf masuk = "e" Then
tinggi = 17
ElseIf masuk = "f" Then
tinggi = 17
ElseIf masuk = "g" Then
tinggi = 18
ElseIf masuk = "h" Then
tinggi = 18
ElseIf masuk = "i" Then
tinggi = 18
ElseIf masuk = "j" Then
tinggi = 18
L7
ElseIf masuk = "k" Then
tinggi = 19
ElseIf masuk = "l" Then
tinggi = 19
ElseIf masuk = "m" Then
tinggi = 19
ElseIf masuk = "n" Then
tinggi = 19
ElseIf masuk = "o" Then
tinggi = 20
ElseIf masuk = "p" Then
tinggi = 20
ElseIf masuk = "q" Then
tinggi = 20
ElseIf masuk = "r" Then
tinggi = 20
ElseIf masuk = "s" Then
tinggi = 20
ElseIf masuk = "t" Then
tinggi = 20
ElseIf masuk = "u" Then
tinggi = 20
ElseIf masuk = "v" Then
tinggi = 20
ElseIf masuk = "w" Then
tinggi = 20
ElseIf masuk = "x" Then
tinggi = 20
ElseIf masuk = "y" Then
tinggi = 20
End If
sensor.Caption = tinggi
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Pengaturan pintu air
‘-----------------------------------------------------------------------------------------------------------
If Val(sensor.Caption) < Val(masukan.Caption) Then
GoTo buka
If Val(sensor.Caption) > Val(masukan.Caption) Then
GoTo tutup
Else: Comm1.Output = "S"
End If
End If
L8
buka:
If Val(sensor.Caption) < 19 Then
Comm1.Output = "R"
Else
Comm1.Output = "W"
End If
tutup:
Comm1.Output = "K"
Else
Comm1.Output = "V"
End If
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Pesan pemberitahuan
‘-----------------------------------------------------------------------------------------------------------
Select Case Val(sensor.Caption)
Case Is < 1
report.Visible = True
report.Caption = "SUNGAI KERING"
Case Is < 19
report.Visible = False
Case Is > 18
report.Visible = True
report.Caption = "SUNGAI MELUAP"
End Select
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Membuka data pembuat
‘-----------------------------------------------------------------------------------------------------------
Private Sub penulis_Click()
Tentang.Visible = True
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Membuka penggunaan program
‘-----------------------------------------------------------------------------------------------------------
Private Sub program_Click()
penggunaan.Visible = True
End
End Sub
L9
,-----------------------------------------------------------------------------------------------------------
‘Keluar dari program
‘-----------------------------------------------------------------------------------------------------------
Private Sub KELUAR_Click()
Comm1.Output = "S"
End
End Sub
‘-----------------------------------------------------------------------------------------------------------
PROGRAM PENGATURAN MANUAL :

,-----------------------------------------------------------------------------------------------------------
‘Setting komunikasi serial
,-----------------------------------------------------------------------------------------------------------
Private Sub Form_Load()
Dim a As Integer
a=0
Comm1.CommPort = 1
Comm1.Settings = "300,n,8,1"
Comm1.InputLen = 1
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Membuka pintu air
,-----------------------------------------------------------------------------------------------------------
Private Sub buka_MouseDown(Button As Integer, Shift As Integer, X As Single, Y As
Single)
Timerc.Enabled = False
If Val(sensor.Caption) > 18 Then
Comm1.Output = "T"
tampil.Caption = "Pintu tidak bisa di buka lagi"
Else
tampil.Caption = "Pintu air membuka"
Comm1.Output = "R"
End If
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Membuka pintu air selesai
,-----------------------------------------------------------------------------------------------------------
Private Sub buka_MouseUp(Button As Integer, Shift As Integer, X As Single, Y As
Single)
Timerc.Enabled = True
tampil.Caption = ""
End Sub
L10
,-----------------------------------------------------------------------------------------------------------
‘Menutup pintu air
,-----------------------------------------------------------------------------------------------------------
Private Sub tutup_MouseDown(Button As Integer, Shift As Integer, X As Single, Y As
Single)
tampil.Caption = "Pintu air tidak bisa di tutup lagi"
Comm1.Output = "S"
ElseIf Val(sensor.Caption) < 18 Then
tampil.Caption = "Pintu air menutup"
Comm1.Output = "K"
ElseIf Val(sensor.Caption) > 18 Then
tampil.Caption = "Pintu air menutup"
Comm1.Output = "V"
End If
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Menutup pintu air selesai
,-----------------------------------------------------------------------------------------------------------
Private Sub tutup_MouseUp(Button As Integer, Shift As Integer, X As Single, Y As
Single)
tampil.Caption = ""
Timerc.Enabled = True
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Pesan pemberitahu
,-----------------------------------------------------------------------------------------------------------
Private Sub Timera_Timer()
Text1.Text = masuk + Text1.Text
Select Case Val(sensor.Caption)
Case Is < 1
WARNING.Visible = True
WARNING.Caption = "SUNGAI KERING"
Case Is < 19
WARNING.Visible = False
Case Is > 18
WARNING.Visible = True
WARNING.Caption = "SUNGAI MELUAP"
End Select
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Pemantauan keinggian air
,-----------------------------------------------------------------------------------------------------------
L11
Private Sub TimerC_Timer()
If Val(sensor.Caption) > 18 Then
Comm1.Output = "T"
Else
Comm1.Output = "S"
End If
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Deklarasi ketinggian air
,-----------------------------------------------------------------------------------------------------------
Private Sub Timerb_Timer()
Dim tinggi, Text2 As Integer
Dim masuk As String
masuk = Comm1.Input
If masuk = "!" Then

tinggi = 0
ElseIf masuk = "#" Then
tinggi = 0
ElseIf masuk = "$" Then
tinggi = 1
ElseIf masuk = "%" Then
tinggi = 1
ElseIf masuk = "&" Then
tinggi = 1
ElseIf masuk = "'" Then
tinggi = 1
ElseIf masuk = "(" Then
tinggi = 2
ElseIf masuk = ")" Then
tinggi = 2
ElseIf masuk = "*" Then
tinggi = 2
ElseIf masuk = "+" Then
tinggi = 2
ElseIf masuk = "," Then
tinggi = 3
ElseIf masuk = "-" Then
tinggi = 3
ElseIf masuk = "." Then
tinggi = 3
ElseIf masuk = "/" Then
tinggi = 3
tinggi = 4
L12
tinggi = 4
tinggi = 4
tinggi = 4
tinggi = 5
tinggi = 5
tinggi = 5
tinggi = 5
tinggi = 6
tinggi = 6
ElseIf masuk = ":" Then
tinggi = 6
ElseIf masuk = ";" Then
tinggi = 6
ElseIf masuk = "<" Then
tinggi = 7
ElseIf masuk = "=" Then
tinggi = 7
ElseIf masuk = ">" Then
tinggi = 7
ElseIf masuk = "@" Then
tinggi = 8
ElseIf masuk = "A" Then
tinggi = 8
ElseIf masuk = "B" Then
tinggi = 8
ElseIf masuk = "C" Then
tinggi = 8
ElseIf masuk = "D" Then
tinggi = 9
ElseIf masuk = "E" Then
tinggi = 9
ElseIf masuk = "F" Then
tinggi = 9
ElseIf masuk = "G" Then
tinggi = 9
ElseIf masuk = "H" Then
tinggi = 10
L13
ElseIf masuk = "I" Then
tinggi = 10
ElseIf masuk = "J" Then
tinggi = 10
ElseIf masuk = "K" Then
tinggi = 10
ElseIf masuk = "L" Then
tinggi = 11
ElseIf masuk = "M" Then
tinggi = 11
ElseIf masuk = "N" Then
tinggi = 11
ElseIf masuk = "O" Then
tinggi = 11
ElseIf masuk = "P" Then
tinggi = 12
ElseIf masuk = "Q" Then
tinggi = 12
ElseIf masuk = "R" Then
tinggi = 12
ElseIf masuk = "S" Then
tinggi = 12
ElseIf masuk = "T" Then
tinggi = 13
ElseIf masuk = "U" Then
tinggi = 13
ElseIf masuk = "V" Then
tinggi = 13
ElseIf masuk = "W" Then
tinggi = 13
ElseIf masuk = "X" Then
tinggi = 14
ElseIf masuk = "Y" Then
tinggi = 14
ElseIf masuk = "Z" Then
tinggi = 14
ElseIf masuk = "[" Then
tinggi = 14
ElseIf masuk = "\" Then
tinggi = 15
ElseIf masuk = "]" Then
tinggi = 15
ElseIf masuk = "^" Then
tinggi = 15
ElseIf masuk = "_" Then
tinggi = 15
L14
ElseIf masuk = "`" Then
tinggi = 16
ElseIf masuk = "a" Then
tinggi = 16
ElseIf masuk = "b" Then
tinggi = 16
ElseIf masuk = "c" Then
tinggi = 17
ElseIf masuk = "d" Then
tinggi = 17
ElseIf masuk = "e" Then
tinggi = 17
ElseIf masuk = "f" Then
tinggi = 17
ElseIf masuk = "g" Then
tinggi = 18
ElseIf masuk = "h" Then
tinggi = 18
ElseIf masuk = "i" Then
tinggi = 18
ElseIf masuk = "j" Then
tinggi = 18
ElseIf masuk = "k" Then
tinggi = 19
ElseIf masuk = "l" Then
tinggi = 19
ElseIf masuk = "m" Then
tinggi = 19
ElseIf masuk = "n" Then
tinggi = 19
ElseIf masuk = "o" Then
tinggi = 20
ElseIf masuk = "p" Then
tinggi = 20
ElseIf masuk = "q" Then
tinggi = 20
ElseIf masuk = "r" Then
tinggi = 20
ElseIf masuk = "s" Then
tinggi = 20
ElseIf masuk = "t" Then
tinggi = 20
ElseIf masuk = "u" Then
tinggi = 20
ElseIf masuk = "v" Then
tinggi = 20
L15
ElseIf masuk = "w" Then
tinggi = 20
ElseIf masuk = "x" Then
tinggi = 20
ElseIf masuk = "y" Then
tinggi = 20
End If
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Keluar program
,-----------------------------------------------------------------------------------------------------------
Private Sub KELUAR_Click()
Comm1.Output = "S"
End
End Sub
,-----------------------------------------------------------------------------------------------------------
‘Berganti ke pengaturan otomatis
,-----------------------------------------------------------------------------------------------------------
Private Sub otomatis_Click()
Comm1.Output = "S"
Timera.Enabled = False
Timerb.Enabled = False
pengaturanmanual.Comm1.PortOpen = False
pengaturanmanual.Visible = False
pengatotomatis.Visible = True
pengatotomatis.Comm1.PortOpen = True
pengatotomatis.Timer1.Enabled = True
End Sub
,-----------------------------------------------------------------------------------------------------------
L16
;AT89S51 MICROCONTROLLER PROGRAM
;***********************************************************************
; PROGRAM PENGUBAH DATA PARAREL KE SERIAL
; TELEMETRI KETINGGIAN AIR SEBAGAI PENGATUR MODEL PINTU AIR
; BERBASIS MIKROKONTROLER AT89S51 DAN PC
;-----------------------------------------------------------------------------------------------------------
;NAMA : BRIATMA KURNIA PUTRA P
;NIM : 025114006
;***********************************************************************
ORG 00H ;MULAI PROGRAM

MOV TMOD,#20H ;TIMER 1 MODE, MODE2
MOV TH1,#-96 ;BAUD RATE 300BPS
MOV SCON,#50H ;PORT SERIAL, MODE 1
SETB TR1 ;AKTFKAN TIMER
SJMP KONVERSI
;=======================================================
ORG 30H ;PROGRAM UTAMA
KONVERSI:
MOV R1,#10H ;DEKLARASI KONTROL AWAL DATA DISIMPAN
MOV R2,#16
CLR P2.1 ;AWAL ADC KONVERSI
SETB P2.1
JB P2.0,$ ;AKHIR ADC KONVERSI
BACA:
CLR P2.2 ;BACA ADC
MOV A,P1
SETB P2.2 ;SELESAI BACA ADC
GESER: ;RATA2 4 DATA TERAKHIR
MOV 15H,10H
MOV 16H,11H
MOV 17H,12H
MOV 10H,A
MOV 11H,15H
MOV 12H,16H
MOV 13H,17H
MOV R0,#11H
MOV R1,#3
MOV 20H,#00H
L17
JUMLAH:
ADD A,@R0
JC TEMP
INC R0
DJNZ R1,JUMLAH
SJMP PUTAR
TEMP:
INC 20H
INC R0
DJNZ R1,JUMLAH
SJMP PUTAR
PUTAR: ;PEMBAGIAN 4
CLR C
MOV C,00H
RRC A
CLR C
MOV C,01H
RRC A
SJMP BANDING
BANDING: ;MENGHINDARI KARAKTER YANG TIDAK

;DIINGINKAN
CLR C
CJNE A,#1FH,CEK2 ;DATA SEBELUM ASCI 33 KIRIM DATA 33
JMP KIRIM33
CEK2:
CJNE A,#1EH,CEK3
SJMP KIRIM33
CEK3:
CJNE A,#20H,CEK4
SJMP KIRIM33
CEK4:
CJNE A,#22H,CEK5
SJMP KIRIM33
CEK5:
CJNE A,#3FH,KIRIM ;Menghindari data ASCI 63
SJMP KIRIM61 ;Kirim ASCI 61
KIRIM33:
MOV A,#21H
MOV SBUF,A
MOV P0,A
JNB TI,$
CLR TI
L18
JMP KONVERSI
KIRIM61:
MOV A,#3DH
MOV SBUF,A
MOV P0,A
JNB TI,$
CLR TI
JMP KONVERSI
KIRIM:
MOV SBUF,A ;KIRIM DATA SERIAL
MOV P0,A
JNB TI,$ ;TUNGGU TRANSMIT INTERUPT
CLR TI ;NOLKAN TI
JMP KONVERSI
END
L19
;***********************************************************************
; PROGRAM PENGENDALI ARAH PUTARAN MOTOR DC DAN BUZZER
; TELEMETRI KETINGGIAN AIR SEBAGAI PENGATUR MODEL PINTU AIR
; BERBASIS MIKROKONTROLER AT89S51 DAN PC
;-----------------------------------------------------------------------------------------------------------
;NAMA : BRIATMA KURNIA PUTRA P
;NIM : 025114006
;***********************************************************************
ORG 00H ;MULAI PROGRAM

SJMP MAIN
ORG 23H
SJMP SERINT
ORG 30H
MAIN:
MOV TMOD,#20H ;TIMER 1 MODE, MODE2
MOV TH1,#-96 ;BAUD RATE 300BPS
MOV SCON,#50H ;PORT SERIAL, MODE 1
MOV P1,#00000000B
SETB TR1
SETB ES ;AKTIFKAN INTERUPSI SERIAL
SETB EA ;AKTIFKAN INTERUPSI
DEAD:
SJMP DEAD
SERINT:
JB RI,RCV_CH ;BILA RECEIVE INETRUPT DITERIMA LOMPAT KE
;RCV_CH
CLR TI ;NOLKAN TI
RETI
RCV_CH:
CLR RI ;INTERUPSI SERIAL PENERIAMAN SIAP
MOV A,SBUF ;PINDAH DATA YANG DI TERIMA KE
;AKUMULATOR
CJNE A,#'K',BANDING2
MOV P1,#00000010b ;JIKA DATA DI TERIMA "K" PUTAR
;MOTOR CW
RETI
L20
BANDING2:
CJNE A,'R',BANDING3
MOV P1,#00000001b ;JIKA DATA DI TERIMA "R" PUTAR
;MOTOR CCW
RETI
BANDING3:
CJNE A,#'S',ALARM
MOV P1,#00000000b ;JIKA DATA DI TERIMA "S" MOTOR
;TIDAK BERPUTAR
RETI
ALARM:
CJNE A,#'T',ALARM2
MOV P1,#00000100b ;JIKA DATA DI TERIMA "T"
;BUNYIKAN BUZZER
RETI
ALARM2:
CJNE A,#'W',ALARM3
MOV P1,#00000101b ;JIKA DATA DITERIMA "W"
;BUNYIKAN BUZZER DAN PUTAR
;MOTOR CCW
RETI
ALARM3:
CJNE A,#'V',STOP
MOV P1,#00000110b ;JIKA DATA DITERIMA "V" BUNYIKAN
;BUZZER DAN PUTAR MOTOR CW
RETI
STOP:
MOV P1,#00000000b ;DATA YANG DITERIMA TAK
;DIKENAL MATIKAN BUZZER DAN
;MOTOR
RETI
END
L21
Telemetri Ketinggian Air Sebagai Pengatur Model Pintu Air
Rangkaian Pengirim Rangkaian Penerima
L22
Sensor Ketinggian Air
Model Pintu Air
L23
Rangkaian penerima dihubungkan ke motor DC
Rangkaian Pengirim dihubungkan dengan sensor ketinggian
L24
CA3140, CA3140A
Data Sheet September 1998 File Number 957.4
4.5MHz, BiMOS Operational Amplifier with Features

MOSFET Input/Bipolar Output • MOSFET Input Stage
- Very High Input Impedance (ZIN) -1.5TΩ (Typ)
The CA3140A and CA3140 are integrated circuit operational
- Very Low Input Current (Il) -10pA (Typ) at ±15V
amplifiers that combine the advantages of high voltage PMOS
- Wide Common Mode Input Voltage Range (VlCR) - Can be
transistors with high voltage bipolar transistors on a single Swung 0.5V Below Negative Supply Voltage Rail
monolithic chip. - Output Swing Complements Input Common Mode
The CA3140A and CA3140 BiMOS operational amplifiers Range
feature gate protected MOSFET (PMOS) transistors in the • Directly Replaces Industry Type 741 in Most
input circuit to provide very high input impedance, very low Applications
input current, and high speed performance. The CA3140A
and CA3140 operate at supply voltage from 4V to 36V (either Applications
single or dual supply). These operational amplifiers are • Ground-Referenced Single Supply Amplifiers in Automo-
internally phase compensated to achieve stable operation in bile and Portable Instrumentation
unity gain follower operation, and additionally, have access • Sample and Hold Amplifiers
terminal for a supplementary external capacitor if additional • Long Duration Timers/Multivibrators
frequency roll-off is desired. Terminals are also provided for (µseconds-Minutes-Hours)
use in applications requiring input offset voltage nulling. The • Photocurrent Instrumentation
use of PMOS field effect transistors in the input stage results • Peak Detectors
in common mode input voltage capability down to 0.5V below • Active Filters
the negative supply terminal, an important attribute for single • Comparators
supply applications. The output stage uses bipolar transistors • Interface in 5V TTL Systems and Other Low
and includes built-in protection against damage from load Supply Voltage Systems
terminal short circuiting to either supply rail or to ground. • All Standard Operational Amplifier Applications
The CA3140 Series has the same 8-lead pinout used for the • Function Generators
“741” and other industry standard op amps. The CA3140A and • Tone Controls
CA3140 are intended for operation at supply voltages up to 36V • Power Supplies
(±18V). • Portable Instruments
• Intrusion Alarm Systems
Ordering Information
Pinouts
PART NUMBER TEMP. PKG. CA3140 (METAL CAN)
(BRAND) RANGE (oC) PACKAGE NO. TOP VIEW
CA3140AE -55 to 125 8 Ld PDIP E8.3 TAB
STROBE
8
CA3140AM -55 to 125 8 Ld SOIC M8.15 OFFSET 1 7 V+
(3140A) NULL
CA3140AS -55 to 125 8 Pin Metal Can T8.C INV. 2 - 6 OUTPUT

INPUT +
CA3140AT -55 to 125 8 Pin Metal Can T8.C
NON-INV. 3 5 OFFSET
CA3140E -55 to 125 8 Ld PDIP E8.3 INPUT 4 NULL
CA3140M -55 to 125 8 Ld SOIC M8.15 V- AND CASE

(3140)
CA3140 (PDIP, SOIC)
CA3140M96 -55 to 125 8 Ld SOIC Tape TOP VIEW
(3140) and Reel
OFFSET
CA3140T -55 to 125 8 Pin Metal Can T8.C 1 8 STROBE
NULL
INV. INPUT 2 7 V+
-
NON-INV. +
3 6 OUTPUT
INPUT
4 OFFSET
V- 5
NULL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CA3140, CA3140A
Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) To (V- -0.5V) SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Metal Can Package . . . . . . . . . . . . . . . 170 85
Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite Maximum Junction Temperature (Metal Can Package). . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Operating Conditions Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications VSUPPLY = ±15V, TA = 25oC
TYPICAL VALUES
PARAMETER SYMBOL TEST CONDITIONS CA3140 CA3140A UNITS
Input Offset Voltage Adjustment Resistor Typical Value of Resistor 4.7 18 kΩ

Between Terminals 4 and 5 or 4 and 1 to
Adjust Max VIO
Input Resistance RI 1.5 1.5 TΩ
Input Capacitance CI 4 4 pF
Output Resistance RO 60 60 Ω
Equivalent Wideband Input Noise Voltage eN BW = 140kHz, RS = 1MΩ 48 48 µV

(See Figure 27)
Equivalent Input Noise Voltage (See Figure 35) eN RS = 100Ω f = 1kHz 40 40 nV/√Hz
f = 10kHz 12 12 nV/√Hz
Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA
IOM- Sink 18 18 mA
Gain-Bandwidth Product, (See Figures 6, 30) fT 4.5 4.5 MHz
Slew Rate, (See Figure 31) SR 9 9 V/µs
Sink Current From Terminal 8 To Terminal 4 to 220 220 µA

Swing Output Low
Transient Response (See Figure 28) tr RL = 2kΩ Rise Time 0.08 0.08 µs
CL = 100pF
OS Overshoot 10 10 %
Settling Time at 10VP-P, (See Figure 5) tS RL = 2kΩ To 1mV 4.5 4.5 µs

CL = 100pF
To 10mV 1.4 1.4 µs
Voltage Follower
Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified
CA3140 CA3140A
PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS
Input Offset Voltage |VIO| - 5 15 - 2 5 mV
Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA
Input Current II - 10 50 - 10 40 pA
Large Signal Voltage Gain (Note 3) AOL 20 100 - 20 100 - kV/V

(See Figures 6, 29)
86 100 - 86 100 - dB
2
CA3140, CA3140A
Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued)
CA3140 CA3140A
PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS

Common Mode Rejection Ratio CMRR - 32 320 - 32 320 µV/V
(See Figure 34)
70 90 - 70 90 - dB
Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V
Power-Supply Rejection Ratio, PSRR - 100 150 - 100 150 µV/V

∆VIO/∆VS (See Figure 36)
76 80 - 76 80 - dB
Max Output Voltage (Note 4) VOM+ +12 13 - +12 13 - V

(See Figures 2, 8)
VOM- -14 -14.4 - -14 -14.4 - V
Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA
Device Dissipation PD - 120 180 - 120 180 mW
Input Offset Voltage Temperature Drift ∆VIO/∆T - 8 - - 6 - µV/oC
NOTES:
3. At VO = 26VP-P , +12V, -14V and RL = 2kΩ.
4. At RL = 2kΩ.
Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC
TYPICAL VALUES
PARAMETER SYMBOL CA3140 CA3140A UNITS
Input Offset Voltage |VIO| 5 2 mV
Input Offset Current |IIO| 0.1 0.1 pA
Input Current II 2 2 pA
Input Resistance RI 1 1 TΩ
Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V
100 100 dB
Common Mode Rejection Ratio CMRR 32 32 µV/V
90 90 dB
Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR 100 100 µV/V

∆VIO/∆VS
80 80 dB
Maximum Output Voltage (See Figures 2, 8) VOM+ 3 3 V
VOM- 0.13 0.13 V
Maximum Output Current: Source IOM+ 10 10 mA
Sink I
OM- 1 1 mA
Slew Rate (See Figure 31) SR 7 7 V/µs
Gain-Bandwidth Product (See Figure 30) fT 3.7 3.7 MHz
Supply Current (See Figure 32) I+ 1.6 1.6 mA
Device Dissipation PD 8 8 mW
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 µA
3
CA3140, CA3140A
Block Diagram
2mA 4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200µA 1.6mA 200µA 2µA 2mA

+
3
A≈
INPUT A ≈ 10 10,000 A≈1 6 OUTPUT
-
2
C1
12pF
4 V-
5 1 8 STROBE
OFFSET
NULL
Schematic Diagram
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK
7 V+
D1 D7
R13
5K
Q3 R9 Q20
Q1 Q2
50Ω
D8
R10
Q4 1K
Q6 Q5 R14
R12 20K
Q19 R11
20Ω 12K
Q7
Q21
Q17
R1
8K Q8 R8
1K Q
18
6 OUTPUT
D2 D3 D4
D5
INVERTING
2
INPUT
- Q9 Q10
+
NON-INVERTING 3
INPUT C1
R2 R3
500Ω 500Ω 12pF
Q14 Q15 Q16
Q13
Q11 Q12 D6
R4 R5 R6 R7
500Ω 500Ω 50Ω 30Ω
5 1 8 4
OFFSET NULL STROBE V-
NOTE: All resistance values are in ohms.
4
CA3140, CA3140A
Application Information When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q16 is the current
Circuit Description
sinking element. Transistor Q16 is mirror connected to D6, R7,
As shown in the block diagram, the input terminals may be with current fed by way of Q21, R12, and Q20. Transistor Q20, in
operated down to 0.5V below the negative supply rail. Two turn, is biased by current flow through R13, zener D8, and R14.
class A amplifier stages provide the voltage gain, and a The dynamic current sink is controlled by voltage level sensing.
unique class AB amplifier stage provides the current gain For purposes of explanation, it is assumed that output Terminal
necessary to drive low-impedance loads. 6 is quiescently established at the potential midpoint between
A biasing circuit provides control of cascoded constant current the V+ and V- supply rails. When output current sinking mode
flow circuits in the first and second stages. The CA3140 operation is required, the collector potential of transistor Q13 is
includes an on chip phase compensating capacitor that is driven below its quiescent level, thereby causing Q17, Q18 to
sufficient for the unity gain voltage follower configuration. decrease the output voltage at Terminal 6. Thus, the gate
terminal of PMOS transistor Q21 is displaced toward the V- bus,
Input Stage
thereby reducing the channel resistance of Q21. As a
The schematic diagram consists of a differential input stage consequence, there is an incremental increase in current flow
using PMOS field-effect transistors (Q9, Q10) working into a through Q20, R12, Q21, D6, R7, and the base of Q16. As a
mirror pair of bipolar transistors (Q11, Q12) functioning as load result, Q16 sinks current from Terminal 6 in direct response to
resistors together with resistors R2 through R5. The mirror pair the incremental change in output voltage caused by Q18. This
transistors also function as a differential-to-single-ended sink current flows regardless of load; any excess current is
converter to provide base current drive to the second stage internally supplied by the emitter-follower Q18. Short circuit
bipolar transistor (Q13). Offset nulling, when desired, can be protection of the output circuit is provided by Q19, which is
effected with a 10kΩ potentiometer connected across driven into conduction by the high voltage drop developed
Terminals 1 and 5 and with its slider arm connected to Terminal across R11 under output short circuit conditions. Under these
4. Cascode-connected bipolar transistors Q2, Q5 are the conditions, the collector of Q19 diverts current from Q4 so as to
constant current source for the input stage. The base biasing reduce the base current drive from Q17, thereby limiting current
circuit for the constant current source is described flow in Q18 to the short circuited load terminal.
subsequently. The small diodes D3, D4, D5 provide gate oxide
protection against high voltage transients, e.g., static electricity. Bias Circuit
Quiescent current in all stages (except the dynamic current
Second Stage
sink) of the CA3140 is dependent upon bias current flow in R1.
Most of the voltage gain in the CA3140 is provided by the
The function of the bias circuit is to establish and maintain
second amplifier stage, consisting of bipolar transistor Q13
constant current flow through D1, Q6, Q8 and D2. D1 is a diode
and its cascode connected load resistance provided by
connected transistor mirror connected in parallel with the base
bipolar transistors Q3, Q4. On-chip phase compensation,
emitter junctions of Q1, Q2, and Q3. D1 may be considered as a
sufficient for a majority of the applications is provided by C1.
current sampling diode that senses the emitter current of Q6
Additional Miller-Effect compensation (roll off) can be
and automatically adjusts the base current of Q6 (via Q1) to
accomplished, when desired, by simply connecting a small
maintain a constant current through Q6, Q8, D2. The base
capacitor between Terminals 1 and 8. Terminal 8 is also
currents in Q2, Q3 are also determined by constant current flow
used to strobe the output stage into quiescence. When
D1. Furthermore, current in diode connected transistor Q2
terminal 8 is tied to the negative supply rail (Terminal 4) by
establishes the currents in transistors Q14 and Q15.
mechanical or electrical means, the output Terminal 6
swings low, i.e., approximately to Terminal 4 potential. Typical Applications
Output Stage Wide dynamic range of input and output characteristics with
The CA3140 Series circuits employ a broad band output stage the most desirable high input impedance characteristics is
that can sink loads to the negative supply to complement the achieved in the CA3140 by the use of an unique design based
capability of the PMOS input stage when operating near the upon the PMOS Bipolar process. Input common mode voltage
negative rail. Quiescent current in the emitter-follower cascade range and output swing capabilities are complementary,
circuit (Q17, Q18) is established by transistors (Q14, Q15) allowing operation with the single supply down to 4V.
whose base currents are “mirrored” to current flowing through
The wide dynamic range of these parameters also means
diode D2 in the bias circuit section. When the CA3140 is
that this device is suitable for many single supply
operating such that output Terminal 6 is sourcing current,
applications, such as, for example, where one input is driven
transistor Q18 functions as an emitter-follower to source current
below the potential of Terminal 4 and the phase sense of the
from the V+ bus (Terminal 7), via D7, R9, and R11. Under these
output signal must be maintained – a most important
conditions, the collector potential of Q13 is sufficiently high to
consideration in comparator applications.
permit the necessary flow of base current to emitter follower
Q17 which, in turn, drives Q18.
5
CA3140, CA3140A
Output Circuit Considerations level shifting circuitry usually associated with the 741 series
Excellent interfacing with TTL circuitry is easily achieved of operational amplifiers.
with a single 6.2V zener diode connected to Terminal 8 as Figure 4 shows some typical configurations. Note that a
shown in Figure 1. This connection assures that the series resistor, RL, is used in both cases to limit the drive
maximum output signal swing will not go more positive than available to the driven device. Moreover, it is recommended
the zener voltage minus two base-to-emitter voltage drops that a series diode and shunt diode be used at the thyristor
within the CA3140. These voltages are independent of the input to prevent large negative transient surges that can
operating supply voltage. appear at the gate of thyristors, from damaging the
integrated circuit.
V+
5V TO 36V
LOGIC Offset Voltage Nulling
7
SUPPLY
2 8 6.2V 5V
The input offset voltage can be nulled by connecting a 10kΩ
potentiometer between Terminals 1 and 5 and returning its
CA3140 6 TYPICAL wiper arm to terminal 4, see Figure 3A. This technique,
TTL GATE
3 ≈ 5V however, gives more adjustment range than required and
4 therefore, a considerable portion of the potentiometer
rotation is not fully utilized. Typical values of series resistors
(R) that may be placed at either end of the potentiometer,
FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
see Figure 3B, to optimize its utilization range are given in
TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT the Electrical Specifications table.
SWING TO TTL LEVELS
An alternate system is shown in Figure 3C. This circuit uses
1000 only one additional resistor of approximately the value
OUTPUT STAGE TRANSISTOR (Q15, Q16)
SUPPLY VOLTAGE (V-) = 0V

TA = 25oC
shown in the table. For potentiometers, in which the
resistance does not drop to 0Ω at either end of rotation, a
SATURATION VOLTAGE (mV)
value of resistance 10% lower than the values shown in the

SUPPLY VOLTAGE (V+) = +5V
100 +15V table should be used.
+30V
Low Voltage Operation
Operation at total supply voltages as low as 4V is possible
10 with the CA3140. A current regulator based upon the PMOS
threshold voltage maintains reasonable constant operating
current and hence consistent performance down to these
lower voltages.
1
0.01 0.1 1.0 10 The low voltage limitation occurs when the upper extreme of
LOAD (SINKING) CURRENT (mA)
the input common mode voltage range extends down to the
FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15 voltage at Terminal 4. This limit is reached at a total supply
AND Q16) vs LOAD CURRENT voltage just below 4V. The output voltage range also begins to
extend down to the negative supply rail, but is slightly higher
Figure 2 shows output current sinking capabilities of the
than that of the input. Figure 8 shows these characteristics and
CA3140 at various supply voltages. Output voltage swing to
shows that with 2V dual supplies, the lower extreme of the input
the negative supply rail permits this device to operate both
common mode voltage range is below ground potential.
power transistors and thyristors directly without the need for
V+
V+ V+
2 7
2 7 2 7
CA3140 6
CA3140 6 CA3140 6
3 4
3 4 5 3 4
5 1 5
1 R R 1
10kΩ 10kΩ 10kΩ
R
V- V- V-
FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION
FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS
6
CA3140, CA3140A
RS V+ +HV
7 LOAD
LOAD 2
30V
NO LOAD MT2 CA3140 6
120VAC 7 RL
2
3
CA3140 6 4
MT1
RL
3
4
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER
+15V
7
3 0.1µF
SIMULATED
10kΩ LOAD
CA3140 6
2 100pF 2kΩ
4
0.1µF
-15V
2kΩ
LOAD RESISTANCE (RL) = 2kΩ
LOAD CAPACITANCE (CL) = 100pF
0.05µF
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC INVERTING
10 5kΩ
1mV 1mV
8
10mV 10mV +15V
6
7
INPUT VOLTAGE (V)
4 0.1µF
2 SIMULATED
2 5kΩ LOAD
FOLLOWER CA3140 6
0 200Ω
INVERTING
-2 3 100pF 2kΩ
4
-4 0.1µF
4.99kΩ 5.11kΩ
-6 1mV 1mV -15V
-8 10mV 10mV SETTLING POINT
-10 D1 D2
0.1 1.0 10
SETTLING TIME (µs) 1N914 1N914
FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS

FIGURE 5. SETTLING TIME vs INPUT VOLTAGE
Bandwidth and Slew Rate are largely due to the high combination of high gain and wide
For those cases where bandwidth reduction is desired, for bandwidth of the CA3140; as shown in Figure 6.
example, broadband noise reduction, an external capacitor Input Circuit Considerations
connected between Terminals 1 and 8 can reduce the open
As mentioned previously, the amplifier inputs can be driven
loop -3dB bandwidth. The slew rate will, however, also be
below the Terminal 4 potential, but a series current limiting
proportionally reduced by using this additional capacitor.
resistor is recommended to limit the maximum input terminal
Thus, a 20% reduction in bandwidth by this technique will
current to less than 1mA to prevent damage to the input
also reduce the slew rate by about 20%.
protection circuitry.
Figure 5 shows the typical settling time required to reach
Moreover, some current limiting resistance should be
1mV or 10mV of the final value for various levels of large
provided between the inverting input and the output when
signal inputs for the voltage follower and inverting unity gain
the CA3140 is used as a unity gain voltage follower. This
amplifiers. The exceptionally fast settling time characteristics
resistance prevents the possibility of extremely large input
7
CA3140, CA3140A
signal transients from forcing a signal through the input differential input voltages that are sustained over long
protection network and directly driving the internal constant periods at elevated temperatures.
current source which could result in positive feedback via the
Both applied voltage and temperature accelerate these
output terminal. A 3.9kΩ resistor is sufficient.
changes. The process is reversible and offset voltage shifts of
The typical input current is on the order of 10pA when the the opposite polarity reverse the offset. Figure 9 shows the
inputs are centered at nominal device dissipation. As the typical offset voltage change as a function of various stress
output supplies load current, device dissipation will increase, voltages at the maximum rating of 125oC (for metal can); at
raising the chip temperature and resulting in increased input lower temperatures (metal can and plastic), for example, at
current. Figure 7 shows typical input terminal current versus 85oC, this change in voltage is considerably less. In typical
ambient temperature for the CA3140. linear applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the
It is well known that MOSFET devices can exhibit slight
same magnitude as those encountered in an operational
changes in characteristics (for example, small changes in
amplifier employing a bipolar transistor input stage.
input offset voltage) due to the application of large
OPEN LOOP PHASE

-75 10K
SUPPLY VOLTAGE: VS = ±15V SUPPLY VOLTAGE: VS = ±15V
TA = 25oC -90
(DEGREES)
OPEN LOOP VOLTAGE GAIN (dB)
RL = 2kΩ,
100 -105
φOL CL = 0pF
-120 1K
INPUT CURRENT (pA)

80 -135
-150
60 100
RL = 2kΩ,
40 CL = 100pF
10
20
0 1
101 102 103 104 105 106 107 108 -60 -40 -20 0 20 40 60 80 100 120 140
FREQUENCY (Hz) TEMPERATURE (oC)
FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs FIGURE 7. INPUT CURRENT vs TEMPERATURE
FREQUENCY
INPUT AND OUTPUT VOLTAGE EXCURSIONS
INPUT AND OUTPUT VOLTAGE EXCURSIONS
RL = ∞
0 1.5
-0.5 +VICR AT TA = 125oC -VICR AT TA = 125oC

FROM TERMINAL 7 (V+)
+VOUT AT TA = 125oC 1.0

FROM TERMINAL 4 (V-)
+VICR AT TA = 25oC -VICR AT TA = 25oC

+VOUT AT TA = 25oC
-1.0 +VICR AT TA = -55oC 0.5 -VOUT FOR -VICR AT TA = -55oC
+VOUT AT TA = -55oC
TA = -55oC to 125oC
-1.5 0
-2.0 -0.5
-2.5 -1.0
-3.0 -1.5
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V+, V-) SUPPLY VOLTAGE (V+, V-)
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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8
CA3140, CA3140A
7 placed across the input to the CA3080A to give a logarithmic

TA = 125oC analog indication of the function generator’s frequency.
6 FOR METAL CAN PACKAGES
OFFSET VOLTAGE SHIFT (mV)
DIFFERENTIAL DC VOLTAGE Analog frequency readout is readily accomplished by the

(ACROSS TERMINALS 2 AND 3) = 2V
5
OUTPUT STAGE TOGGLED
means described above because the output current of the
CA3080A varies approximately one decade for each 60mV
4 change in the applied voltage, VABC (voltage between
Terminals 5 and 4 of the CA3080A of the function generator).
3
Therefore, six decades represent 360mV change in VABC.
2
DIFFERENTIAL DC VOLTAGE Now, only the reference voltage must be established to set
1
(ACROSS TERMINALS 2 AND 3) = 0V the lower limit on the meter. The three remaining transistors
OUTPUT VOLTAGE = V+ / 2
from the CA3086 Array used in the sweep generator are
0 used for this reference voltage. In addition, this reference
0 500 1000 1500 2000 2500 3000 3500 4000 4500
generator arrangement tends to track ambient temperature
TIME (HOURS)
variations, and thus compensates for the effects of the
FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE normal negative temperature coefficient of the CA3080A
SHIFT vs OPERATING LIFE
VABC terminal voltage.
Super Sweep Function Generator
Another output voltage from the reference generator is used
A function generator having a wide tuning range is shown in to insure temperature tracking of the lower end of the
Figure 10. The 1,000,000/1 adjustment range is Frequency Adjustment Potentiometer. A large series
accomplished by a single variable potentiometer or by an resistance simulates a current source, assuring similar
auxiliary sweeping signal. The CA3140 functions as a non- temperature coefficients at both ends of the Frequency
inverting readout amplifier of the triangular signal developed Adjustment Control.
across the integrating capacitor network connected to the
output of the CA3080A current source. To calibrate this circuit, set the Frequency Adjustment
Potentiometer at its low end. Then adjust the Minimum
Buffered triangular output signals are then applied to a Frequency Calibration Control for the lowest frequency. To
second CA3080 functioning as a high speed hysteresis establish the upper frequency limit, set the Frequency
switch. Output from the switch is returned directly back to the Adjustment Potentiometer to its upper end and then adjust
input of the CA3080A current source, thereby, completing the Maximum Frequency Calibration Control for the
the positive feedback loop maximum frequency. Because there is interaction among
The triangular output level is determined by the four 1N914 these controls, repetition of the adjustment procedure may
level limiting diodes of the second CA3080 and the resistor be necessary. Two adjustments are used for the meter. The
divider network connected to Terminal No. 2 (input) of the meter sensitivity control sets the meter scale width of each
CA3080. These diodes establish the input trip level to this decade, while the meter position control adjusts the pointer
switching stage and, therefore, indirectly determine the on the scale with negligible effect on the sensitivity
amplitude of the output triangle. adjustment. Thus, the meter sensitivity adjustment control
calibrates the meter so that it deflects 1/6 of full scale for
Compensation for propagation delays around the entire loop each decade change in frequency.
is provided by one adjustment on the input of the CA3080.
This adjustment, which provides for a constant generator Sine Wave Shaper
amplitude output, is most easily made while the generator is The circuit shown in Figure 12 uses a CA3140 as a voltage
sweeping. High frequency ramp linearity is adjusted by the follower in combination with diodes from the CA3019 Array
single 7pF to 60pF capacitor in the output of the CA3080A. to convert the triangular signal from the function generator to
a sine-wave output signal having typically less than 2% THD.
It must be emphasized that only the CA3080A is
The basic zero crossing slope is established by the 10kΩ
characterized for maximum output linearity in the current
potentiometer connected between Terminals 2 and 6 of the
generator function.
CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer
Meter Driver and Buffer Amplifier from Terminal 2 to ground. Two break points are established
Figure 11 shows the CA3140 connected as a meter driver by diodes D1 through D4. Positive feedback via D5 and D6
and buffer amplifier. Low driving impedance is required of establishes the zero slope at the maximum and minimum
the CA3080A current source to assure smooth operation of levels of the sine wave. This technique is necessary because
the Frequency Adjustment Control. This low-driving the voltage follower configuration approaches unity gain
impedance requirement is easily met by using a CA3140 rather than the zero gain required to shape the sine wave at
connected as a voltage follower. Moreover, a meter may be the two extremes.
9
CA3140, CA3140A
CENTERING
-15V 10kΩ +15V
HIGH
7.5kΩ +15V +15V FREQUENCY
LEVEL 62kΩ 10kΩ
360Ω 0.1 910kΩ
7 µF 7-60pF
3 + 7
15kΩ 5 EXTERNAL
360Ω CA3080A 6 3 + 7
51 OUTPUT
2 - 7-60 CA3140 6 2 -
4 pF
pF 2 - 11kΩ CA3080 6
5 10kΩ 11kΩ 3 +
2MΩ HIGH 4
4 2.7kΩ
SYMMETRY -15V FREQ. 0.1
-15V EXTERNAL
+15V SHAPE -15V µF -15V
OUTPUT 13kΩ TO OUTPUT
2kΩ
100kΩ
AMPLIFIER
FROM BUFFER METER FREQUENCY
DRIVER (OPTIONAL) ADJUSTMENT 5.1kΩ TO
39kΩ 120Ω 10kΩ SINE WAVE
SHAPER 1N914
-15V +15V OUTPUT
AMPLIFIER
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
FIGURE 10A. CIRCUIT
FREQUENCY
ADJUSTMENT
Top Trace: Output at junction of 2.7Ω and 51Ω resistors;

5V/Div., 500ms/Div. +15V
METER DRIVER
POWER
AND BUFFER
Center Trace: External output of triangular function generator; SUPPLY ±15V
AMPLIFIER M
2V/Div., 500ms/Div. -15V
Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div. FUNCTION
FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING GENERATOR
WIDEBAND
LINE DRIVER
SINE WAVE
SHAPER
51Ω
GATE DC LEVEL
FINE SWEEP
SWEEP ADJUST
RATE GENERATOR
OFF INT.
EXTERNAL
COARSE V- EXT. INPUT
RATE
SWEEP
1V/Div., 1s/Div. LENGTH
Three tone test signals, highest frequency ≥0.5MHz. Note the slight V-
asymmetry at the three second/cycle signal. This asymmetry is due to
slightly different positive and negative integration from the CA3080A
and from the PC board and component leakages at the 100pA level.
FIGURE 10C. FUNCTION GENERATOR WITH FIXED FIGURE 10D. INTERCONNECTIONS
FREQUENCIES
FIGURE 10. FUNCTION GENERATOR
10
CA3140, CA3140A
FREQUENCY
500kΩ CALIBRATION
MAXIMUM
FREQUENCY 620kΩ
51kΩ 7
ADJUSTMENT TO CA3080A +15V -15V
10kΩ 3 + OF FUNCTION CA3080A
0.1µF
CA3140 6 GENERATOR
SWEEP IN (FIGURE 10) 7 5.6kΩ
3MΩ 2 - 4.7kΩ 4 3 +
7.5kΩ
5.1kΩ CA3140 6
4 5
TO
+15V 2 - 4 SUBSTRATE WIDEBAND
2kΩ METER 620Ω
0.1µF OF CA3019 OUTPUT
SENSITIVITY
12kΩ ADJUSTMENT 0.1µF AMPLIFIER
1kΩ 7
FREQUENCY 2.4kΩ -15V 10kΩ
CALIBRATION 200µA +15V
M METER R3 10kΩ
MINIMUM EXTERNAL
2.5 100 1MΩ
kΩ 11 OUTPUT
kΩ D1 D4
9 9.1kΩ
510Ω -15V
510Ω 6 5 8 2
R1
8 10 14 10kΩ
2kΩ D3 D6 D2 430Ω
6 12 9 1
METER R2
7 POSITION 3.6kΩ 13 1kΩ
ADJUSTMENT 3 4
3/ OF CA3086 D
5 CA3019 5
-15V DIODE ARRAY
FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER
750kΩ
“LOG”
100kΩ
SAWTOOTH 18MΩ
1N914
1MΩ 100kΩ FINE
RATE
22MΩ
1N914 SAWTOOTH 8.2kΩ

0.47µF
SYMMETRY +15V SAWTOOTH AND
RAMP LOW LEVEL
SET (-14.5V)
0.047µF COARSE 50kΩ
RATE
4700pF
470pF 75kΩ
SAWTOOTH 51kΩ
+15V
0.1
µF “LOG”+15V
+15V
7
2 - TRIANGLE 36kΩ 7
CA3140 6 3 - 10kΩ GATE
3 + 100kΩ CA3140 6 PULSE
4 30kΩ OUTPUT
0.1 TO OUTPUT 2 + 4
µF 50kΩ AMPLIFIER
LOG -15V
-15V 10kΩ
RATE
ADJUST EXTERNAL OUTPUT
43kΩ
10kΩ TO FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
-15V
7 +15V
3 +
CA3140 6
2 - 4 51kΩ 6.8kΩ 91kΩ 10kΩ
LOGVIO 5
1 TRIANGLE
25kΩ
5 1
3.9Ω TRANSISTORS SAWTOOTH
4 2 FROM CA3086
-15V ARRAY
100Ω “LOG”
390Ω 3
FIGURE 13. SWEEPING GENERATOR
11
CA3140, CA3140A
This circuit can be adjusted most easily with a distortion

analyzer, but a good first approximation can be made by
comparing the output signal with that of a sine wave VOLTAGE
REFERENCE ADJUSTMENT
generator. The initial slope is adjusted with the VOLTAGE 7
potentiometer R1, followed by an adjustment of R2. The final 3 +
REGULATED
slope is established by adjusting R3, thereby adding INPUT CA3140 6 OUTPUT
additional segments that are contributed by these diodes. 2 -
4
Because there is some interaction among these controls,
repetition of the adjustment procedure may be necessary.
Sweeping Generator
Figure 13 shows a sweeping generator. Three CA3140s are FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
SHOWING VOLTAGE FOLLOWER CONFIGURATION
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a hysteresis switch that Essentially, the regulators, shown in Figures 16 and 17, are
determines the starting and stopping points of the sweep. A connected as non inverting power operational amplifiers with a
third CA3140 is used as a logarithmic shaping network for gain of 3.2. An 8V reference input yields a maximum output
the log function. Rates and slopes, as well as sawtooth, voltage slightly greater than 25V. As a voltage follower, when
triangle, and logarithmic sweeps are generated by this the reference input goes to 0V the output will be 0V. Because
circuit. the offset voltage is also multiplied by the 3.2 gain factor, a
potentiometer is needed to null the offset voltage.
Wideband Output Amplifier
Series pass transistors with high ICBO levels will also
Figure 14 shows a high slew rate, wideband amplifier
prevent the output voltage from reaching zero because there
suitable for use as a 50Ω transmission line driver. This
is a finite voltage drop (VCESAT) across the output of the
circuit, when used in conjunction with the function generator
CA3140 (see Figure 2). This saturation voltage level may
and sine wave shaper circuits shown in Figures 10 and 12
indeed set the lowest voltage obtainable.
provides 18VP-P output open circuited, or 9VP-P output
when terminated in 50Ω. The slew rate required of this The high impedance presented by Terminal 8 is
amplifier is 28V/µs (18VP-P x π x 0.5MHz). advantageous in effecting current limiting. Thus, only a small
+15V signal transistor is required for the current-limit sensing
+ 50µF 2.2 amplifier. Resistive decoupling is provided for this transistor
SIGNAL
LEVEL - 25V kΩ 2N3053
ADJUSTMENT
to minimize damage to it or the CA3140 in the event of
unusual input or output transients on the supply rail.
2.5kΩ 3 + 7 1N914 2.7Ω OUT
51Ω
CA3140 6 Figures 16 and 17, show circuits in which a D2201 high speed
200Ω 1N914 2.7Ω 2W
2 - 4 diode is used for the current sensor. This diode was chosen
8
1 - 50µF for its slightly higher forward voltage drop characteristic, thus
+ 25V 2.2
OUTPUT
kΩ
2N4037 giving greater sensitivity. It must be emphasized that heat
DC LEVEL +15V 2.4pF
ADJUSTMENT 3kΩ 2pF sinking of this diode is essential to minimize variation of the
-15V
current trip point due to internal heating of the diode. That is,
-15V
1.8kΩ NOMINAL BANDWIDTH = 10MHz
1A at 1V forward drop represents one watt which can result in
200Ω tr = 35ns significant regenerative changes in the current trip point as the
diode temperature rises. Placing the small signal reference
amplifier in the proximity of the current sensing diode also
FIGURE 14. WIDEBAND OUTPUT AMPLIFIER helps minimize the variability in the trip level due to the
Power Supplies negative temperature coefficient of the diode. In spite of those
limitations, the current limiting point can easily be adjusted
High input impedance, common mode capability down to the over the range from 10mA to 1A with a single adjustment
negative supply and high output drive current capability are potentiometer. If the temperature stability of the current
key factors in the design of wide range output voltage limiting system is a serious consideration, the more usual
supplies that use a single input voltage to provide a current sampling resistor type of circuitry should be employed.
regulated output voltage that can be adjusted from
A power Darlington transistor (in a metal can with heatsink),
essentially 0V to 24V.
is used as the series pass element for the conventional
Unlike many regulator systems using comparators having a current limiting system, Figure 16, because high power
bipolar transistor input stage, a high impedance reference Darlington dissipation will be encountered at low output
voltage divider from a single supply can be used in voltage and high currents.
connection with the CA3140 (see Figure 15).
12
CA3140, CA3140A
A small heat sink VERSAWATT transistor is used as the regulation also remains constant. Line regulation is 0.1% per
series pass element in the fold back current system, Figure volt. Hum and noise voltage is less than 200µV as read with a
17, since dissipation levels will only approach 10W. In this meter having a 10MHz bandwidth.
system, the D2201 diode is used for current sampling.
Figure 18A shows the turn ON and turn OFF characteristics
Foldback is provided by the 3kΩ and 100kΩ divider network
of both regulators. The slow turn on rise is due to the slow
connected to the base of the current sensing transistor.
rate of rise of the reference voltage. Figure 18B shows the
Both regulators provide better than 0.02% load regulation. transient response of the regulator with the switching of a
Because there is constant loop gain at all voltage settings, the 20Ω load at 20V output.
2N6385 OUTPUT ⇒ 0V TO 25V

CURRENT “FOLDBACK” CURRENT
POWER DARLINGTON LIMITING 25V AT 1A
LIMITER
ADJUST OUTPUT “FOLDS BACK”
0.1 ⇒ 24V 2N5294 D2201 TO 40mA
D2201 AT 1A +30V 2 3
+30V 3 2
1kΩ 200Ω
75Ω 1kΩ 1kΩ 1 1
100kΩ 3kΩ
1kΩ
3kΩ 2 100kΩ 2N2102
2N2102
3 1kΩ
100Ω 1kΩ 8
1 8 7 56pF 180kΩ
7 56pF 180kΩ
2
2 6 CA3140 1kΩ
6 1kΩ 82kΩ
CA3140 82kΩ +
2.7kΩ 10µF 5 3
+
2.7kΩ 10µF 5 3 - 100kΩ
1
- 100kΩ
1 4
4 INPUT
INPUT VOLTAGE
VOLTAGE + ADJUST +
+ ADJUST + 2.2kΩ 5µF 50kΩ 250µF
2.2kΩ 5µF 50kΩ 250µF - -
- - 10 11 1 2 14
100kΩ
100kΩ
10 11 1 2 14
12
12 9 3 0.01µF
9 3 0.01µF
8 7 5 13
8 7 5 13
6 4 CA3086
6 4 CA3086
1kΩ
1kΩ
62kΩ
62kΩ
HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION
HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION (MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD)
(MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD) LINE REGULATION 0.1%/V <0.02%
LINE REGULATION 0.1%/V <0.02%
FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK”
CURRENT LIMITING
Top Trace: Output Voltage;

5V/Div., 1s/Div. 200mV/Div., 5µs/Div.
FIGURE 18A. SUPPLY TURN-ON AND TURNOFF Bottom Trace: Collector of load switching transistor, load = 1A;
CHARACTERISTICS 5V/Div., 5µs/Div.
FIGURE 18B. TRANSIENT RESPONSE

FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17
13
CA3140, CA3140A
Tone Control Circuits Bass treble boost and cut are ±15dB at 100Hz and 10kHz,
High slew rate, wide bandwidth, high output voltage respectively. Full peak-to-peak output is available up to at
capability and high input impedance are all characteristics least 20kHz due to the high slew rate of the CA3140. The
required of tone control amplifiers. Two tone control circuits amplifier gain is 3dB down from its “flat” position at 70kHz.
that exploit these characteristics of the CA3140 are shown in Figure 19 shows another tone control circuit with similar
Figures 19 and 20. boost and cut specifications. The wideband gain of this
The first circuit, shown in Figure 20, is the Baxandall tone circuit is equal to the ultimate boost or cut plus one, which in
control circuit which provides unity gain at midband and this case is a gain of eleven. For 20dB boost and cut, the
uses standard linear potentiometers. The high input input loading of this circuit is essentially equal to the value of
impedance of the CA3140 makes possible the use of low- the resistance from Terminal No. 3 to ground. A detailed
cost, low-value, small size capacitors, as well as reduced analysis of this circuit is given in “An IC Operational
load of the driving stage. Transconductance Amplifier (OTA) With Power Capability” by
L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast
and Television Receivers, Vol. BTR-18, No. 3, August, 1972.
FOR SINGLE SUPPLY

+30V NOTES:
2.2MΩ
5. 20dB Flat Position Gain.
7 6. ±15dB Bass and Treble Boost and Cut
0.005µF 0.1µF
3 + at 100Hz and 10kHz, respectively.
5.1 CA3140 6 7. 25VP-P output at 20kHz.
MΩ 2 - 8. -3dB at 24kHz from 1kHz reference.
4
FOR DUAL SUPPLIES

BOOST TREBLE CUT
200kΩ +15V
0.012µF (LINEAR) 0.001µF
0.1 100 0.005µF 7

2.2MΩ 18kΩ 100pF 0.1µF
µF pF 3 +
CA3140 6
5.1MΩ
2 -
4
0.1µF
0.022µF 0.0022µF
2µF -15V
- +
10kΩ 1MΩ 100kΩ TONE CONTROL NETWORK
CCW (LOG)
BOOST BASS CUT
TONE CONTROL NETWORK
FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
FOR SINGLE SUPPLY
BOOST BASS CUT

(LINEAR)
0.047µF 240kΩ 5MΩ 240kΩ
FOR DUAL SUPPLIES
2.2MΩ +32V
750 750 +15V
pF pF
7 0.1
µF 7
3 + 0.1µF
3 +
0.1 2.2 CA3140 6
CA3140 6
µF MΩ 2 - 0.047µF
2.2MΩ TONE CONTROL -
2
4 NETWORK
4
0.1µF
20pF NOTES: -15V
9. ±15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively.
51kΩ 5MΩ 51kΩ
(LINEAR) 10. 25VP-P Output at 20kHz.
BOOST TREBLE CUT 11. -3dB at 70kHz from 1kHz Reference.
TONE CONTROL NETWORK 12. 0dB Flat Position Gain.
FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES
14
CA3140, CA3140A
Wien Bridge Oscillator OUTPUT

19VP-P TO 22VP-P
Another application of the CA3140 that makes excellent use +15V THD <0.3%
R2
of its high input impedance, high slew rate, and high voltage
C2 1000pF 7
qualities is the Wien Bridge sine wave oscillator. A basic Wien 0.1µF CA3109
3 + 8 9
Bridge oscillator is shown in Figure 21. When R1 = R2 = R CA3140 6
DIODE
ARRAY
and C1 = C2 = C, the frequency equation reduces to the R1 C1 2 - SUBSTRATE
1000 OF CA3019 1
familiar f = 1/(2πRC) and the gain required for oscillation, 4 6 2
pF 0.1µF
AOSC is equal to 3. Note that if C2 is increased by a factor of 7 3
four and R2 is reduced by a factor of four, the gain required 0.1µF
-15V
for oscillation becomes 1.5, thus permitting a potentially 7.5kΩ 5 4
higher operating frequency closer to the gain bandwidth R1 = R2 = R
product of the CA3140.
50Hz, R = 3.3MΩ
C2 R2 3.6kΩ
NOTES: 100Hz, R = 1.6MΩ
1
f = ------------------------------------------- 1kHz, R = 160MΩ
2π R 1 C 1 R 2 C 2 500Ω
10kHz, R = 16MΩ
+
OUTPUT
30kHz, R = 5.1MΩ
C1 R2
- A OSC = 1 + ------- + ------- FIGURE 22. WIEN BRIDGE OSCILLATOR CIRCUIT USING
C2 R1
RF CA3140
Simple Sample-and-Hold System

C1 R1 RF
RS A CL = 1 + --------
RS Figure 23 shows a very simple sample-and-hold system
using the CA3140 as the readout amplifier for the storage
capacitor. The CA3080A serves as both input buffer
FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT amplifier and low feed-through transmission switch (see
USING AN OPERATIONAL AMPLIFIER Note 13). System offset nulling is accomplished with the
CA3140 via its offset nulling terminals. A typical simulated
Oscillator stabilization takes on many forms. It must be load of 2kΩ and 30pF is shown in the schematic.
precisely set, otherwise the amplitude will either diminish or
reach some form of limiting with high levels of distortion. The 30kΩ 0 SAMPLE
element, RS, is commonly replaced with some variable STROBE
-15 HOLD
resistance element. Thus, through some control means, the 1N914
value of RS is adjusted to maintain constant oscillator

+15V
output. A FET channel resistance, a thermistor, a lamp bulb,
1N914 +15V
or other device whose resistance increases as the output 5 0.1µF
2kΩ 3.5kΩ
7
amplitude is increased are a few of the elements often INPUT 3 + 7
utilized. CA3080A 6 3 +
2 - CA3140 6
4 -
Figure 22 shows another means of stabilizing the oscillator 2 4 0.1
1 µF
with a zener diode shunting the feedback resistor (RF of 0.1µF 5
Figure 21). As the output signal amplitude increases, the 2kΩ -15V 100kΩ
2kΩ
zener diode impedance decreases resulting in more -15V
200pF C1
feedback with consequent reduction in gain; thus stabilizing 200pF
the amplitude of the output signal. Furthermore, this 400Ω 2kΩ
combination of a monolithic zener diode and bridge rectifier 0.1µF 30pF

circuit tends to provide a zero temperature coefficient for this SIMULATED LOAD
NOT REQUIRED
regulating system. Because this bridge rectifier system has
no time constant, i.e., thermal time constant for the lamp
bulb, and RC time constant for filters often used in detector FIGURE 23. SAMPLE AND HOLD CIRCUIT
networks, there is no lower frequency limit. For example,
In this circuit, the storage compensation capacitance (C1) is
with 1µF polycarbonate capacitors and 22MΩ for the
only 200pF. Larger value capacitors provide longer “hold”
frequency determining network, the operating frequency is
periods but with slower slew rates. The slew rate is:
0.007Hz.
dv I
------ = ---- = 0.5mA ⁄ 200pF = 2.5V ⁄ µs
As the frequency is increased, the output amplitude must be dt C
reduced to prevent the output signal from becoming slew- NOTE:
rate limited. An output frequency of 180kHz will reach a slew 13. AN6668 “Applications of the CA3080 and CA 3080A High Per-
rate of approximately 9V/µs when its amplitude is 16VP-P. formance Operational Transconductance Amplifiers”.
15
CA3140, CA3140A
Pulse “droop” during the hold interval is 170pA/200pF which is Current Amplifier
0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA represents The low input terminal current needed to drive the CA3140
the typical leakage current of the CA3080A when strobed off. If makes it ideal for use in current amplifier applications such
C1 were increased to 2000pF, the “hold-droop” rate will as the one shown in Figure 25 (see Note 14). In this circuit,
decrease to 0.085µV/µs, but the slew rate would decrease to low current is supplied at the input potential as the power
0.25V/µs. The parallel diode network connected between supply to load resistor RL. This load current is increased by
Terminal 3 of the CA3080A and Terminal 6 of the CA3140 the multiplication factor R2/R1, when the load current is
prevents large input signal feedthrough across the input monitored by the power supply meter M. Thus, if the load
terminals of the CA3080A to the 200pF storage capacitor when current is 100nA, with values shown, the load current
the CA3080A is strobed off. Figure 24 shows dynamic presented to the supply will be 100µA; a much easier current
characteristic waveforms of this sample-and-hold system. to measure in many systems.
R1
10kΩ
+15V
R2
IL x 0.1µF
R1
7
3 + R2
M CA3140 6
10MΩ IL
2 - 4
0.1µF
POWER 1
SUPPLY 5 RL
100kΩ
Top Trace: Output; 50mV/Div., 200ns/Div.

Bottom Trace: Input; 50mV/Div., 200ns/Div. 4.3kΩ
-15V
FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT

MEASUREMENT SYSTEMS
Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by
the scale factor.
The dotted components show a method of decoupling the

circuit from the effects of high output load capacitance and
the potential oscillation in this situation. Essentially, the
Top Trace: Output Signal; 5V/Div, 2µs/Div. necessary high frequency feedback is provided by the
Center Trace: Difference of Input and Output Signals through capacitor with the dotted series resistor providing load
Tektronix Amplifier 7A13; 5mV/Div., 2µs/Div. decoupling.
Bottom Trace: Input Signal; 5V/Div., 2µs/Div.
LARGE SIGNAL RESPONSE AND SETTLING TIME Full Wave Rectifier
Figure 26 shows a single supply, absolute value, ideal full-
wave rectifier with associated waveforms. During positive
excursions, the input signal is fed through the feedback
network directly to the output. Simultaneously, the positive
excursion of the input signal also drives the output terminal
(No. 6) of the inverting amplifier in a negative going
excursion such that the 1N914 diode effectively disconnects
the amplifier from the signal path. During a negative going
excursion of the input signal, the CA3140 functions as a
normal inverting amplifier with a gain equal to -R2/R1. When
the equality of the two equations shown in Figure 26 is
SAMPLING RESPONSE satisfied, the full wave output is symmetrical.
Top Trace: Output; 100mV/Div., 500ns/Div. NOTE:
Bottom Trace: Input; 20V/Div., 500ns/Div. 14. “Operational Amplifiers Design and Applications”, J. G. Graeme,
FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC McGraw-Hill Book Company, page 308, “Negative Immittance
CHARACTERISTICS WAVEFORMS Converter Circuits”.
16
CA3140, CA3140A
R2 +15V
5kΩ +15V
0.1µF
10kΩ 7 SIMULATED
R1 0.1µF INPUT LOAD
3 +
2 - 7
10kΩ CA3140 6
CA3140 6
2 -
3 + 1N914 100pF 2kΩ
4 4
5 10kΩ
1
8 R3 0.1µF
PEAK
ADJUST
100kΩ -15V
10kΩ BW (-3dB) = 4.5MHz
OFFSET
SR = 9V/µs
ADJUST 2kΩ
R2 R3
GAIN = ------- = X = ----------------------------- 0.05µF
R1 R1 R2 + R3
2 FIGURE 28A. TEST CIRCUIT
R 3 =  ----------------- R 1
X+X
 1–X 
5kΩ R2
FOR X = 0.5 --------------- = -------
10kΩ R1
R 3 = 10kΩ  ----------- = 15kΩ

0.75
 0.5 
20VP-P Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V
OUTPUT
0 Top Trace: Output; 50mV/Div., 200ns/Div.
Bottom Trace: Input; 50mV/Div., 200ns/Div.
INPUT FIGURE 28B. SMALL SIGNAL RESPONSE
0
FIGURE 26. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL

WAVE RECTIFIER WITH ASSOCIATED
WAVEFORMS
+15V
0.01µF
RS 7
3 +
1MΩ NOISE VOLTAGE
CA3140 6
OUTPUT
2 -
4
(Measurement made with Tektronix 7A13 differential amplifier.)
30.1kΩ
0.01µF
-15V Top Trace: Output Signal; 5V/Div., 5µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
BW (-3dB) = 140kHz Bottom Trace: Input Signal; 5V/Div., 5µs/Div.
1kΩ
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT ) = 48µV (TYP)
FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENT FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST
CIRCUIT AND ASSOCIATED WAVEFORMS
17
CA3140, CA3140A
Typical Performance Curves

20
RL = 2kΩ RL = 2kΩ
GAIN BANDWIDTH PRODUCT (MHz)

CL = 100pF
10
TA = -55oC
OPEN-LOOP VOLTAGE GAIN (dB)
25oC 25oC
125
125oC 125oC
TA = -55oC
100
75
50
25
0 1
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE VOLTAGE AND TEMPERATURE
RL = 2kΩ RL = ∞
CL = 100pF 7
QUIESCENT SUPPLY CURRENT (mA)
6
TA = -55oC
25oC 5 25oC
125oC
20 TA = -55oC 4 125oC
SLEW RATE (V/µs)
15 3
10 2
5 1
0 0
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY
TEMPERATURE VOLTAGE AND TEMPERATURE
SUPPLY VOLTAGE: VS = ±15V 120 SUPPLY VOLTAGE: VS = ±15V

COMMON-MODE REJECTION RATIO (dB)
TA = 25oC TA = 25oC
25 100
OUTPUT SWING (VP-P)
20 80
15 60
10 40
5 20
0 0
10K 100K 1M 4M 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 34. COMMON MODE REJECTION RATIO vs FREQUENCY
FREQUENCY
18
CA3140, CA3140A
Typical Performance Curves (Continued)
1000
SUPPLY VOLTAGE: VS = ±15V SUPPLY VOLTAGE: VS = ±15V
EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz)
TA = 25oC TA = 25oC
100
POWER SUPPLY REJECTION RATIO (dB)

+PSRR
100 80
60
10 40 -PSRR
20
POWER SUPPLY REJECTION RATIO
(PSRR) = ∆VIO/∆VS
1 0
1 101 102 103 104 105 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FREQUENCY
Metallization Mask Layout
0 10 20 30 40 50 60 65
61
60
50
40
58-66
30 (1.473-1.676)
20
10
0
4-10
(0.102-0.254)
62-70
(1.575-1.778)
Dimensions in parenthesis are in millimeters and are derived

from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
The photographs and dimensions represent a chip when it is

part of the wafer. When the wafer is cut into chips, the cleavage
angles are 57o instead of 90ο with respect to the face of the
chip. Therefore, the isolated chip is actually 7 mils (0.17mm)
larger in both dimensions.
19
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters
November 1999
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit µP Compatible A/D Converters
General Description n Differential analog voltage inputs
n Logic inputs and outputs meet both MOS and TTL
The ADC0801, ADC0802, ADC0803, ADC0804 and
voltage level specifications
ADC0805 are CMOS 8-bit successive approximation A/D
n Works with 2.5V (LM336) voltage reference
converters that use a differential potentiometric
ladder — similar to the 256R products. These converters are n On-chip clock generator
designed to allow operation with the NSC800 and INS8080A n 0V to 5V analog input voltage range with single 5V
derivative control bus with TRI-STATE output latches directly supply
driving the data bus. These A/Ds appear like memory loca- n No zero adjust required
tions or I/O ports to the microprocessor and no interfacing n 0.3" standard width 20-pin DIP package
logic is needed. n 20-pin molded chip carrier or small outline package
Differential analog voltage inputs allow increasing the n Operates ratiometrically or with 5 VDC, 2.5 VDC, or
common-mode rejection and offsetting the analog zero input analog span adjusted voltage reference
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span Key Specifications
to the full 8 bits of resolution.
n Resolution 8 bits
n Total error ± 1⁄4 LSB, ± 1⁄2 LSB and ± 1 LSB
Features n Conversion time 100 µs
n Compatible with 8080 µP derivatives — no interfacing
logic needed - access time - 135 ns
n Easy interface to all microprocessors, or operates “stand
alone”
Connection Diagram
ADC080X
Dual-In-Line and Small Outline (SO) Packages
DS005671-30
See Ordering Information
TEMP RANGE 0˚C TO 70˚C 0˚C TO 70˚C −40˚C TO +85˚C
± 1⁄4 Bit Adjusted ADC0801LCN
ERROR ± 1⁄2 Bit Unadjusted ADC0802LCWM ADC0802LCN
± 1⁄2 Bit Adjusted ADC0803LCN
± 1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ
PACKAGE OUTLINE M20B — Small N20A — Molded DIP
Outline
Z-80 ® is a registered trademark of Zilog Corp.
© 2001 National Semiconductor Corporation DS005671 www.national.com

Typical Applications
DS005671-1
8080 Interface
DS005671-31
Error Specification (Includes Full-Scale,

Zero Error, and Non-Linearity)
Part Full- VREF/2=2.500 VDC VREF/2=No Connection
Number Scale (No Adjustments) (No Adjustments)
Adjusted
ADC0801 ± 1⁄4 LSB
ADC0802 ± 1⁄2 LSB
ADC0803 ± ⁄ LSB
12
ADC0804 ± 1 LSB
ADC0805 ± 1 LSB
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Absolute Maximum Ratings (Notes 1, 2) Infrared (15 seconds) 220˚C
If Military/Aerospace specified devices are required, Storage Temperature Range −65˚C to +150˚C
please contact the National Semiconductor Sales Office/ Package Dissipation at TA =25˚C 875 mW
Distributors for availability and specifications. ESD Susceptibility (Note 10) 800V
Supply Voltage (VCC) (Note 3) 6.5V
Voltage Operating Ratings (Notes 1, 2)
Logic Control Inputs −0.3V to +18V Temperature Range TMIN≤TA≤TMAX
At Other Input and Outputs −0.3V to (VCC+0.3V) ADC0804LCJ −40˚C≤TA≤+85˚C
Lead Temp. (Soldering, 10 seconds) ADC0801/02/03/05LCN −40˚C≤TA≤+85˚C
Dual-In-Line Package (plastic) 260˚C ADC0804LCN 0˚C≤TA≤+70˚C
Dual-In-Line Package (ceramic) 300˚C ADC0802/04LCWM 0˚C≤TA≤+70˚C
Surface Mount Package Range of VCC 4.5 VDC to 6.3 VDC
Vapor Phase (60 seconds) 215˚C
Electrical Characteristics
The following specifications apply for VCC =5 VDC, TMIN≤TA≤TMAX and fCLK =640 kHz unless otherwise specified.
Parameter Conditions Min Typ Max Units
ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj. ±⁄14 LSB
(See Section 2.5.2)
ADC0802: Total Unadjusted Error (Note 8) VREF/2=2.500 VDC ± 1 ⁄2 LSB
ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj. ± 1 ⁄2 LSB
(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8) VREF/2=2.500 VDC ±1 LSB
ADC0805: Total Unadjusted Error (Note 8) VREF/2-No Connection ±1 LSB
VREF/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩ
ADC0804 (Note 9) 0.75 1.1 kΩ
Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 VCC+0.05 VDC
DC Common-Mode Error Over Analog Input Voltage ± 1/16 ±⁄18 LSB
Range
Power Supply Sensitivity VCC =5 VDC ± 10% Over ± 1/16 ± 1 ⁄8 LSB
Allowed VIN(+) and VIN(−)
Voltage Range (Note 4)
AC Electrical Characteristics
The following specifications apply for VCC =5 VDC and TMIN≤TA≤TMAX unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
TC Conversion Time fCLK =640 kHz (Note 6) 103 114 µs
TC Conversion Time (Notes 5, 6) 66 73 1/fCLK
fCLK Clock Frequency VCC =5V, (Note 5) 100 640 1460 kHz
Clock Duty Cycle 40 60 %
CR Conversion Rate in Free-Running INTR tied to WR with 8770 9708 conv/s
Mode CS =0 VDC, fCLK =640 kHz
tW(WR)L Width of WR Input (Start Pulse Width) CS =0 VDC (Note 7) 100 ns
tACC Access Time (Delay from Falling CL =100 pF 135 200 ns
Edge of RD to Output Data Valid)
t1H, t0H TRI-STATE Control (Delay CL =10 pF, RL =10k 125 200 ns
from Rising Edge of RD to (See TRI-STATE Test
Hi-Z State) Circuits)
tWI, tRI Delay from Falling Edge 300 450 ns
of WR or RD to Reset of INTR
CIN Input Capacitance of Logic 5 7.5 pF
Control Inputs
3 www.national.com
AC Electrical Characteristics (Continued)
The following specifications apply for VCC =5 VDC and TMIN≤TA≤TMAX unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
COUT TRI-STATE Output 5 7.5 pF
Capacitance (Data Buffers)
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
VIN (1) Logical “1” Input Voltage VCC =5.25 VDC 2.0 15 VDC
(Except Pin 4 CLK IN)
VIN (0) Logical “0” Input Voltage VCC =4.75 VDC 0.8 VDC
(Except Pin 4 CLK IN)
IIN (1) Logical “1” Input Current VIN =5 VDC 0.005 1 µADC
(All Inputs)
IIN (0) Logical “0” Input Current VIN =0 VDC −1 −0.005 µADC
(All Inputs)
CLOCK IN AND CLOCK R
VT+ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 VDC
Threshold Voltage
VT− CLK IN (Pin 4) Negative 1.5 1.8 2.1 VDC
Going Threshold Voltage
VH CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 VDC
(VT+)−(VT−)
VOUT (0) Logical “0” CLK R Output IO =360 µA 0.4 VDC
Voltage VCC =4.75 VDC
VOUT (1) Logical “1” CLK R Output IO =−360 µA 2.4 VDC
Voltage VCC =4.75 VDC
DATA OUTPUTS AND INTR
VOUT (0) Logical “0” Output Voltage
Data Outputs IOUT =1.6 mA, VCC =4.75 VDC 0.4 VDC
INTR Output IOUT =1.0 mA, VCC =4.75 VDC 0.4 VDC
VOUT (1) Logical “1” Output Voltage IO =−360 µA, VCC =4.75 VDC 2.4 VDC
VOUT (1) Logical “1” Output Voltage IO =−10 µA, VCC =4.75 VDC 4.5 VDC
IOUT TRI-STATE Disabled Output VOUT =0 VDC −3 µADC
Leakage (All Data Buffers) VOUT =5 VDC 3 µADC
ISOURCE VOUT Short to Gnd, TA =25˚C 4.5 6 mADC
ISINK VOUT Short to VCC, TA =25˚C 9.0 16 mADC
POWER SUPPLY
ICC Supply Current (Includes fCLK =640 kHz,
Ladder Current) VREF/2=NC, TA =25˚C
and CS =5V
ADC0801/02/03/04LCJ/05 1.1 1.8 mA
ADC0804LCN/LCWM 1.9 2.5 mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from VCC to Gnd and has a typical breakdown voltage of 7 VDC.
Note 4: For VIN(−)≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec
allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will
be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations,
initial tolerance and loading.
Note 5: Accuracy is guaranteed at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be
extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.
Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 4 and section 2.0.
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AC Electrical Characteristics (Continued)
Note 7: The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).
Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and Figure 7.
Note 9: The VREF/2 pin is the center point of a two-resistor divider connected from VCC to ground. In all versions of the ADC0801, ADC0802, ADC0803, and
ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ.
Note 10: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Typical Performance Characteristics

Logic Input Threshold Voltage Delay From Falling Edge of CLK IN Schmitt Trip Levels
vs. Supply Voltage RD to Output Data Valid vs. Supply Voltage
vs. Load Capacitance
DS005671-38
DS005671-40
DS005671-39
fCLK vs. Clock Capacitor Full-Scale Error vs Effect of Unadjusted Offset Error
Conversion Time vs. VREF/2 Voltage
DS005671-41
DS005671-42 DS005671-43
Output Current vs Power Supply Current Linearity Error at Low

Temperature vs Temperature (Note 9) VREF/2 Voltages
DS005671-44 DS005671-46
DS005671-45
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TRI-STATE Test Circuits and Waveforms
t1H t1H, CL =10 pF
DS005671-48
DS005671-47
tr =20 ns
t0H t0H, CL =10 pF
DS005671-50
DS005671-49 tr =20 ns
Timing Diagrams (All timing is measured from the 50% voltage points)
DS005671-51
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Timing Diagrams (All timing is measured from the 50% voltage points) (Continued)
Output Enable and Reset with INTR
DS005671-52
Note: Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR .
Typical Applications
6800 Interface Ratiometeric with Full-Scale Adjust
DS005671-53
DS005671-54
Note: before using caps at VIN or VREF/2,

see section 2.3.2 Input Bypass Capacitors.
7 www.national.com
Typical Applications (Continued)
Absolute with a 2.500V Reference Absolute with a 5V Reference
DS005671-56
DS005671-55
*For low power, see also LM385–2.5
Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V Span Adjust: 0V ≤ VIN ≤ 3V
DS005671-58
DS005671-57
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Directly Converting a Low-Level Signal A µP Interfaced Comparator
DS005671-60
For:
VIN(+) > VIN(−)
Output=FFHEX
For:
VIN(+) < VIN(−)
DS005671-59 Output=00HEX
VREF/2=256 mV
1 mV Resolution with µP Controlled Range
DS005671-61
VREF/2=128 mV
1 LSB=1 mV
VDAC≤VIN≤(VDAC+256 mV)
0 ≤ VDAC < 2.5V
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Digitizing a Current Flow
DS005671-62
Self-Clocking Multiple A/Ds External Clocking
DS005671-64
100 kHz≤fCLK≤1460 kHz
DS005671-63
* Use a large R value

to reduce loading
at CLK R output.
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Self-Clocking in Free-Running Mode µP Interface for Free-Running A/D
DS005671-65
*After power-up, a momentary grounding of the WR input is needed to

guarantee operation.
DS005671-66
Operating with “Automotive” Ratiometric Transducers Ratiometric with VREF/2 Forced
DS005671-68
DS005671-67
*VIN(−)=0.15 VCC
15% of VCC≤VXDR≤85% of VCC
µP Compatible Differential-Input Comparator with Pre-Set VOS (with or without Hysteresis)
DS005671-69
*See Figure 5 to select R value

DB7=“1” for VIN(+) > VIN(−)+(VREF/2)
Omit circuitry within the dotted area if
hysteresis is not needed
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Handling ± 10V Analog Inputs Low-Cost, µP Interfaced, Temperature-to-Digital

Converter
DS005671-70
DS005671-71
*Beckman Instruments #694-3-R10K resistor array
µP Interfaced Temperature-to-Digital Converter
DS005671-72
*Circuit values shown are for 0˚C≤TA≤+128˚C

***Can calibrate each sensor to allow easy replacement, then A/D can be calibrated with a pre-set input voltage.
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Handling ± 5V Analog Inputs Read-Only Interface
DS005671-34
DS005671-33
*Beckman Instruments #694-3-R10K resistor array
µP Interfaced Comparator with Hysteresis Protecting the Input
DS005671-9
Diodes are 1N914
DS005671-35
13 www.national.com
Analog Self-Test for a System
DS005671-36
A Low-Cost, 3-Decade Logarithmic Converter
DS005671-37
*LM389 transistors
A, B, C, D = LM324A quad op amp
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3-Decade Logarithmic A/D Converter
DS005671-73
Noise Filtering the Analog Input Multiplexing Differential Inputs
DS005671-74
DS005671-75
fC =20 Hz
Uses Chebyshev implementation for steeper roll-off unity-gain, 2nd order,
low-pass filter
Adding a separate filter for each channel increases system response time
if an analog multiplexer is used
Output Buffers with A/D Data Enabled Increasing Bus Drive and/or Reducing Time on Bus
DS005671-77
DS005671-76
*Allows output data to set-up at falling edge of CS
*A/D output data is updated 1 CLK period prior to assertion of INTR
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Sampling an AC Input Signal
DS005671-78
Note 11: Oversample whenever possible [keep fs > 2f(−60)] to eliminate input frequency folding (aliasing) and to allow for the skirt response of the filter.
Note 12: Consider the amplitude errors which are introduced within the passband of the filter.
70% Power Savings by Clock Gating
DS005671-79
(Complete shutdown takes ≈ 30 seconds.)
Power Savings by A/D and VREF Shutdown
DS005671-80
*Use ADC0801, 02, 03 or 05 for lowest power consumption.

Note: Logic inputs can be driven to VCC with A/D supply at zero volts.
Buffer prevents data bus from overdriving output of A/D when in shutdown mode.
Functional Description D−1, D, and D+1. For the perfect A/D, not only will
center-value (A−1, A, A+1, . . . . ) analog inputs produce
the correct output digital codes, but also each riser (the
1.0 UNDERSTANDING A/D ERROR SPECS
transitions between adjacent output codes) will be located
A perfect A/D transfer characteristic (staircase waveform) is ± 1⁄2 LSB away from each center-value. As shown, the risers
shown in Figure 1. The horizontal scale is analog input are ideal and have no width. Correct digital output codes will
voltage and the particular points labeled are in steps of 1 be provided for a range of analog input voltages that extend
LSB (19.53 mV with 2.5V tied to the VREF/2 pin). The digital
output codes that correspond to these inputs are shown as
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Functional Description (Continued) Next to each transfer function is shown the corresponding
error plot. Many people may be more familiar with error plots
± 1⁄2 LSB from the ideal center-values. Each tread (the range than transfer functions. The analog input voltage to the A/D
of analog input voltage that provides the same digital output is provided by either a linear ramp or by the discrete output
code) is therefore 1 LSB wide. steps of a high resolution DAC. Notice that the error is
Figure 2 shows a worst case error plot for the ADC0801. All continuously displayed and includes the quantization uncer-
center-valued inputs are guaranteed to produce the correct tainty of the A/D. For example the error at point 1 of Figure 1
output codes and the adjacent risers are guaranteed to be is +1⁄2 LSB because the digital code appeared 1⁄2 LSB in
no closer to the center-value points than ± 1⁄4 LSB. In other advance of the center-value of the tread. The error plots
words, if we apply an analog input equal to the center-value always have a constant negative slope and the abrupt up-
± 1⁄4 LSB, we guarantee that the A/D will produce the correct side steps are always 1 LSB in magnitude.
digital code. The maximum range of the position of the code
transition is indicated by the horizontal arrow and it is guar-
anteed to be no more than 1⁄2 LSB.
The error curve of Figure 3 shows a worst case error plot for
the ADC0802. Here we guarantee that if we apply an analog
input equal to the LSB analog voltage center-value the A/D
will produce the correct digital code.
Transfer Function Error Plot
DS005671-81
DS005671-82
FIGURE 1. Clarifying the Error Specs of an A/D Converter

Accuracy= ± 0 LSB: A Perfect A/D
DS005671-83
DS005671-84

Accuracy= ± 1⁄4 LSB
17 www.national.com
Functional Description (Continued)
DS005671-85
DS005671-86

Accuracy= ± 1⁄2 LSB
2.0 FUNCTIONAL DESCRIPTION A functional diagram of the A/D converter is shown in Figure
The ADC0801 series contains a circuit equivalent of the 4. All of the package pinouts are shown and the major logic
256R network. Analog switches are sequenced by succes- control paths are drawn in heavier weight lines.
sive approximation logic to match the analog difference input The converter is started by having CS and WR simulta-
voltage [VIN(+) − VIN(−)] to a corresponding tap on the R neously low. This sets the start flip-flop (F/F) and the result-
network. The most significant bit is tested first and after 8 ing “1” level resets the 8-bit shift register, resets the Interrupt
comparisons (64 clock cycles) a digital 8-bit binary code (INTR) F/F and inputs a “1” to the D flop, F/F1, which is at the
(1111 1111 = full-scale) is transferred to an output latch and input end of the 8-bit shift register. Internal clock signals then
then an interrupt is asserted (INTR makes a high-to-low transfer this “1” to the Q output of F/F1. The AND gate, G1,
transition). A conversion in process can be interrupted by combines this “1” output with a clock signal to provide a reset
issuing a second start command. The device may be oper- signal to the start F/F. If the set signal is no longer present
ated in the free-running mode by connecting INTR to the WR (either WR or CS is a “1”) the start F/F is reset and the 8-bit
input with CS =0. To ensure start-up under all possible shift register then can have the “1” clocked in, which starts
conditions, an external WR pulse is required during the first the conversion process. If the set signal were to still be
power-up cycle. present, this reset pulse would have no effect (both outputs
On the high-to-low transition of the WR input the internal of the start F/F would momentarily be at a “1” level) and the
SAR latches and the shift register stages are reset. As long 8-bit shift register would continue to be held in the reset
as the CS input and WR input remain low, the A/D will remain mode. This logic therefore allows for wide CS and WR
in a reset state. Conversion will start from 1 to 8 clock signals and the converter will start after at least one of these
periods after at least one of these inputs makes a low-to-high signals returns high and the internal clocks again provide a
transition. reset signal for the start F/F.
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DS005671-13
Note 13: CS shown twice for clarity.

Note 14: SAR = Successive Approximation Register.
FIGURE 4. Block Diagram

After the “1” is clocked through the 8-bit shift register (which which causes the input to the D-type latch, LATCH 1, to go
completes the SAR search) it appears as the input to the low. As the latch enable input is still present, the Q output will
D-type latch, LATCH 1. As soon as this “1” is output from the go high, which then allows the INTR F/F to be RESET. This
shift register, the AND gate, G2, causes the new digital word reduces the width of the resulting INTR output pulse to only
to transfer to the TRI-STATE output latches. When LATCH 1 a few propagation delays (approximately 300 ns).
is subsequently enabled, the Q output makes a high-to-low When data is to be read, the combination of both CS and RD
transition which causes the INTR F/F to set. An inverting being low will cause the INTR F/F to be reset and the
buffer then supplies the INTR input signal. TRI-STATE output latches will be enabled to provide the 8-bit
Note that this SET control of the INTR F/F remains low for 8 digital outputs.
of the external clock periods (as the internal clocks run at 1⁄8
of the frequency of the external clock). If the data output is 2.1 Digital Control Inputs
continuously enabled (CS and RD both held low), the INTR The digital control inputs (CS, RD, and WR) meet standard
output will still signal the end of conversion (by a high-to-low T2L logic voltage levels. These signals have been renamed
transition), because the SET input can control the Q output when compared to the standard A/D Start and Output Enable
of the INTR F/F even though the RESET input is constantly labels. In addition, these inputs are active low to allow an
at a “1” level in this operating mode. This INTR output will easy interface to microprocessor control busses. For
therefore stay low for the duration of the SET signal, which is non-microprocessor based applications, the CS input (pin 1)
8 periods of the external clock frequency (assuming the A/D can be grounded and the standard A/D Start function is
is not started during this interval). obtained by an active low pulse applied at the WR input (pin
When operating in the free-running or continuous conversion 3) and the Output Enable function is caused by an active low
mode (INTR pin tied to WR and CS wired low — see also pulse at the RD input (pin 2).
section 2.8), the START F/F is SET by the high-to-low tran-
sition of the INTR signal. This resets the SHIFT REGISTER
19 www.national.com
2.2 Analog Differential Voltage Inputs and

Common-Mode Rejection
This A/D has additional applications flexibility due to the
analog differential voltage input. The VIN(−) input (pin 7) can
be used to automatically subtract a fixed voltage value from
the input reading (tare correction). This is also useful in 4
mA–20 mA current loop conversion. In addition,
common-mode noise can be reduced by use of the differen-
tial input.
The time interval between sampling VIN(+) and VIN(−) is 4-1⁄2
clock periods. The maximum error voltage due to this slight
DS005671-14
time difference between the input voltage samples is given
by: rON of SW 1 and SW 2 . 5 kΩ
r=rON CSTRAY . 5 kΩ x 12 pF = 60 ns
FIGURE 5. Analog Input Impedance
The voltage on this capacitance is switched and will result in

where: currents entering the VIN(+) input pin and leaving the VIN(−)
∆Ve is the error voltage due to sampling delay input which will depend on the analog differential input volt-
age levels. These current transients occur at the leading
VP is the peak value of the common-mode voltage
edge of the internal clocks. They rapidly decay and do not
fcm is the common-mode frequency cause errors as the on-chip comparator is strobed at the end
As an example, to keep this error to 1⁄4 LSB (∼5 mV) when of the clock period.
operating with a 60 Hz common-mode frequency, fcm, and
using a 640 kHz A/D clock, fCLK, would allow a peak value of Fault Mode
the common-mode voltage, VP, which is given by: If the voltage source applied to the VIN(+) or VIN(−) pin
exceeds the allowed operating range of VCC+50 mV, large
input currents can flow through a parasitic diode to the VCC
pin. If these currents can exceed the 1 mA max allowed
spec, an external diode (1N914) should be added to bypass
or
this current to the VCC pin (with the current bypassed with
this diode, the voltage at the VIN(+) pin can exceed the VCC
voltage by the forward voltage of this diode).
2.3.2 Input Bypass Capacitors

which gives
Bypass capacitors at the inputs will average these charges
VP.1.9V. and cause a DC current to flow through the output resis-
The allowed range of analog input voltages usually places tances of the analog signal sources. This charge pumping
more severe restrictions on input common-mode noise lev- action is worse for continuous conversions with the VIN(+)
els. input voltage at full-scale. For continuous conversions with a
An analog input voltage with a reduced span and a relatively 640 kHz clock frequency with the VIN(+) input at 5V, this DC
large zero offset can be handled easily by making use of the current is at a maximum of approximately 5 µA. Therefore,
differential input (see section 2.4 Reference Voltage). bypass capacitors should not be used at the analog inputs or
the VREF/2 pin for high resistance sources ( > 1 kΩ). If input
2.3 Analog Inputs bypass capacitors are necessary for noise filtering and high
source resistance is desirable to minimize capacitor size, the
2.3 1 Input Current detrimental effects of the voltage drop across this input
resistance, which is due to the average value of the input
Normal Mode current, can be eliminated with a full-scale adjustment while
Due to the internal switching action, displacement currents the given source resistor and input bypass capacitor are
will flow at the analog inputs. This is due to on-chip stray both in place. This is possible because the average value of
capacitance to ground as shown in Figure 5. the input current is a precise linear function of the differential
input voltage.
2.3.3 Input Source Resistance

Large values of source resistance where an input bypass
capacitor is not used, will not cause errors as the input
currents settle out prior to the comparison time. If a low pass
filter is required in the system, use a low valued series
resistor (≤ 1 kΩ) for a passive RC section or add an op amp
RC active low pass filter. For low source resistance applica-
tions, (≤ 1 kΩ), a 0.1 µF bypass capacitor at the inputs will
prevent noise pickup due to series lead inductance of a long
www.national.com 20
Functional Description (Continued) Notice that the reference voltage for the IC is either 1⁄2 of the
voltage applied to the VCC supply pin, or is equal to the
wire. A 100Ω series resistor can be used to isolate this voltage that is externally forced at the VREF/2 pin. This allows
capacitor — both the R and C are placed outside the feed- for a ratiometric voltage reference using the VCC supply, a 5
back loop — from the output of an op amp, if used. VDC reference voltage can be used for the VCC supply or a
voltage less than 2.5 VDC can be applied to the VREF/2 input
2.3.4 Noise for increased application flexibility. The internal gain to the
The leads to the analog inputs (pins 6 and 7) should be kept VREF/2 input is 2, making the full-scale differential input
as short as possible to minimize input noise coupling. Both voltage twice the voltage at pin 9.
noise and undesired digital clock coupling to these inputs An example of the use of an adjusted reference voltage is to
can cause system errors. The source resistance for these accommodate a reduced span — or dynamic voltage range
inputs should, in general, be kept below 5 kΩ. Larger values of the analog input voltage. If the analog input voltage were
of source resistance can cause undesired system noise to range from 0.5 VDC to 3.5 VDC, instead of 0V to 5 VDC, the
pickup. Input bypass capacitors, placed from the analog span would be 3V as shown in Figure 7. With 0.5 VDC
inputs to ground, will eliminate system noise pickup but can applied to the VIN(−) pin to absorb the offset, the reference
create analog scale errors as these capacitors will average voltage can be made equal to 1⁄2 of the 3V span or 1.5 VDC.
the transient input switching currents of the A/D (see section The A/D now will encode the VIN(+) signal from 0.5V to 3.5 V
2.3.1.). This scale error depends on both a large source with the 0.5V input corresponding to zero and the 3.5 VDC
resistance and the use of an input bypass capacitor. This input corresponding to full-scale. The full 8 bits of resolution
error can be eliminated by doing a full-scale adjustment of are therefore applied over this reduced analog input voltage
the A/D (adjust VREF/2 for a proper full-scale reading — see range.
section 2.5.2 on Full-Scale Adjustment) with the source re-
sistance and input bypass capacitor in place. 2.4.2 Reference Accuracy Requirements
The converter can be operated in a ratiometric mode or an
2.4 Reference Voltage
absolute mode. In ratiometric converter applications, the
2.4.1 Span Adjust magnitude of the reference voltage is a factor in both the
output of the source transducer and the output of the A/D
For maximum applications flexibility, these A/Ds have been converter and therefore cancels out in the final digital output
designed to accommodate a 5 VDC, 2.5 VDC or an adjusted code. The ADC0805 is specified particularly for use in ratio-
voltage reference. This has been achieved in the design of metric applications with no adjustments required. In absolute
the IC as shown in Figure 6. conversion applications, both the initial value and the tem-
perature stability of the reference voltage are important fac-
tors in the accuracy of the A/D converter. For VREF/2 volt-
ages of 2.4 VDC nominal value, initial errors of ± 10 mVDC will
cause conversion errors of ± 1 LSB due to the gain of 2 of the
VREF/2 input. In reduced span applications, the initial value
and the stability of the VREF/2 input voltage become even
more important. For example, if the span is reduced to 2.5V,
the analog input LSB voltage value is correspondingly re-
duced from 20 mV (5V span) to 10 mV and 1 LSB at the
VREF/2 input becomes 5 mV. As can be seen, this reduces
the allowed initial tolerance of the reference voltage and
requires correspondingly less absolute change with tem-
perature variations. Note that spans smaller than 2.5V place
even tighter requirements on the initial accuracy and stability
of the reference source.
In general, the magnitude of the reference voltage will re-
quire an initial adjustment. Errors due to an improper value
of reference voltage appear as full-scale errors in the A/D
transfer function. IC voltage regulators may be used for
references if the ambient temperature changes are not ex-
cessive. The LM336B 2.5V IC reference diode (from Na-
tional Semiconductor) has a temperature stability of 1.8 mV
typ (6 mV max) over 0˚C≤TA≤+70˚C. Other temperature
DS005671-15
FIGURE 6. The VREFERENCE Design on the IC range parts are also available.
21 www.national.com
DS005671-87
a) Analog Input Signal Example
DS005671-88
*Add if VREF/2 ≤ 1 VDC with LM358 to draw 3 mA to ground.
b) Accommodating an Analog Input from

0.5V (Digital Out = 00HEX) to 3.5V
(Digital Out=FFHEX)
FIGURE 7. Adapting the A/D Analog Input Voltages to Match an Arbitrary Input Signal Range
2.5 Errors and Reference Voltage Adjustments 256) is applied to pin 6 and the zero reference voltage at pin
7 should then be adjusted to just obtain the 00HEX to 01HEX
2.5.1 Zero Error code transition.
The zero of the A/D does not require adjustment. If the The full-scale adjustment should then be made (with the
minimum analog input voltage value, VIN(MIN), is not ground, proper VIN(−) voltage applied) by forcing a voltage to the
a zero offset can be done. The converter can be made to VIN(+) input which is given by:
output 0000 0000 digital code for this minimum input voltage
by biasing the A/D VIN(−) input at this VIN(MIN) value (see
Applications section). This utilizes the differential mode op-
eration of the A/D.
The zero error of the A/D converter relates to the location of where:
the first riser of the transfer function and can be measured by VMAX =The high end of the analog input range
grounding the VIN (−) input and applying a small magnitude and
positive voltage to the VIN (+) input. Zero error is the differ-
VMIN =the low end (the offset zero) of the analog range.
ence between the actual DC input voltage that is necessary
(Both are ground referenced.)
to just cause an output digital code transition from 0000 0000
to 0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB = 9.8 mV The VREF/2 (or VCC) voltage is then adjusted to provide a
for VREF/2=2.500 VDC). code change from FEHEX to FFHEX. This completes the
adjustment procedure.
2.5.2 Full-Scale
2.6 Clocking Option
The full-scale adjustment can be made by applying a differ-
ential input voltage that is 11⁄2 LSB less than the desired The clock for the A/D can be derived from the CPU clock or
analog full-scale voltage range and then adjusting the mag- an external RC can be added to provide self-clocking. The
nitude of the VREF/2 input (pin 9 or the VCC supply if pin 9 is CLK IN (pin 4) makes use of a Schmitt trigger as shown in
not used) for a digital output code that is just changing from Figure 8.
1111 1110 to 1111 1111.
2.5.3 Adjusting for an Arbitrary Analog Input Voltage

Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
that does not go to ground) this new zero reference should
be properly adjusted first. A VIN(+) voltage that equals this
desired zero reference plus 1⁄2 LSB (where the LSB is cal-
culated for the desired analog span, 1 LSB=analog span/
www.national.com 22
Functional Description (Continued) (low power Schottky such as the DM74LS240 series is rec-
ommended) or special higher drive current products which
are designed as bus drivers. High current bipolar bus drivers
with PNP inputs are recommended.
2.10 Power Supplies

Noise spikes on the VCC supply line can cause conversion
errors as the comparator will respond to this noise. A low
inductance tantalum filter capacitor should be used close to
the converter VCC pin and values of 1 µF or greater are
recommended. If an unregulated voltage is available in the
system, a separate LM340LAZ-5.0, TO-92, 5V voltage regu-
lator for the converter (and other analog circuitry) will greatly
DS005671-17 reduce digital noise on the VCC supply.
2.11 Wiring and Hook-Up Precautions

Standard digital wire wrap sockets are not satisfactory for
breadboarding this A/D converter. Sockets on PC boards
can be used and all logic signal wires and leads should be
FIGURE 8. Self-Clocking the A/D grouped and kept as far away as possible from the analog
signal leads. Exposed leads to the analog inputs can cause
Heavy capacitive or DC loading of the clock R pin should be undesired digital noise and hum pickup, therefore shielded
avoided as this will disturb normal converter operation. leads may be necessary in many applications.
Loads less than 50 pF, such as driving up to 7 A/D converter
A single point analog ground that is separate from the logic
clock inputs from a single clock R pin of 1 converter, are
ground points should be used. The power supply bypass
allowed. For larger clock line loading, a CMOS or low power
capacitor and the self-clocking capacitor (if used) should
TTL buffer or PNP input logic should be used to minimize the
both be returned to digital ground. Any VREF/2 bypass ca-
loading on the clock R pin (do not use a standard TTL
pacitors, analog input filter capacitors, or input signal shield-
buffer).
ing should be returned to the analog ground point. A test for
proper grounding is to measure the zero error of the A/D
2.7 Restart During a Conversion
converter. Zero errors in excess of 1⁄4 LSB can usually be
If the A/D is restarted (CS and WR go low and return high) traced to improper board layout and wiring (see section 2.5.1
during a conversion, the converter is reset and a new con- for measuring the zero error).
version is started. The output data latch is not updated if the
conversion in process is not allowed to be completed, there- 3.0 TESTING THE A/D CONVERTER
fore the data of the previous conversion remains in this latch.
There are many degrees of complexity associated with test-
The INTR output simply remains at the “1” level.
ing an A/D converter. One of the simplest tests is to apply a
known analog input voltage to the converter and use LEDs to
2.8 Continuous Conversions
display the resulting digital output code as shown in Figure 9.
For operation in the free-running mode an initializing pulse
For ease of testing, the VREF/2 (pin 9) should be supplied
should be used, following power-up, to ensure circuit opera-
with 2.560 VDC and a VCC supply voltage of 5.12 VDC should
tion. In this application, the CS input is grounded and the WR
be used. This provides an LSB value of 20 mV.
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a If a full-scale adjustment is to be made, an analog input
power-up cycle to guarantee operation. voltage of 5.090 VDC (5.120–11⁄2 LSB) should be applied to
the VIN(+) pin with the VIN(−) pin grounded. The value of the
2.9 Driving the Data Bus VREF/2 input voltage should then be adjusted until the digital
This MOS A/D, like MOS microprocessors and memories, output code is just changing from 1111 1110 to 1111 1111.
will require a bus driver when the total capacitance of the This value of VREF/2 should then be used for all the tests.
data bus gets large. Other circuitry, which is tied to the data The digital output LED display can be decoded by dividing
bus, will add to the total capacitive loading, even in the 8 bits into 2 hex characters, the 4 most significant (MS)
TRI-STATE (high impedance mode). Backplane bussing and the 4 least significant (LS). Table 1 shows the fractional
also greatly adds to the stray capacitance of the data bus. binary equivalent of these two 4-bit groups. By adding the
There are some alternatives available to the designer to voltages obtained from the “VMS” and “VLS” columns in
handle this problem. Basically, the capacitive loading of the Table 1, the nominal value of the digital display (when
data bus slows down the response time, even though DC VREF/2 = 2.560V) can be determined. For example, for an
specifications are still met. For systems operating with a output LED display of 1011 0110 or B6 (in hex), the voltage
relatively slow CPU clock frequency, more time is available values from the table are 3.520 + 0.120 or 3.640 VDC. These
in which to establish proper logic levels on the bus and voltage values represent the center-values of a perfect A/D
therefore higher capacitive loads can be driven (see typical converter. The effects of quantization error have to be ac-
characteristics curves). counted for in the interpretation of the test results.
At higher CPU clock frequencies time can be extended for
I/O reads (and/or writes) by inserting wait states (8080) or
using clock extending circuits (6800).
Finally, if time is short and capacitive loading is high, external
bus drivers must be used. These can be TRI-STATE buffers
23 www.national.com
Functional Description (Continued) For a higher speed test system, or to obtain plotted data, a
digital-to-analog converter is needed for the test set-up. An
accurate 10-bit DAC can serve as the precision voltage
source for the A/D. Errors of the A/D under test can be
expressed as either analog voltages or differences in 2
digital words.
A basic A/D tester that uses a DAC and provides the error as
an analog output voltage is shown in Figure 8. The 2 op
amps can be eliminated if a lab DVM with a numerical
subtraction feature is available to read the difference volt-
age, “A–C”, directly. The analog input voltage can be sup-
plied by a low frequency ramp generator and an X-Y plotter
can be used to provide analog error (Y axis) versus analog
input (X axis).
For operation with a microprocessor or a computer-based
test system, it is more convenient to present the errors
digitally. This can be done with the circuit of Figure 11, where
the output code transitions can be detected as the 10-bit
DAC is incremented. This provides 1⁄4 LSB steps for the 8-bit
A/D under test. If the results of this test are automatically
plotted with the analog input on the X axis and the error (in
LSB’s) as the Y axis, a useful transfer function of the A/D
under test results. For acceptance testing, the plot is not
necessary and the testing speed can be increased by estab-
DS005671-18 lishing internal limits on the allowed error for each code.
FIGURE 9. Basic A/D Tester
4.0 MICROPROCESSOR INTERFACING
To dicuss the interface with 8080A and 6800 microproces-
sors, a common sample subroutine structure is used. The
microprocessor starts the A/D, reads and stores the results
of 16 successive conversions, then returns to the user’s
program. The 16 data bytes are stored in 16 successive
memory locations. All Data and Addresses will be given in
hexadecimal form. Software and hardware details are pro-
vided separately for each type of microprocessor.
4.1 Interfacing 8080 Microprocessor Derivatives (8048,

8085)
This converter has been designed to directly interface with
derivatives of the 8080 microprocessor. The A/D can be
mapped into memory space (using standard memory ad-
dress decoding for CS and the MEMR and MEMW strobes)
or it can be controlled as an I/O device by using the I/O R
and I/O W strobes and decoding the address bits A0 → A7
(or address bits A8 → A15 as they will contain the same 8-bit
address information) to obtain the CS input. Using the I/O
space provides 256 additional addresses and may allow a
simpler 8-bit address decoder but the data can only be input
to the accumulator. To make use of the additional memory
reference instructions, the A/D should be mapped into
memory space. An example of an A/D in I/O space is shown
in Figure 12.
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DS005671-89
FIGURE 10. A/D Tester with Analog Error Output
DS005671-90
FIGURE 11. Basic “Digital” A/D Tester
TABLE 1. DECODING THE DIGITAL OUTPUT LEDs
OUTPUT VOLTAGE
FRACTIONAL BINARY VALUE FOR CENTER VALUES
HEX BINARY WITH
VREF/2=2.560 VDC
MS GROUP LS GROUP VMS VLS
GROUP GROUP
(Note 15) (Note 15)
F 1 1 1 1 15/16 15/256 4.800 0.300
E 1 1 1 0 7/8 7/128 4.480 0.280
D 1 1 0 1 13/16 13/256 4.160 0.260
C 1 1 0 0 3/4 3/64 3.840 0.240
B 1 0 1 1 11/16 11/256 3.520 0.220
A 1 0 1 0 5/8 5/128 3.200 0.200
9 1 0 0 1 9/16 9/256 2.880 0.180
8 1 0 0 0 1/2 1/32 2.560 0.160
7 0 1 1 1 7/16 7/256 2.240 0.140
6 0 1 1 0 3/8 3/128 1.920 0.120
5 0 1 0 1 5/16 2/256 1.600 0.100
4 0 1 0 0 1/4 1/64 1.280 0.080
3 0 0 1 1 3/16 3/256 0.960 0.060
2 0 0 1 0 1/8 1/128 0.640 0.040
1 0 0 0 1 1/16 1/256 0.320 0.020
0 0 0 0 0 0 0
Note 15: Display Output=VMS Group + VLS Group
25 www.national.com
DS005671-20
Note 16: *Pin numbers for the DP8228 system controller, others are INS8080A.
Note 17: Pin 23 of the INS8228 must be tied to +12V through a 1 kΩ resistor to generate the RST 7
instruction when an interrupt is acknowledged as required by the accompanying sample program.
FIGURE 12. ADC0801_INS8080A CPU Interface
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SAMPLE PROGRAM FOR Figure 12 ADC0801–INS8080A CPU INTERFACE
DS005671-99
Note 18: The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack.
Note 19: All address used were arbitrarily chosen.
The standard control bus signals of the 8080 CS, RD and It is important to note that in systems where the A/D con-
WR) can be directly wired to the digital control inputs of the verter is 1-of-8 or less I/O mapped devices, no address
A/D and the bus timing requirements are met to allow both decoding circuitry is necessary. Each of the 8 address bits
starting the converter and outputting the data onto the data (A0 to A7) can be directly used as CS inputs — one for each
bus. A bus driver should be used for larger microprocessor I/O device.
systems where the data bus leaves the PC board and/or
must drive capacitive loads larger than 100 pF. 4.1.2 INS8048 Interface
The INS8048 interface technique with the ADC0801 series
4.1.1 Sample 8080A CPU Interfacing Circuitry and (see Figure 13) is simpler than the 8080A CPU interface.
Program There are 24 I/O lines and three test input lines in the 8048.
The following sample program and associated hardware With these extra I/O lines available, one of the I/O lines (bit
shown in Figure 12 may be used to input data from the 0 of port 1) is used as the chip select signal to the A/D, thus
converter to the INS8080A CPU chip set (comprised of the eliminating the use of an external address decoder. Bus
INS8080A microprocessor, the INS8228 system controller control signals RD, WR and INT of the 8048 are tied directly
and the INS8224 clock generator). For simplicity, the A/D is to the A/D. The 16 converted data words are stored at
controlled as an I/O device, specifically an 8-bit bi-directional on-chip RAM locations from 20 to 2F (Hex). The RD and WR
port located at an arbitrarily chosen port address, E0. The signals are generated by reading from and writing into a
TRI-STATE output capability of the A/D eliminates the need dummy address, respectively. A sample interface program is
for a peripheral interface device, however address decoding shown below.
is still required to generate the appropriate CS for the con-
verter.
27 www.national.com
DS005671-21
FIGURE 13. INS8048 Interface
SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE
DS005671-A0
4.2 Interfacing the Z-80

The Z-80 control bus is slightly different from that of the
8080. General RD and WR strobes are provided and sepa-
rate memory request, MREQ, and I/O request, IORQ, sig-
nals are used which have to be combined with the general-
ized strobes to provide the equivalent 8080 signals. An
advantage of operating the A/D in I/O space with the Z-80 is DS005671-23
that the CPU will automatically insert one wait state (the RD FIGURE 14. Mapping the A/D as an I/O Device
and WR strobes are extended one clock period) to allow for Use with the Z-80 CPU
more time for the I/O devices to respond. Logic to map the
A/D in I/O space is shown in Figure 14. Additional I/O advantages exist as software DMA routines
are available and use can be made of the output data
transfer which exists on the upper 8 address lines (A8 to
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Functional Description (Continued) already memory mapped in the M6800 system and no CS
decoding is necessary. Also notice that the A/D output data
A15) during I/O input instructions. For example, MUX chan- lines are connected to the microprocessor bus under pro-
nel selection for the A/D can be accomplished with this gram control through the PIA and therefore the A/D RD pin
operating mode. can be grounded.
A sample interface program equivalent to the previous one is
4.3 Interfacing 6800 Microprocessor Derivatives shown below Figure 16. The PIA Data and Control Registers
(6502, etc.) of Port B are located at HEX addresses 8006 and 8007,
The control bus for the 6800 microprocessor derivatives respectively.
does not use the RD and WR strobe signals. Instead it
employs a single R/W line and additional timing, if needed, 5.0 GENERAL APPLICATIONS
can be derived fom the φ2 clock. All I/O devices are memory The following applications show some interesting uses for
mapped in the 6800 system, and a special signal, VMA, the A/D. The fact that one particular microprocessor is used
indicates that the current address is valid. Figure 15 shows is not meant to be restrictive. Each of these application
an interface schematic where the A/D is memory mapped in circuits would have its counterpart using any microprocessor
the 6800 system. For simplicity, the CS decoding is shown that is desired.
using 1⁄2 DM8092. Note that in many 6800 systems, an
already decoded 4/5 line is brought out to the common bus 5.1 Multiple ADC0801 Series to MC6800 CPU Interface
at pin 21. This can be tied directly to the CS pin of the A/D,
To transfer analog data from several channels to a single
provided that no other devices are addressed at HX ADDR:
microprocessor system, a multiple converter scheme pre-
4XXX or 5XXX.
sents several advantages over the conventional multiplexer
The following subroutine performs essentially the same func- single-converter approach. With the ADC0801 series, the
tion as in the case of the 8080A interface and it can be called differential inputs allow individual span adjustment for each
from anywhere in the user’s program. channel. Furthermore, all analog input channels are sensed
In Figure 16 the ADC0801 series is interfaced to the M6800 simultaneously, which essentially divides the microproces-
microprocessor through (the arbitrarily chosen) Port B of the sor’s total system servicing time by the number of channels,
MC6820 or MC6821 Peripheral Interface Adapter, (PIA). since all conversions occur simultaneously. This scheme is
Here the CS pin of the A/D is grounded since the PIA is shown in Figure 17.
DS005671-24
Note 20: Numbers in parentheses refer to MC6800 CPU pin out.

Note 21: Number or letters in brackets refer to standard M6800 system common bus code.
FIGURE 15. ADC0801-MC6800 CPU Interface
29 www.national.com
SAMPLE PROGRAM FOR Figure 15 ADC0801-MC6800 CPU INTERFACE
DS005671-A1
Note 22: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.
DS005671-25
FIGURE 16. ADC0801–MC6820 PIA Interface
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SAMPLE PROGRAM FOR Figure 16 ADC0801–MC6820 PIA INTERFACE
DS005671-A2
The following schematic and sample subroutine (DATA IN) CPU, starts all the converters simultaneously and waits for
may be used to interface (up to) 8 ADC0801’s directly to the the interrupt signal. Upon receiving the interrupt, it reads the
MC6800 CPU. This scheme can easily be extended to allow converters (from HEX addresses 5000 through 5007) and
the interface of more converters. In this configuration the stores the data successively at (arbitrarily chosen) HEX
converters are (arbitrarily) located at HEX address 5000 in addresses 0200 to 0207, before returning to the user’s pro-
the MC6800 memory space. To save components, the clock gram. All CPU registers then recover the original data they
signal is derived from just one RC pair on the first converter. had before servicing DATA IN.
This output drives the other A/Ds.
All the converters are started simultaneously with a STORE 5.2 Auto-Zeroed Differential Transducer Amplifier
instruction at HEX address 5000. Note that any other HEX and A/D Converter
address of the form 5XXX will be decoded by the circuit, The differential inputs of the ADC0801 series eliminate the
pulling all the CS inputs low. This can easily be avoided by need to perform a differential to single ended conversion for
using a more definitive address decoding scheme. All the a differential transducer. Thus, one op amp can be elimi-
interrupts are ORed together to insure that all A/Ds have nated since the differential to single ended conversion is
completed their conversion before the microprocessor is provided by the differential input of the ADC0801 series. In
interrupted. general, a transducer preamp is required to take advantage
The subroutine, DATA IN, may be called from anywhere in of the full A/D converter input dynamic range.
the user’s program. Once called, this routine initializes the
31 www.national.com
DS005671-26
Note 23: Numbers in parentheses refer to MC6800 CPU pin out.

Note 24: Numbers of letters in brackets refer to standard M6800 system common bus code.
FIGURE 17. Interfacing Multiple A/Ds in an MC6800 System
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SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM
DS005671-A3
SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A/D’s IN AN MC6800 SYSTEM
DS005671-A4
Note 25: In order for the microprocessor to service subroutines and interrupts, the stack pointer must be dimensioned in the user’s program.
For amplification of DC input signals, a major system error is where IX is the current through resistor RX. All of the offset
the input offset voltage of the amplifiers used for the preamp. error terms can be cancelled by making ± IXRX = VOS1 +
Figure 18 is a gain of 100 differential preamp whose offset VOS3 − VOS2. This is the principle of this auto-zeroing
voltage errors will be cancelled by a zeroing subroutine scheme.
which is performed by the INS8080A microprocessor sys- The INS8080A uses the 3 I/O ports of an INS8255 Progra-
tem. The total allowable input offset voltage error for this mable Peripheral Interface (PPI) to control the auto zeroing
preamp is only 50 µV for 1⁄4 LSB error. This would obviously and input data from the ADC0801 as shown in Figure 19.
require very precise amplifiers. The expression for the differ- The PPI is programmed for basic I/O operation (mode 0) with
ential output voltage of the preamp is: Port A being an input port and Ports B and C being output
ports. Two bits of Port C are used to alternately open or close
the 2 switches at the input of the preamp. Switch SW1 is
closed to force the preamp’s differential input to be zero
during the zeroing subroutine and then opened and SW2 is
then closed for conversion of the actual differential input
signal. Using 2 switches in this manner eliminates concern
for the ON resistance of the switches as they must conduct
only the input bias current of the input amplifiers.
Output Port B is used as a successive approximation regis-
ter by the 8080 and the binary scaled resistors in series with
each output bit create a D/A converter. During the zeroing
subroutine, the voltage at Vx increases or decreases as
required to make the differential output voltage equal to zero.
This is accomplished by ensuring that the voltage at the
output of A1 is approximately 2.5V so that a logic “1” (5V) on
33 www.national.com
Functional Description (Continued) the ADC0801. It is important that the voltage levels that drive
the auto-zero resistors be constant. Also, for symmetry, a
any output of Port B will source current into node VX thus logic swing of 0V to 5V is convenient. To achieve this, a
raising the voltage at VX and making the output differential CMOS buffer is used for the logic output signals of Port B
more negative. Conversely, a logic “0” (0V) will pull current and this CMOS package is powered with a stable 5V source.
out of node VX and decrease the voltage, causing the differ- Buffer amplifier A1 is necessary so that it can source or sink
ential output to become more positive. For the resistor val- the D/A output current.
ues shown, VX can move ± 12 mV with a resolution of 50 µV,
which will null the offset error term to 1⁄4 LSB of full-scale for
DS005671-91
Note 26: R2 = 49.5 R1

Note 27: Switches are LMC13334 CMOS analog switches.
Note 28: The 9 resistors used in the auto-zero section can be ± 5% tolerance.
FIGURE 18. Gain of 100 Differential Transducer Preamp
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DS005671-92
FIGURE 19. Microprocessor Interface Circuitry for Differential Preamp

A flow chart for the zeroing subroutine is shown in Figure 20. need for the CPU to determine which device requires servic-
It must be noted that the ADC0801 series will output an all ing. Figure 22 and the accompanying software is a method
zero code when it converts a negative input [VIN(−) ≥ VIN(+)]. of determining which of 7 ADC0801 converters has com-
Also, a logic inversion exists as all of the I/O ports are pleted a conversion (INTR asserted) and is requesting an
buffered with inverting gates. interrupt. This circuit allows starting the A/D converters in
Basically, if the data read is zero, the differential output any sequence, but will input and store valid data from the
voltage is negative, so a bit in Port B is cleared to pull VX converters with a priority sequence of A/D 1 being read first,
more negative which will make the output more positive for A/D 2 second, etc., through A/D 7 which would have the
the next conversion. If the data read is not zero, the output lowest priority for data being read. Only the converters
voltage is positive so a bit in Port B is set to make VX more whose INT is asserted will be read.
positive and the output more negative. This continues for 8 The key to decoding circuitry is the DM74LS373, 8-bit D type
approximations and the differential output eventually con- flip-flop. When the Z-80 acknowledges the interrupt, the
verges to within 5 mV of zero. program is vectored to a data input Z-80 subroutine. This
The actual program is given in Figure 21. All addresses used subroutine will read a peripheral status word from the
are compatible with the BLC 80/10 microcomputer system. DM74LS373 which contains the logic state of the INTR
In particular: outputs of all the converters. Each converter which initiates
an interrupt will place a logic “0” in a unique bit position in the
Port A and the ADC0801 are at port address E4
status word and the subroutine will determine the identity of
Port B is at port address E5 the converter and execute a data read. An identifier word
Port C is at port address E6 (which indicates which A/D the data came from) is stored in
PPI control word port is at port address E7 the next sequential memory location above the location of
the data so the program can keep track of the identity of the
Program Counter automatically goes to ADDR:3C3D upon
data entered.
acknowledgement of an interrupt from the ADC0801
5.3 Multiple A/D Converters in a Z-80 Interrupt

Driven Mode
In data acquisition systems where more than one A/D con-
verter (or other peripheral device) will be interrupting pro-
gram execution of a microprocessor, there is obviously a
35 www.national.com
DS005671-28
FIGURE 20. Flow Chart for Auto-Zero Routine
www.national.com 36
DS005671-A5
Note 29: All numerical values are hexadecimal representations.
FIGURE 21. Software for Auto-Zeroed Differential A/D

5.3 Multiple A/D Converters in a Z-80 Interrupt Driven • The stack pointer must be dimensioned in the main pro-
Mode (Continued) gram as the RST 7 instruction automatically pushes the
The following notes apply: PC onto the stack and the subroutine uses an additional
6 stack addresses.
• It is assumed that the CPU automatically performs a RST
7 instruction when a valid interrupt is acknowledged • The peripherals of concern are mapped into I/O space
(CPU is in interrupt mode 1). Hence, the subroutine with the following port assignments:
starting address of X0038.
• The address bus from the Z-80 and the data bus to the
Z-80 are assumed to be inverted by bus drivers.
• A/D data and identifying words will be stored in sequen-
tial memory locations starting at the arbitrarily chosen
address X 3E00.
37 www.national.com
Functional Description (Continued) HEX PORT ADDRESS PERIPHERAL
04 A/D 4
HEX PORT ADDRESS PERIPHERAL 05 A/D 5
00 MM74C374 8-bit flip-flop 06 A/D 6
01 A/D 1 07 A/D 7
02 A/D 2 This port address also serves as the A/D identifying word in
03 A/D 3 the program.
DS005671-29
FIGURE 22. Multiple A/Ds with Z-80 Type Microprocessor
www.national.com 38
DS005671-A6
39 www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
SO Package (M)
Order Number ADC0802LCWM or ADC0804LCWM
NS Package Number M20B
Molded Dual-In-Line Package (N)

Order Number ADC0801LCN, ADC0802LCN,
ADC0803LCN, ADC0804LCN or ADC0805LCN
NS Package Number N20A
www.national.com 40
ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters
Notes
LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform
into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
whose failure to perform when properly used in the life support device or system, or to affect its
accordance with instructions for use provided in the safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Asia Pacific Customer Japan Ltd.
Americas Fax: +49 (0) 180-530 85 86 Response Group Tel: 81-3-5639-7560
Email: support@nsc.com Email: europe.support@nsc.com Tel: 65-2544466 Fax: 81-3-5639-7507
Deutsch Tel: +49 (0) 69 9508 6208 Fax: 65-2504466
English Tel: +44 (0) 870 24 0 2171 Email: ap.support@nsc.com
www.national.com Français Tel: +33 (0) 1 41 91 8790
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Features
• Compatible with MCS-51® Products
• 4K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
•
•
Six Interrupt Sources
Full Duplex UART Serial Channel
8-bit
•
•
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Microcontroller
• Watchdog Timer
• Dual Data Pointer with 4K Bytes
• Power-off Flag
• Fast Programming Time In-System
• Flexible ISP Programming (Byte and Page Mode)
Programmable
Description Flash
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
AT89S51
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a
monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of
RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-
vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
Rev. 2487A–10/01
1
Pin Configurations
PDIP PLCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.0 1 40 VCC
VCC
P1.4
P1.3
P1.2
P1.1
P1.0
NC
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
6
5
4
3
2
1
44
43
42
41
40
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3) (MOSI) P1.5 7 39 P0.4 (AD4)
(MOSI) P1.5 6 35 P0.4 (AD4) (MISO) P1.6 8 38 P0.5 (AD5)
(MISO) P1.6 7 34 P0.5 (AD5) (SCK) P1.7 9 37 P0.6 (AD6)
(SCK) P1.7 8 33 P0.6 (AD6) RST 10 36 P0.7 (AD7)
RST 9 32 P0.7 (AD7) (RXD) P3.0 11 35 EA/VPP
(RXD) P3.0 10 31 EA/VPP NC 12 34 NC
(TXD) P3.1 11 30 ALE/PROG (TXD) P3.1 13 33 ALE/PROG
(INT0) P3.2 12 29 PSEN (INT0) P3.2 14 32 PSEN
(INT1) P3.3 13 28 P2.7 (A15) (INT1) P3.3 15 31 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14) (T0) P3.4 16 30 P2.6 (A14)
(T1) P3.5 15 26 P2.5 (A13) (T1) P3.5 17 29 P2.5 (A13)
18
19
20
21
22
23
24
25
26
27
28
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
TQFP
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
VCC
P1.4
P1.3
P1.2
P1.1
P1.0
NC
44
43
42
41
40
39
38
37
36
35
34
(MOSI) P1.5 1 33 P0.4 (AD4)

(MISO) P1.6 2 32 P0.5 (AD5)
(SCK) P1.7 3 31 P0.6 (AD6)
RST 4 30 P0.7 (AD7)
(RXD) P3.0 5 29 EA/VPP
NC 6 28 NC
(TXD) P3.1 7 27 ALE/PROG
(INT0) P3.2 8 26 PSEN
(INT1) P3.3 9 25 P2.7 (A15)
(T0) P3.4 10 24 P2.6 (A14)
(T1) P3.5 11 23 P2.5 (A13)
12
13
14
15
16
17
18
19
20
21
22
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
2 AT89S51
2487A–10/01
AT89S51
Block Diagram
P0.0 - P0.7 P2.0 - P2.7
VCC
PORT 0 DRIVERS PORT 2 DRIVERS
GND
RAM ADDR. PORT 0 PORT 2

REGISTER RAM LATCH LATCH FLASH
PROGRAM
B STACK ADDRESS
REGISTER ACC POINTER REGISTER
BUFFER
TMP2 TMP1
PC
ALU INCREMENTER
INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS
PROGRAM
PSW COUNTER
PSEN
ALE/PROG TIMING INSTRUCTION
AND REGISTER DUAL DPTR
EA / VPP CONTROL
RST
WATCH PORT 3 PORT 1 ISP PROGRAM

DOG LATCH LATCH PORT LOGIC
OSC
PORT 3 DRIVERS PORT 1 DRIVERS
P3.0 - P3.7 P1.0 - P1.7
3
2487A–10/01
Pin Description
VCC Supply voltage.
GND Ground.
Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance
inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes
during program verification. External pull-ups are required during program verification.
Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin Alternate Functions

P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)
pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe-
cial Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash pro-
gramming and verification.
pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S51, as shown in the
following table.
4 AT89S51
2487A–10/01
AT89S51
Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-
RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state
of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may
be used for external timing or clocking purposes. Note, however, that one ALE pulse is
skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode.
PSEN Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S51 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each access
to external data memory.
EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (V PP ) during Flash
programming.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier
5
2487A–10/01
Special A map of the on-chip memory area called the Special Function Register (SFR) space is shown
Function in Table 1.
Registers Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data,
and write accesses will have an indeterminate effect.
Table 1. AT89S51 SFR Map and Reset Values
0F8H 0FFH
B
0F0H 0F7H
00000000
0E8H 0EFH
ACC
0E0H 0E7H
00000000
0D8H 0DFH
PSW
0D0H 0D7H
00000000
0C8H 0CFH
0C0H 0C7H
IP
0B8H 0BFH
XX000000
P3
0B0H 0B7H
11111111
IE
0A8H 0AFH
0X000000
P2 AUXR1 WDTRST
0A0H 0A7H
11111111 XXXXXXX0 XXXXXXXX
SCON SBUF
98H 9FH
00000000 XXXXXXXX
P1
90H 97H
11111111
TCON TMOD TL0 TL1 TH0 TH1 AUXR

88H 8FH
00000000 00000000 00000000 00000000 00000000 00000000 XXX00XX0
P0 SP DP0L DP0H DP1L DP1H PCON

80H 87H
11111111 00000111 00000000 00000000 00000000 00000000 0XXX0000
6 AT89S51
2487A–10/01
AT89S51
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities
can be set for each of the five interrupt sources in the IP register.
Table 2. AUXR: Auxiliary Register

AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit
Addressable
– – – WDIDLE DISRTO – – DISALE
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion

DISALE Disable/Enable ALE
DISALE
Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
7
2487A–10/01
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR.
POF is set to “1” during power up. It can be set and rest under software control and is not
affected by reset.
Table 3. AUXR1: Auxiliary Register 1

AUXR1
Address = A2H
Reset Value = XXXXXXX0B
Not Bit
Addressable
– – – – – – – DPS
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion

DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
Memory MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
Organization
Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through
FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are
directed to external memory.
Data Memory The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.
Watchdog The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
Timer
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a
(One-time user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).
Enabled with When the WDT is enabled, it will increment every machine cycle while the oscillator is running.
The WDT timeout period is dependent on the external clock frequency. There is no way to dis-
Reset-out) able the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment
every machine cycle while the oscillator is running. This means the user must reset the WDT
at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it
8 AT89S51
2487A–10/01
AT89S51
should be serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.
WDT During In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down
Power-down mode: by a hardware reset or via a level-activated external interrupt, which is
and Idle enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To pre-
vent the WDT from resetting the device while the interrupt pin is held low, the WDT is not
started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-
rupt service for the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best
to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit =
0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and
reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
UART The UART in the AT89S51 operates the same way as the UART in the AT89C51. For further
information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com).
From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then
‘Product Overview’.
Timer 0 and 1 Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the
AT89C51. For further information on the timers’ operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.
Interrupts The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in
Figure 1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 4 shows that bit position IE.6 is unimplemented. In the AT89S51, bit position
IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they
may be used in future AT89 products.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle
9
2487A–10/01
.
Table 4. Interrupt Enable (IE) Register

(MSB) (LSB)
EA – – ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing
its enable bit.
– IE.6 Reserved
– IE.5 Reserved
ES IE.4 Serial Port interrupt enable bit
ET1 IE.3 Timer 1 interrupt enable bit
EX1 IE.2 External interrupt 1 enable bit
ET0 IE.1 Timer 0 interrupt enable bit
EX0 IE.0 External interrupt 0 enable bit
User software should never write 1s to reserved bits, because they may be used in future AT89
products.
Figure 1. Interrupt Sources
0
INT0 IE0
1
TF0
0
INT1 IE1
1
TF1
TI
RI
10 AT89S51
2487A–10/01
AT89S51
Oscillator XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
Characteristics configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in Figure 3. There are no require-
ments on the duty cycle of the external clock signal, since the input to the internal clocking
circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
Figure 2. Oscillator Connections

C2
XTAL2
C1
XTAL1
GND
Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators
Figure 3. External Clock Drive Configuration
NC XTAL2
EXTERNAL
OSCILLATOR XTAL1
SIGNAL
GND
Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special function
registers remain unchanged during this mode. The idle mode can be terminated by any
enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
Power-down In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-
Mode down is the last instruction executed. The on-chip RAM and Special Function Registers retain
their values until the Power-down mode is terminated. Exit from Power-down mode can be ini-
tiated either by a hardware reset or by activation of an enabled external interrupt into INT0 or
INT1. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not
be activated before VCC is restored to its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
11
2487A–10/01
Table 5. Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
Program The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed
Memory Lock (P) to obtain the additional features listed in the following table.
Bits Table 6. Lock Bit Protection Modes

Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executed from external program
memory are disabled from fetching code bytes from internal
memory, EA is sampled and latched on reset, and further
programming of the Flash memory is disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also disabled
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during
reset. If the device is powered up without a reset, the latch initializes to a random value and
holds that value until reset is activated. The latched value of EA must agree with the current
logic level at that pin in order for the device to function properly.
Programming The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compati-
the Flash –
ble with conventional third-party Flash or EPROM programmers.
Parallel Mode
The AT89S51 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89S51, the address, data, and control
signals should be set up according to the Flash programming mode table and Figures 13 and
14. To program the AT89S51, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
Data Polling: The AT89S51 features Data Polling to indicate the end of a byte write cycle.
During a write cycle, an attempted read of the last byte written will result in the complement of
the written data on P0.7. Once the write cycle has been completed, true data is valid on all out-
puts, and the next cycle may begin. Data Polling may begin any time after a write cycle has
been initiated.
12 AT89S51
2487A–10/01
AT89S51
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY out-
put signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0
is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the individ-
ual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled
to a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H indicates 89S51
(200H) = 06H
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the
proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase
instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data output.
Programming The Code memory array can be programmed using the serial ISP interface while RST is
pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After
the Flash –
RST is set high, the Programming Enable instruction needs to be executed first before other
Serial Mode operations can be executed. Before a reprogramming sequence can occur, a Chip Erase
operation is required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be con-
nected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be
less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK fre-
quency is 2 MHz.
Serial To program and verify the AT89S51 in the serial programming mode, the following sequence
Programming is recommended:
Algorithm 1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz
clock to XTAL1 pin and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Programming Enable serial instruction to
pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be
less than the CPU clock at XTAL1 divided by 16.
3. The Code array is programmed one byte at a time in either the Byte or Page mode.
The write cycle is self-timed and typically takes less than 0.5 ms at 5V.
4. Any memory location can be verified by using the Read instruction that returns the con-
tent at the selected address at serial output MISO/P1.6.
5. At the end of a programming session, RST can be set low to commence normal device
operation.
13
2487A–10/01
Power-off sequence (if needed):
Set XTAL1 to “L” (if a crystal is not used).
Set RST to “L”.
Turn VCC power off.
Data Polling: The Data Polling feature is also available in the serial mode. In this mode, dur-
ing a write cycle an attempted read of the last byte written will result in the complement of the
MSB of the serial output byte on MISO.
Serial The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 8
Programming on page 18.
Instruction Set
Programming Every code byte in the Flash array can be programmed by using the appropriate combination
Interface – of control signals. The write operation cycle is self-timed and once initiated, will automatically
time itself to completion.
Parallel Mode
All major programming vendors offer worldwide support for the Atmel microcontroller series.
Please contact your local programming vendor for the appropriate software revision.
Table 7. Flash Programming Modes

P2.3-0 P1.7-0
ALE/ EA/ P0.7-0
Mode VCC RST PSEN PROG VPP P2.6 P2.7 P3.3 P3.6 P3.7 Data Address
(2)
Write Code Data 5V H L 12V L H H H H DIN A11-8 A7-0
Read Code Data 5V H L H H L L L H H DOUT A11-8 A7-0

(3)
Write Lock Bit 1 5V H L 12V H H H H H X X X
(3)
Write Lock Bit 2 5V H L 12V H H H L L X X X
(3)
Write Lock Bit 3 5V H L 12V H L H H L X X X
P0.2,
Read Lock Bits
5V H L H H H H L H L P0.3, X X
1, 2, 3
P0.4
(1)
Chip Erase 5V H L 12V H L H L L X X X
Read Atmel ID 5V H L H H L L L L L 1EH 0000 00H
Read Device ID 5V H L H H L L L L L 51H 0001 00H
Read Device ID 5V H L H H L L L L L 06H 0010 00H

Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.
2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.
3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.
4. RDY/BSY signal is output on P3.0 during programming.
5. X = don’t care.
14 AT89S51
2487A–10/01
AT89S51
Figure 4. Programming the Flash Memory (Parallel Mode)

VCC
AT89S51
A0 - A7 VCC
ADDR. P1.0-P1.7
0000H/FFFH PGM
P2.0 - P2.3 P0 DATA
A8 - A11
P2.6
SEE FLASH P2.7 ALE PROG
PROGRAMMING P3.3
MODES TABLE P3.6
P3.7
XTAL2 EA VIH/VPP
3-33 MHz
RDY/
P3.0
BSY
XTAL1 RST VIH
GND PSEN
Figure 5. Verifying the Flash Memory (Parallel Mode)

VCC
AT89S51
A0 - A7 VCC
ADDR. P1.0-P1.7
0000H/FFFH PGM DATA
P2.0 - P2.3 P0 (USE 10K
A8 - A11
PULLUPS)
P2.6
SEE FLASH P2.7 ALE
PROGRAMMING P3.3
MODES TABLE P3.6
VIH
P3.7
XTAL 2 EA
3-33 MHz
XTAL1 RST VIH
GND PSEN
15
2487A–10/01
Flash Programming and Verification Characteristics (Parallel Mode)
TA = 20°C to 30°C, VCC = 4.5 to 5.5V
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 11.5 12.5 V

IPP Programming Supply Current 10 mA
ICC VCC Supply Current 30 mA
1/tCLCL Oscillator Frequency 3 33 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold After PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold After PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold After PROG 10 µs
tGLGH PROG Width 0.2 1 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float After ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 50 µs
Figure 6. Flash Programming and Verification Waveforms – Parallel Mode

PROGRAMMING VERIFICATION
P1.0 - P1.7
ADDRESS ADDRESS
P2.0 - P2.3
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tGHDX
tAVGL tGHAX
ALE/PROG
tSHGL tGHSL
tGLGH
VPP LOGIC 1
EA/VPP LOGIC 0
tEHSH tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY) BUSY READY
tWC
16 AT89S51
2487A–10/01
AT89S51
Figure 7. Flash Memory Serial Downloading

VCC
AT89S51
VCC
INSTRUCTION
INPUT P1.5/MOSI
DATA OUTPUT P1.6/MISO
CLOCK IN P1.7/SCK
XTAL2
3-33 MHz
XTAL1 RST VIH
GND
Flash Programming and Verification Waveforms – Serial Mode

Figure 8. Serial Programming Waveforms
7 6 5 4 3 2 1 0
17
2487A–10/01
Table 8. Serial Programming Instruction Set
Instruction
Format
Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming
0110 1001 while RST is high
(Output)
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash memory
array
Read Program Memory 0010 0000 xxxx Read data from Program
A11
A1
A8
A10
A9
A5
A3
A6
A4
A2
A0
D7
A7
D6
D5
D4
D3
D0
D2
D1
(Byte Mode) memory in the byte mode
Write Program Memory 0100 0000 xxxx Write data to Program
A1
D7
D6
A5
D5
D3
D0
A3
D4
D1
A11
A6
A2
A0
D2
A7
A4
A8
A10
A9
(Byte Mode) memory in the byte mode
Write Lock Bits(2)
B2
B1
1010 1100 1110 00 xxxx xxxx xxxx xxxx Write Lock bits. See Note (2).
Read Lock Bits 0010 0100 xxxx xxxx xxxx xxxx xx xx Read back current status of
LB1
LB2
LB3
the lock bits (a programmed
lock bit reads back as a “1”)
Read Signature Bytes(1) 0010 1000 xxx xxx xxxx Signature Byte Read Signature Byte
A5
A4
A3
A2
A1
A0
Read Program Memory 0011 0000 xxxx Byte 0 Byte 1... Read data from Program
A11
A8
A10
A9
(Page Mode) Byte 255 memory in the Page Mode

(256 bytes)
Write Program Memory 0101 0000 xxxx Byte 0 Byte 1... Write data to Program
A11
A8
A10
A9
(Page Mode) Byte 255 memory in the Page Mode

(256 bytes)
Notes: 1. The signature bytes are not readable in Lock Bit Modes 3 and 4.
2. B1 = 0, B2 = 0 →Mode 1, no lock protection
B1 = 0, B2 = 1 →Mode 2, lock bit 1 activated
} Each of the lock bits needs to be activated sequentially before
Mode 4 can be executed.
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data
bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to
be decoded.
18 AT89S51
2487A–10/01
AT89S51
Serial Programming Characteristics
Figure 9. Serial Programming Timing
MOSI
tOVSH tSHOX tSLSH
SCK
tSHSL
MISO
tSLIV
Table 9. Serial Programming Characteristics, TA = -40° C to 85° C, VCC = 4.0 - 5.5V (Unless Otherwise Noted)
Symbol Parameter Min Typ Max Units
tCLCL Oscillator Period 30 ns
tSHSL SCK Pulse Width High 8 tCLCL ns
tSLSH SCK Pulse Width Low 8 tCLCL ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
tSLIV SCK Low to MISO Valid 10 16 32 ns
tERASE Chip Erase Instruction Cycle Time 500 ms
tSWC Serial Byte Write Cycle Time 64 tCLCL + 400 µs
19
2487A–10/01
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 6.6V conditions for extended periods may affect
device reliability.
DC Output Current...................................................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol Parameter Condition Min Max Units
VIL Input Low Voltage (Except EA) -0.5 0.2 VCC-0.1 V
VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V
VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V
VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V
Output Low Voltage(1) (Ports 0.45 V
VOL 1,2,3) IOL = 1.6 mA
(1)
Output Low Voltage 0.45 V
VOL1 (Port 0, ALE, PSEN) IOL = 3.2 mA
IOH = -60 µA, VCC = 5V ± 10% 2.4 V
IOH = -25 µA 0.75 VCC V
Output High Voltage
VOH (Ports 1,2,3, ALE, PSEN) IOH = -10 µA 0.9 VCC V
IOH = -800 µA, VCC = 5V ± 10% 2.4 V
IOH = -300 µA 0.75 VCC V
Output High Voltage
VOH1 (Port 0 in External Bus Mode) IOH = -80 µA 0.9 VCC V
Logical 0 Input Current (Ports -50 µA
IIL 1,2,3) VIN = 0.45V
Logical 1 to 0 Transition Current -650 µA
ITL (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10%
Input Leakage Current (Port 0, ±10 µA
ILI EA) 0.45 < VIN < VCC
RRST Reset Pulldown Resistor 50 300 KΩ
CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
Active Mode, 12 MHz 25 mA
Power Supply Current Idle Mode, 12 MHz 6.5 mA
(2)
ICC Power-down Mode VCC = 5.5V 50 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
20 AT89S51
2487A–10/01
AT89S51
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics

12 MHz Oscillator Variable Oscillator
Symbol Parameter Min Max Min Max Units
tLHLL ALE Pulse Width 127 2tCLCL-40 ns
tAVLL Address Valid to ALE Low 43 tCLCL-25 ns
tLLAX Address Hold After ALE Low 48 tCLCL-25 ns
tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns
tLLPL ALE Low to PSEN Low 43 tCLCL-25 ns
tPLPH PSEN Pulse Width 205 3tCLCL-45 ns
tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-60 ns
tPXIX Input Instruction Hold After PSEN 0 0 ns
tPXIZ Input Instruction Float After PSEN 59 tCLCL-25 ns
tPXAV PSEN to Address Valid 75 tCLCL-8 ns
tAVIV Address to Valid Instruction In 312 5tCLCL-80 ns
tPLAZ PSEN Low to Address Float 10 10 ns
tRLRH RD Pulse Width 400 6tCLCL-100 ns
tWLWH WR Pulse Width 400 6tCLCL-100 ns
tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns
tRHDX Data Hold After RD 0 0 ns
tRHDZ Data Float After RD 97 2tCLCL-28 ns
tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns
tAVDV Address to Valid Data In 585 9tCLCL-165 ns
tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns
tAVWL Address to RD or WR Low 203 4tCLCL-75 ns
tQVWX Data Valid to WR Transition 23 tCLCL-30 ns
tQVWH Data Valid to WR High 433 7tCLCL-130 ns
tWHQX Data Hold After WR 33 tCLCL-25 ns
tRLAZ RD Low to Address Float 0 0 ns
tWHLH RD or WR High to ALE High 43 123 tCLCL-25 tCLCL+25 ns
21
2487A–10/01
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL tLLIV
tLLPL
PSEN tPLIV
tPXAV
tPLAZ
tPXIZ
tLLAX
tPXIX
PORT 0 A0 - A7 INSTR IN A0 - A7
tAVIV
PORT 2 A8 - A15 A8 - A15
External Data Memory Read Cycle

tLHLL
ALE
tWHLH
PSEN
tLLDV
tRLRH
tLLWL
RD tLLAX
tRLDV tRHDZ
tAVLL
tRLAZ
tRHDX
PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN
tAVWL
tAVDV
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
22 AT89S51
2487A–10/01
AT89S51
External Data Memory Write Cycle

tLHLL
ALE
tWHLH
PSEN
tLLWL tWLWH
WR tLLAX
tAVLL tQVWX tWHQX
tQVWH
PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN
tAVWL
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
External Clock Drive Waveforms

tCHCX
tCHCX tCLCH tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V

0.45V
tCLCX
tCLCL
External Clock Drive

Symbol Parameter Min Max Units
tCLCL Clock Period 30 ns
tCHCX High Time 12 ns
tCLCX Low Time 12 ns
tCLCH Rise Time 5 ns
tCHCL Fall Time 5 ns
23
2487A–10/01
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc Variable Oscillator
Symbol Parameter Min Max Min Max Units
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns
tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-80 ns
tXHDX Input Data Hold After Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns
Shift Register Mode Timing Waveforms

INSTRUCTION 0 1 2 3 4 5 6 7 8
ALE
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF 0 1 2 3 4 5 6 7
tXHDX
OUTPUT DATA tXHDV SET TI
CLEAR RI VALID VALID VALID VALID VALID VALID VALID VALID
INPUT DATA SET RI
AC Testing Input/Output Waveforms(1)

VCC - 0.5V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
0.45V
Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH
min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
V LOAD+ 0.1V V OL - 0.1V
V LOAD Timing Reference

Points
V LOAD - 0.1V V OL + 0.1V
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.
24 AT89S51
2487A–10/01
AT89S51
Speed Power
(MHz) Supply Ordering Code Package Operation Range
24 4.0V to 5.5V AT89S51-24AC 44A Commercial
AT89S51-24JC 44J (0° C to 70° C)
AT89S51-24PC 40P6
AT89S51-24AI 44A Industrial
AT89S51-24JI 44J (-40° C to 85° C)
AT89S51-24PI 40P6
33 4.5V to 5.5V AT89S51-33AC 44A Commercial
AT89S51-33JC 44J (0° C to 70° C)
AT89S51-33PC 40P6
= Preliminary Availability
Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
25
2487A–10/01
Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Flat Package (TQFP) Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
.045(1.14) X 45° PIN NO. 1 .045(1.14) X 30° - 45° .012(.305)

12.21(0.478) IDENTIFY .008(.203)
PIN 1 ID SQ
11.75(0.458)
.656(16.7) .630(16.0)
SQ
.650(16.5) .590(15.0)
0.45(0.018) .032(.813) .021(.533)
0.80(0.031) BSC 0.30(0.012) .695(17.7)
.026(.660) SQ .013(.330)
.685(17.4)
.050(1.27) TYP .043(1.09)

.500(12.7) REF SQ .020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
10.10(0.394) .165(4.19)
SQ
9.90(0.386)
1.20(0.047) MAX
0
0.20(.008) 7
0.09(.003) .022(.559) X 45° MAX (3X)
0.75(0.030) 0.15(0.006)
0.45(0.018) 0.05(0.002)
*Controlling dimension: millimeters
40P6, 40-pin, 0.600" Wide, Plastic Dual Inline

Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6)
2.04(51.8) PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
1.900(48.26) REF MAX
.220(5.59) .005(.127)
MAX MIN
SEATING
PLANE
.065(1.65)
.161(4.09) .015(.381)
.125(3.18)
.022(.559)
.065(1.65) .014(.356)
.110(2.79) .041(1.04)
.090(2.29)
.630(16.0)
.590(15.0)
0 REF
.012(.305) 15
.008(.203)
.690(17.5)
.610(15.5)
26 AT89S51
2487A–10/01
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2487A–10/01/xM
XR-2206
Monolithic
...the analog plus company TM Function Generator
June 1997-3
FEATURES APPLICATIONS
Waveform Generation
Low-Sine Wave Distortion, 0.5%, Typical
Excellent Temperature Stability, 20ppm/°C, Typ. Sweep Generation
Wide Sweep Range, 2000:1, Typical AM/FM Generation
Low-Supply Sensitivity, 0.01%V, Typ.
V/F Conversion
Linear Amplitude Modulation
FSK Generation
TTL Compatible FSK Controls
Wide Supply Range, 10V to 26V Phase-Locked Loops (VCO)
Adjustable Duty Cycle, 1% TO 99%
GENERAL DESCRIPTION
The XR-2206 is a monolithic function generator The circuit is ideally suited for communications,
integrated circuit capable of producing high quality sine, instrumentation, and function generator applications
square, triangle, ramp, and pulse waveforms of requiring sinusoidal tone, AM, FM, or FSK generation. It
high-stability and accuracy. The output waveforms can be has a typical drift specification of 20ppm/°C. The oscillator
both amplitude and frequency modulated by an external frequency can be linearly swept over a 2000:1 frequency
voltage. Frequency of operation can be selected range with an external control voltage, while maintaining
externally over a range of 0.01Hz to more than 1MHz. low distortion.
ORDERING INFORMATION
Operating
Part No. Package Temperature Range
XR-2206M 16 Lead 300 Mil CDIP -55°C to +125°C
XR-2206P 16 Lead 300 Mil PDIP –40°C to +85°C
XR-2206CP 16 Lead 300 Mil PDIP 0°C to +70°C
XR-2206D 16 Lead 300 Mil JEDEC SOIC 0°C to +70°C
Rev. 1.03
1972
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 (510) 668-7017
1
XR-2206
VCC GND BIAS

4 12 10
11 SYNCO
TC1 5
Timing
Capacitor VCO
TC2 6
TR1 7
Timing
Resistors Current Multiplier
8 Switches And Sine
TR2 +1 2 STO
Shaper
FSKI 9
AMSI 1 3 MO
WAVEA1 13
WAVEA2 14
SYMA1 15
SYMA2 16
Figure 1. XR-2206 Block Diagram
Rev. 1.03
2
XR-2206
AMSI 1 16 SYMA2 AMSI 1 16 SYMA2

STO 2 15 SYMA1 STO 2 15 SYMA1
MO 3 14 WAVEA2 MO 3 14 WAVEA2
VCC 4 13 WAVEA1 VCC 4 13 WAVEA1
TC1 5 12 GND TC1 5 12 GND
TC2 6 11 SYNCO TC2 6 11 SYNCO
TR1 7 10 BIAS TR1 7 10 BIAS
TR2 8 9 FSKI TR2 8 9 FSKI
16 Lead PDIP, CDIP (0.300”) 16 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin # Symbol Type Description
1 AMSI I Amplitude Modulating Signal Input.
2 STO O Sine or Triangle Wave Output.
3 MO O Multiplier Output.
4 VCC Positive Power Supply.
5 TC1 I Timing Capacitor Input.
6 TC2 I Timing Capacitor Input.
7 TR1 O Timing Resistor 1 Output.
8 TR2 O Timing Resistor 2 Output.
9 FSKI I Frequency Shift Keying Input.
10 BIAS O Internal Voltage Reference.
11 SYNCO O Sync Output. This output is a open collector and needs a pull up resistor to VCC.
12 GND Ground pin.
13 WAVEA1 I Wave Form Adjust Input 1.
14 WAVEA2 I Wave Form Adjust Input 2.
15 SYMA1 I Wave Symetry Adjust 1.
16 SYMA2 I Wave Symetry Adjust 2.
Rev. 1.03
3
XR-2206
DC ELECTRICAL CHARACTERISTICS
Test Conditions: Test Circuit of Figure 2 Vcc = 12V, TA = 25°C, C = 0.01F, R1 = 100k, R2 = 10k, R3 = 25k
Unless Otherwise Specified. S1 open for triangle, closed for sine wave.
XR-2206M/P XR-2206CP/D
Parameters Min. Typ. Max. Min. Typ. Max. Units Conditions
General Characteristics
Single Supply Voltage 10 26 10 26 V
Split-Supply Voltage +5 +13 +5 +13 V
Supply Current 12 17 14 20 mA R1 10k
Oscillator Section
Max. Operating Frequency 0.5 1 0.5 1 MHz C = 1000pF, R1 = 1k
Lowest Practical Frequency 0.01 0.01 Hz C = 50F, R1 = 2M
Frequency Accuracy +1 +4 +2 % of fo fo = 1/R1C
Temperature Stability +10 +50 +20 ppm/°C 0°C TA 70°C
Frequency R1 = R2 = 20k
Sine Wave Amplitude Stability2 4800 4800 ppm/°C
Supply Sensitivity 0.01 0.1 0.01 %/V VLOW = 10V, VHIGH = 20V,
R1 = R2 = 20k
Sweep Range 1000:1 2000:1 2000:1 fH = fL fH @ R1 = 1k
fL @ R1 = 2M
Sweep Linearity
10:1 Sweep 2 2 % fL = 1kHz, fH = 10kHz
1000:1 Sweep 8 8 % fL = 100Hz, fH = 100kHz
FM Distortion 0.1 0.1 % +10% Deviation
Recommended Timing Components
Timing Capacitor: C 0.001 100 0.001 100 F Figure 5
Timing Resistors: R1 & R2 1 2000 1 2000 k
Triangle Sine Wave Output1 Figure 3
Triangle Amplitude 160 160 mV/k Figure 2, S1 Open
Sine Wave Amplitude 40 60 80 60 mV/k Figure 2, S1 Closed
Max. Output Swing 6 6 Vp-p
Output Impedance 600 600
Triangle Linearity 1 1 %
Amplitude Stability 0.5 0.5 dB For 1000:1 Sweep
Sine Wave Distortion
Without Adjustment 2.5 2.5 % R1 = 30k
With Adjustment 0.4 1.0 0.5 1.5 % See Figure 7 and Figure 8
Notes
1 Output amplitude is directly proportional to the resistance, R , on Pin 3. See Figure 3.
3
2 For maximum amplitude stability, R should be a positive temperature coefficient resistor.
3
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 1.03
4
XR-2206
DC ELECTRICAL CHARACTERISTICS (CONT’D)
XR-2206M/P XR-2206CP/D
Parameters Min. Typ. Max. Min. Typ. Max. Units Conditions
Amplitude Modulation
Input Impedance 50 100 50 100 k
Modulation Range 100 100 %
Carrier Suppression 55 55 dB
Linearity 2 2 % For 95% modulation
Square-Wave Output
Amplitude 12 12 Vp-p Measured at Pin 11.
Rise Time 250 250 ns CL = 10pF
Fall Time 50 50 ns CL = 10pF
Saturation Voltage 0.2 0.4 0.2 0.6 V IL = 2mA
Leakage Current 0.1 20 0.1 100 A VCC = 26V
FSK Keying Level (Pin 9) 0.8 1.4 2.4 0.8 1.4 2.4 V See section on circuit controls
Reference Bypass Voltage 2.9 3.1 3.3 2.5 3 3.5 V Measured at Pin 10.
Notes
1 Output amplitude is directly proportional to the resistance, R , on Pin 3. See Figure 3.
3
2 For maximum amplitude stability, R should be a positive temperature coefficient resistor.
3
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26V Total Timing Current . . . . . . . . . . . . . . . . . . . . . . . . 6mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 750mW Storage Temperature . . . . . . . . . . . . -65°C to +150°C
Derate Above 25°C . . . . . . . . . . . . . . . . . . . . . . 5mW/°C
SYSTEM DESCRIPTION
The XR-2206 is comprised of four functional blocks; a terminals to ground. With two timing pins, two discrete
voltage-controlled oscillator (VCO), an analog multiplier output frequencies can be independently produced for
and sine-shaper; a unity gain buffer amplifier; and a set of FSK generation applications by using the FSK input
current switches. control pin. This input controls the current switches which
The VCO produces an output frequency proportional to select one of the timing resistor currents, and routes it to
an input current, which is set by a resistor from the timing the VCO.
Rev. 1.03
5
XR-2206
VCC
1mF
4
1 Symmetry Adjust
16
5
Mult. 25K
S1 = Open For Triangle
C And 15
VCO = Closed For Sinewave
Sine 14
6 Shaper
S1
13 THD Adjust
9
FSK Input 500
R1 7 Current Triangle Or
2 Sine Wave
R2 8 Switches +1
Output
11 Square Wave
Output
10 12 3 XR-2206
R3 10K
25K
1mF
+ VCC
1mF
VCC
5.1K 5.1K
Figure 2. Basic Test Circuit
6
ÎÎÎÎÎÎÎÎÎÎ
26
Triangle 70°C Max.
Package
Peak Output Voltage (Volts)
5 Dissipation
22
1KW
4
Sinewave
2KW
ICC (mA)
3 18
ÎÎÎÎÎÎÎÎÎÎ 10KW
2
14
1 30KW
0 20 40 60
R3 in (KW)
80 100
10
8 12 16 20
VCC (V)
24 28
Figure 3. Output Amplitude Figure 4. Supply Current vs

as a Function of the Resistor, Supply Voltage, Timing, R
R3, at Pin 3
Rev. 1.03
6
XR-2206
10M
ÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎ
ÁÁÁÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM TIMING R
ÎÎÎÎÎÎÎÎÎÎÎ
Normal Output Amplitude

4V 4V
ÁÁÁÁÁ
1M
Timing Resistor ( W )
ÁÁÁÁÁ
1.0
NORMAL RANGE
100K
ÁÁÁÁÁ ÎÎÎÎÎÎÎÎÎÎÎ
TYPICAL VALUE 0.5
10K
1K
ÁÁÁÁÁ
10-2
MINIMUM TIMING R
10 102 104 106

0
VCC / 2
Frequency (Hz) DC Voltage At Pin 1
Figure 5. R versus Oscillation Frequency. Figure 6. Normalized Output Amplitude

versus DC Bias at AM Input (Pin 1)
ÎÎÎÎÎÎÎÎÎÎÎÎ
5
ÁÁÁÁÁÁÁ
5
ÁÁÁÁÁÁÁ ÁÁÁ
4
ÁÁÁÁÁÁÁ
4
ÁÁÁÁ
C = 0.01mF R=3KW
Trimmed For Minimum
Distortion (%)
VOUT =0.5VRMS Pin 2
ÎÎÎÎÎÎÎÎÎÎÎÎ ÁÁÁÁ
Distortion At 30 KW
Distortion (%)
3 RL=10KW
3
2 2
1 1
0
1.0 10
Timing R K(W)
100 103
0
10 100 1K 10K
Frequency (Hz)
100K 1M
Figure 7. Trimmed Distortion versus Figure 8. Sine Wave Distortion versus

Timing Resistor. Operating Frequency with
Timing Capacitors Varied.
Rev. 1.03
7
XR-2206
C=0.01F
2
R=1M
R=2K
Frequency Drift (%)
1
R=200K R=10K
R=200K
0
R=10K IC IT
Pin 7
R=2K R=1M Rc or 8
-1 Sweep
Input +
R=1K VC IB
- +
-2 3V
R=1K R
ÁÁ
-
12
-3
-50 -25 0 25 50 75 100 125
Ambient Temperature (C°)
Figure 9. Frequency Drift versus Figure 10. Circuit Connection for Frequency Sweep.
Temperature.
VCC
1F
4
1 16
5
Mult. S1 Closed For Sinewave
C 15
VCO And
Sine 14
6 Shaper S1
13 200
9
7 Current
2 Triangle Or
8 Switches +1 Sine Wave Output
2M R1 1K
11 Square Wave
Output
R 10 12 3 XR-2206
R3 10K
+ 50K
1F
+ VCC
10F
VCC
5.1K 5.1K
Figure 11. Circuit tor Sine Wave Generation without External Adjustment.
(See Figure 3 for Choice of R3)
Rev. 1.03
8
XR-2206
VCC
1F
4 Symmetry Adjust
1 16
5
Mult. 25K RB
C And 15 S1 Closed For Sinewave
1 VCO
F= Sine 14
RC 6 Shaper S1
13 RA
9
500
7 Current 2 Triangle Or
2M R1 8 Switches +1 Sine Wave Output
1K
11 Square Wave
Output
R 10 12 3 XR-2206
R3 10K
+ 50K
1F
+ VCC
10F
VCC
5.1K 5.1K
Figure 12. Circuit for Sine Wave Generation with Minimum Harmonic Distortion.
(R3 Determines Output Swing - See Figure 3)
VCC
1F
4
1 16
5
Mult. 15
>2V F1 C VCO And 14
Sine
F2 6 Shaper
<1V
13 200
9
FSK Input
R1 7 Current 2
R2 8 Switches +1 FSK Output
11
F1=1/R1C
F2=1/R2C 10 12 3 XR-2206
R3
+ 50K
1F
+
10F
VCC
5.1K 5.1K
Figure 13. Sinusoidal FSK Generator
Rev. 1.03
9
XR-2206
VCC
1F f 2 1
C R1 R2

4
1 R1
5 16 Duty Cycle =
R1 R2
Mult.
C VCO And 15
Sine 14
6
Shaper
9 13
R1 7 Current
R2 2 Sawtooth Output
8 Switches +1
11
Pulse Output
10 12 3 XR-2206
R3 5.1K
+ 24K
1F
+ VCC
10F
VCC
5.1K 5.1K
Figure 14. Circuit for Pulse and Ramp Generation.
Frequency-Shift Keying APPLICATIONS INFORMATION
The XR-2206 can be operated with two separate timing Sine Wave Generation
resistors, R1 and R2, connected to the timing Pin 7 and 8,
respectively, as shown in Figure 13. Depending on the Without External Adjustment
polarity of the logic signal at Pin 9, either one or the other
of these timing resistors is activated. If Pin 9 is Figure 11 shows the circuit connection for generating a
open-circuited or connected to a bias voltage 2V, only sinusoidal output from the XR-2206. The potentiometer,
R1 is activated. Similarly, if the voltage level at Pin 9 is R1 at Pin 7, provides the desired frequency tuning. The
1V, only R2 is activated. Thus, the output frequency can maximum output swing is greater than V+/2, and the
be keyed between two levels. f1 and f2, as: typical distortion (THD) is < 2.5%. If lower sine wave
distortion is desired, additional adjustments can be
f1 = 1/R1C and f2 = 1/R2C
provided as described in the following section.
For split-supply operation, the keying voltage at Pin 9 is The circuit of Figure 11 can be converted to split-supply
referenced to V-. operation, simply by replacing all ground connections
with V-. For split-supply operation, R3 can be directly
Output DC Level Control connected to ground.
The dc level at the output (Pin 2) is approximately the

same as the dc bias at Pin 3. In Figure 11, Figure 12 and
Figure 13, Pin 3 is biased midway between V+ and
ground, to give an output dc level of V+/2.
Rev. 1.03
10
XR-2206
With External Adjustment: PRINCIPLES OF OPERATION
Description of Controls
The harmonic content of sinusoidal output can be
reduced to -0.5% by additional adjustments as shown in Frequency of Operation:
Figure 12. The potentiometer, RA, adjusts the
The frequency of oscillation, fo, is determined by the
sine-shaping resistor, and RB provides the fine
external timing capacitor, C, across Pin 5 and 6, and by
adjustment for the waveform symmetry. The adjustment
the timing resistor, R, connected to either Pin 7 or 8. The
procedure is as follows:
frequency is given as:
1. Set RB at midpoint and adjust RA for minimum
distortion.
f 0 + 1 Hz
RC
2. With RA set as above, adjust RB to further reduce
distortion.
and can be adjusted by varying either R or C. The
recommended values of R, for a given frequency range,
as shown in Figure 5. Temperature stability is optimum
Triangle Wave Generation
for 4k < R < 200k. Recommended values of C are from
1000pF to 100F.
The circuits of Figure 11 and Figure 12 can be converted
to triangle wave generation, by simply open-circuiting Pin Frequency Sweep and Modulation:
13 and 14 (i.e., S1 open). Amplitude of the triangle is Frequency of oscillation is proportional to the total timing
approximately twice the sine wave output. current, IT, drawn from Pin 7 or 8:
320I T (mA)
f+ Hz
FSK Generation C(F)
Figure 13 shows the circuit connection for sinusoidal FSK Timing terminals (Pin 7 or 8) are low-impedance points,
signal operation. Mark and space frequencies can be and are internally biased at +3V, with respect to Pin 12.
independently adjusted by the choice of timing resistors, Frequency varies linearly with IT, over a wide range of
R1 and R2; the output is phase-continuous during current values, from 1A to 3mA. The frequency can be
transitions. The keying signal is applied to Pin 9. The controlled by applying a control voltage, VC, to the
circuit can be converted to split-supply operation by activated timing pin as shown in Figure 10. The frequency
simply replacing ground with V-. of oscillation is related to VC as:
Pulse and Ramp Generation ǒ V

f+ 1 1 ) R 1 – C
RC RC 3
ǒ ǓǓHz
Figure 14 shows the circuit for pulse and ramp waveform where VC is in volts. The voltage-to-frequency conversion
generation. In this mode of operation, the FSK keying gain, K, is given as:
terminal (Pin 9) is shorted to the square-wave output (Pin
11), and the circuit automatically frequency-shift keys
itself between two separate frequencies during the K + ēfńēV C + – 0.32 HzńV
R CC
positive-going and negative-going output waveforms.
The pulse width and duty cycle can be adjusted from 1%
to 99% by the choice of R1 and R2. The values of R1 and CAUTION: For safety operation of the circuit, IT should be
R2 should be in the range of 1k to 2M. limited to 3mA.
Rev. 1.03
11
XR-2206
Output Amplitude:
Maximum output amplitude is inversely proportional to at Pin 1 is approximately 100k. Output amplitude varies
the external resistor, R3, connected to Pin 3 (see linearly with the applied voltage at Pin 1, for values of dc
Figure 3). For sine wave output, amplitude is bias at this pin, within 14 volts of VCC/2 as shown in
approximately 60mV peak per k of R3; for triangle, the Figure 6. As this bias level approaches VCC/2, the phase
peak amplitude is approximately 160mV peak per k of of the output signal is reversed, and the amplitude goes
R3. Thus, for example, R3 = 50k would produce through zero. This property is suitable for phase-shift
approximately 13V sinusoidal output amplitude. keying and suppressed-carrier AM generation. Total
dynamic range of amplitude modulation is approximately
55dB.
Amplitude Modulation:
CAUTION: AM control must be used in conjunction with a
Output amplitude can be modulated by applying a dc bias well-regulated supply, since the output amplitude now becomes
and a modulating signal to Pin 1. The internal impedance a function of VCC.
VR VCC 11 15 V2 5 14 16 6 13 1 3 2
VCC
7
6
5
8
10
VCC
VR
V1
4
VR
Int’nI.
Reg. V1
VR
V2
12
9
Figure 15. Equivalent Schematic Diagram
Rev. 1.03
12
XR-2206
16 LEAD CERAMIC DUAL-IN-LINE

(300 MIL CDIP)
Rev. 1.00
16 9
1 8
D E1
Base A1
Plane A
Seating L
Plane
e c
B B1 α
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A 0.100 0.200 2.54 5.08

A1 0.015 0.060 0.38 1.52
B 0.014 0.026 0.36 0.66
B1 0.045 0.065 1.14 1.65
c 0.008 0.018 0.20 0.46
D 0.740 0.840 18.80 21.34
E1 0.250 0.310 6.35 7.87
E 0.300 BSC 7.62 BSC
e 0.100 BSC 2.54 BSC
L 0.125 0.200 3.18 5.08
α 0° 15° 0° 15°
Note: The control dimension is the inch column
Rev. 1.03
13
XR-2206
16 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP)
Rev. 1.00
16 9
E1
1 8
D E
A2
Seating A
Plane L C
A1 α
B
e B1 eA
eB
INCHES MILLIMETERS
A 0.145 0.210 3.68 5.33

A1 0.015 0.070 0.38 1.78
A2 0.115 0.195 2.92 4.95
B 0.014 0.024 0.36 0.56
B1 0.030 0.070 0.76 1.78
C 0.008 0.014 0.20 0.38
D 0.745 0.840 18.92 21.34
E 0.300 0.325 7.62 8.26
E1 0.240 0.280 6.10 7.11
e 0.100 BSC 2.54 BSC
eA 0.300 BSC 7.62 BSC
eB 0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
α 0° 15° 0° 15°
Rev. 1.03
14
XR-2206
16 LEAD SMALL OUTLINE

(300 MIL JEDEC SOIC)
Rev. 1.00
16 9
E H
1
8
C
A
Seating
Plane α
e B
A1
INCHES MILLIMETERS
A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30
B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.398 0.413 10.10 10.50
E 0.291 0.299 7.40 7.60
e 0.050 BSC 1.27 BSC
H 0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
α 0° 8° 0° 8°
Note: The control dimension is the millimeter column
Rev. 1.03
15
XR-2206
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1972 EXAR Corporation

Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.03
16
XR-2211
FSK Demodulator/
...the analog plus company TM Tone Decoder
June 1997-3
FEATURES APPLICATIONS
Wide Frequency Range, 0.01Hz to 300kHz

Caller Identification Delivery
Wide Supply Voltage Range, 4.5V to 20V
FSK Demodulation
HCMOS/TTL/Logic Compatibility
Data Synchronization
FSK Demodulation, with Carrier Detection
Wide Dynamic Range, 10mV to 3V rms Tone Decoding
Adjustable Tracking Range, +1% to 80% FM Detection

Excellent Temp. Stability, +50ppm/°C, max. Carrier Detection
GENERAL DESCRIPTION
The XR-2211 is a monolithic phase-locked loop (PLL) quadrature phase detector which provides carrier
system especially designed for data communications detection, and an FSK voltage comparator which provides
applications. It is particularly suited for FSK modem FSK demodulation. External components are used to
applications. It operates over a wide supply voltage range independently set center frequency, bandwidth, and output
of 4.5 to 20V and a wide frequency range of 0.01Hz to delay. An internal voltage reference proportional to the
300kHz. It can accommodate analog signals between power supply is provided at an output pin.
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic The XR-2211 is available in 14 pin packages specified for
PLL for tracking an input signal within the pass band, a military and industrial temperature ranges.
Operating
Part No. Package Temperature Range
XR-2211M 14 Pin CDIP (0.300”) -55°C to +125°C
XR-2211N 14 Pin CDIP (0.300”) -40°C to +85°C
XR-2211P 14 Pin PDIP (0.300”) -40°C to +85°C
XR-2211ID 14 Lead SOIC (Jedec, 0.150”) -40°C to +85°C
Rev. 3.01
1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017
1
XR-2211
BLOCK DIAGRAM
VCC GND NC
1 4 9
Pre Amplifier 11 LDO

INP 2 Loop
-Det 3 LDF
TIM C1 14 Lock
Detect
Comparator
VCO 6 LDOQ
TIM C2 13 Quad
-Det 5 LDOQN
TIM R 12
Internal
VREF 10 VREF
FSK Comp 7 DO
Reference
COMP I 8
Figure 1. XR-2211 Block Diagram
Rev. 3.01
2
XR-2211
PIN CONFIGURATION
VCC 1 14 TIM C1 VCC 1 14 TIM C1

INP 2 13 TIM C2 INP 2 13 TIM C2
LDF 3 12 TIM R LDF 3 12 TIM R
GND 4 11 LDO GND 4 11 LDO
LDOQN 5 10 VREF LDOQN 5 10 VREF
LDOQ 6 9 NC LDOQ 6 9 NC
DO 7 8 COMP I
DO 7 8 COMP I
14 Lead CDIP, PDIP (0.300”) 14 Lead SOIC (Jedec, 0.150”)
PIN DESCRIPTION
Pin # Symbol Type Description
1 VCC Positive Power Supply.
2 INP I Receive Analog Input.
3 LDF O Lock Detect Filter.
4 GND Ground Pin.
5 LDOQN O Lock Detect Output Not. This output will be low if the VCO is in the capture range.
6 LDOQ O Lock Detect Output. This output will be high if the VCO is in the capture range.
7 DO O Data Output. Decoded FSK output.
8 COMP I I FSK Comparator Input.
9 NC Not Connected.
10 VREF O Internal Voltage Reference. The value of VREF is VCC/2 - 650mV.
11 LDO O Loop Detect Output. This output provides the result of the quadrature phase detection.
12 TIM R I Timing Resistor Input. This pin connects to the timing resistor of the VCO.
13 TIM C2 I Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14 TIM C1 I Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
Rev. 3.01
3
XR-2211
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter Min. Typ. Max. Unit Conditions

General
Supply Voltage 4.5 20 V
Supply Current 4 7 mA R0 > 10KW. See Figure 4.
Oscillator Section
Frequency Accuracy +1 +3 % Deviation from fO = 1/R0 C0
Frequency Stability
Temperature +20 +50 ppm/°C See Figure 8.
Power Supply 0.05 0.5 %/V VCC = 12 +1V. See Figure 7.
0.2 %/V VCC = + 5V. See Figure 7.
Upper Frequency Limit 100 300 kHz R0 = 8.2KW, C0 = 400pF
Lowest Practical Operating 0.01 Hz R0 = 2MW, C0 = 50mF
Frequency
Timing Resistor, R0 - See
Figure 5
Operating Range 5 2000 KW
Recommended Range 5 KW See Figure 7 and Figure 8.
Loop Phase Dectector Section
Peak Output Current +150 +200 +300 mA Measured at Pin 11
Output Offset Current 1 mA
Output Impedance 1 MW
Maximum Swing +4 +5 V Referenced to Pin 10
Quadrature Phase Detector Measured at Pin 3
Peak Output Current 100 300 mA
Output Impedance 1 MW
Maximum Swing 11 VPP
Input Preampt Section Measured at Pin 2
Input Impedance 20 KW
Input Signal
Voltage Required to
Cause Limiting 2 10 mV rms
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Rev. 3.01
4
XR-2211
DC ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter Min. Typ. Max. Unit Conditions

Voltage Comparator Section
Input Impedance 2 MW Measured at Pins 3 and 8
Input Bias Current 100 nA
Voltage Gain 55 70 dB RL = 5.1KW
Output Voltage Low 300 500 mV IC = 3mA
Output Leakage Current 0.01 10 mA VO = 20V
Internal Reference
Voltage Level 4.9 5.3 5.7 V Measured at Pin 10
Output Impedance 100 W AC Small Signal
Maximum Source Current 80 mA
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Specifications are subject to change without notice

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Package Power Dissipation Ratings
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms CDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW Derate Above TA = 25°C . . . . . . . . . . . . . . . 8mW/°C
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mW
Derate Above TA = 25°C . . . . . . . . . . . . . . 60mW/°C
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390mW
Derate Above TA = 25°C . . . . . . . . . . . . . . . 5mW/°C
SYSTEM DESCRIPTION
The main PLL within the XR-2211 is constructed from an (internally connected). When in lock, these frequencies
input preamplifier, analog multiplier used as a phase are fIN+ fVCO (2 times fIN when in lock) and fIN - fVCO (0Hz
detector and a precision voltage controlled oscillator when lock). By adding a capacitor to the phase detector
(VCO). The preamplifier is used as a limiter such that output, the 2 times fIN component is reduced, leaving a
input signals above typically 10mV rms are amplified to a DC voltage that represents the phase difference between
constant high level signal. The multiplying-type phase the two frequencies. This closes the loop and allows the
detector acts as a digital exclusive or gate. Its output VCO to track the input frequency.
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a The FSK comparator is used to determine if the VCO is
current controlled oscillator with its normal input current driven above or below the center frequency (FSK
(fO) set by a resistor (R0) to ground and its driving current comparator). This will produce both active high and
with a resistor (R1) from the phase detector. active low outputs to indicate when the main PLL is in lock
The output of the phase detector produces sum and (quadrature phase detector and lock detector
difference of the input and the VCO frequencies comparator).
Rev. 3.01
5
XR-2211
PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this 10 must be bypassed to ground with a 0.1mF capacitor for
terminal. The internal impedance at pin 2 is 20KW. proper operation of the circuit.
Recommended input signal level is in the range of 10mV
rms to 3V rms. Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
Quadrature Phase Detector Output (Pin 3): This is the detector. The PLL loop filter is formed by R1 and C1
connected to pin 11 (see Figure 3.) With no input signal, or
high impedance output of quadrature phase detector and
with no phase error within the PLL, the DC level at pin 11 is
is internally connected to the input of lock detect voltage
very nearly equal to VREF. The peak to peak voltage swing
comparator. In tone detection applications, pin 3 is
available at the phase detector output is equal to 2 x VREF.
connected to ground through a parallel combination of RD
and CD (see Figure 3) to eliminate the chatter at lock VCO Control Input (Pin 12): VCO free-running
detect outputs. If the tone detect section is not used, pin 3 frequency is determined by external timing resistor, R0,
can be left open. connected from this terminal to ground. The VCO
free-running frequency, fO, is:
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
“low” state when the PLL is out of lock and goes to “high”
state when the PLL is locked. It is an open collector type fO 1 Hz
R 0·C 0
output and requires a pull-up resistor, RL, to VCC for
proper operation. At “low” state, it can sink up to 5mA of
load current. where C0 is the timing capacitor across pins 13 and 14.
For optimum temperature stability, R0 must be in the
range of 10KW to 100KW (see Figure 9.)
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6. This terminal is a low impedance point, and is internally
This output is also an open collector type stage which can biased at a DC level equal to VREF. The maximum timing
sink 5mA of load current at low or “on” state. current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
FSK Data Output (Pin 7): This output is an open collector
logic stage which requires a pull-up resistor, RL, to VCC for VCO Timing Capacitor (Pins 13 and 14): VCO
proper operation. It can sink 5mA of load current. When frequency is inversely proportional to the external timing
decoding FSK signals, FSK data output is at “high” or “off” capacitor, C0, connected across these terminals (see
state for low input frequency, and at “low” or “on” state for Figure 6.) C0 must be non-polar, and in the range of
high input frequency. If no input signal is present, the logic 200pF to 10mF.
state at pin 7 is indeterminate.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, RX, in series with R0 at pin 12
FSK Comparator Input (Pin 8): This is the high
(see Figure 10.)
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is VCO Free-Running Frequency, fO: XR-2211 does not
connected between this terminal and the PLL phase have a separate VCO output terminal. Instead, the VCO
detector output (pin 11). This data filter is formed by RF outputs are internally connected to the phase detector
and CF (see Figure 3.) The threshold voltage of the sections of the circuit. For set-up or adjustment purposes,
comparator is set by the internal reference voltage, VREF, the VCO free-running frequency can be tuned by using
available at pin 10. the generalized circuit in Figure 3, and applying an
alternating bit pattern of O’s and 1’s at the known mark
Reference Voltage, VREF (Pin 10): This pin is internally and space frequencies. By adjusting R0, the VCO can
biased at the reference voltage level, VREF: VREF = VCC /2 then be tuned to obtain a 50% duty cycle on the FSK
- 650mV. The DC voltage level at this pin forms an internal output (pin 7). This will ensure that the VCO fO value is
reference for the voltage levels at pins 5, 8, 11 and 12. Pin accurately referenced to the mark and space frequencies.
Rev. 3.01
6
XR-2211
ÎÎÎÎÎÎ Loop
ÎÎ
ÎÎÎÎÎ
Data
ÎÎÎÎÎÎ
Filter Filter FSK
Output
ÎÎÎÎÎÎ ÎÎÎÎÎ
φ Det
FSK
Comp
ÎÎÎ ÎÎÎ φ
ÎÎÎ ÎÎÎ
Input
Preamp
VCO
ÎÎÎÎÎÎ ÎÎ
φ
ÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎ
φ Det Lock Detect
Outputs
Lock Detect Lock Detect

Filter Comp
Figure 2. Functional Block Diagram of a Tone and FSK

Decoding System Using XR-2211
VCC
RB
Rl
Loop 11 RF 8
Phase 7
+
Detect C1 CF
FSK
Comp.
R1 10
2 12 Internal
Input VCO Reference
Signal 0.1mF
0.1mF
14 13 R0
C0 6
+ LDOQ
Quad
Phase LDOQN
Detect 5
3 Lock
Detect
Comp.
RD CD
Figure 3. Generalized Circuit Connection for

FSK and Tone Detection
Rev. 3.01
7
XR-2211
DESIGN EQUATIONS
(All resistance in W, all frequency in Hz and all capacitance in farads, unless otherwise specified)
(See Figure 3 for definition of components)
1. VCO Center Frequency, fO:
fO + 1
R 0·C 0
2. Internal Reference Voltage, VREF (measured at pin 10):
V REF + ǒV2 Ǔ–650mV in volts

CC
3. Loop Low-Pass Filter Time Constant, t:
+ C 1·R PP (seconds)
where:
R PP + ǒRR)·RR Ǔ
1
1 F
if RF is or CF reactance is , then RPP = R1

4. Loop Damping, j:
+ Ǹǒ 1250·C 0
R 1·C 1
Ǔ
Note: For derivation/explanation of this equation, please see TAN-011.
5. Loop-tracking
f
bandwidth, "+ f
0
f + R 0
f0 R1
Tracking
Bandwidth
Df Df
fLL f1 fO f2 fLH
Rev. 3.01
8
XR-2211
6. FSK Data filter time constant, tF:
RB · RF
tF + ·C (seconds)
( R B ) R F) F
7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 10 and pin11, per unit of
phase error at phase detector input):
Kd + ƪ
V REF · R 1 volt
10, 000·p radian
ƫ
8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin 11):
K0 + –2p
V REF ·C 0 · R 1
+ ǒradianvolt
ńsecond
Ǔ
9. The filter transfer function:
F(s) + 1 at 0 Hz. S = Jw and w = 0

1 ) SR 1·C 1
10. Total loop gain. KT:
K T + K O·K d·F(s) + ǒ5, 000·C R·(R ) R )Ǔƪseconds

0
F
1 F
1 ƫ
11. Peak detector current IA:
V REF
IA + (V REF in volts and I A in amps)
20, 000
Rev. 3.01
9
XR-2211
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 10, the functions
of external components are defined as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth,
and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a one-pole post-detection filter for
the FSK data output. The resistor RB from pin 7 to pin 8 introduces positive feedback across the FSK comparator to
facilitate rapid transition between output logic states.
Design Instructions:
The circuit of Figure 10 can be tailored for any FSK decoding application by the choice of five key circuit components: R0,
R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, fO and f1, these parameters can be calculated as
follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Calculate PLL center frequency, fO:
f O + ǸF 1·F 2
b) Choose value of timing resistor R0, to be in the range of 10KW to 100KW. This choice is arbitrary. The recommended
value is R0 = 20KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX.
RX
RO + RO )
2
c) Calculate value of C0 from design equation (1) or from Figure 7:
CO + 1
R0 · f0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R 0·f 0
R1 + ·2
(f 1–f 2)
e) Calculate C1 to set loop damping. (See design equation 4):

Normally, j = 0.5 is recommended.
1250·C 0
C1 +
R1 · 2
Rev. 3.01
10
XR-2211
f) The input to the XR-2211 may sometimes be too sensitive to noise conditions on the input line. Figure 4 illustrates
a method of de-sensitizing the XR-2211 from such noisy line conditions by the use of a resistor, Rx, connected
from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level.
V IN minimum (peak) + V a–V b + V " 2.8mV offset + V REF

20, 000
(20, 000 ) R X)
ǒ V
or R X + 20, 000 REF –1
V
Ǔ
VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold)
VCC
To Phase
Detector
ÎÎ
Input Va Vb
2
Rx 20K 20K
ÎÎ
ÎÎ
VREF 10
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, CF:
(R F ) R 1)·R B
R sum +
( R 1 ) R F ) R B)
CF + 0.25 Baud rate in 1

(R sum·Baud Rate) seconds
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
11
XR-2211
20 1.0
ÎÎÎÎÎÎÎÎÎÎÎ R0=5KW
Supply vs. Current (mA)
15
R0=10KW
R0=5KΩ
C0( mF)
10 0.1 R0=20KW
R0=10KΩ
ÎÎÎÎÎÎÎÎÎÎÎ R0=40KW
5
R0>100K R0=80KW
R0=160KW
0
0.01
4 6 8 10 12 14 16 18 20 22 24 100 1000 10000
fO(HZ)
Supply Voltage, V+ (Volts)
Figure 5. Typical Supply Current vs. V+ Figure 6. VCO Frequency vs. Timing Resistor
(Logic Outputs Open Circuited)
1,000
C0=0.001mF
1.02
fO = 1kHz 5
1
RF = 10R0
Normalized Frequency
1.01 5
C0=0.0033mF
4 2
3
R0(KW )
1.00
100 4
C0=0.01mF 3
0.99
C0=0.1mF
Curve R0
2 1 5K
0.98 2 10K
C0=0.0331mF 3 30K
1 4 100K
C0=0.33mF 0.97 5 300K
10 4 6 8 10 12 14 16 18 20 22 24
0 1000 10000
V+ (Volts)
fO(Hz)
Figure 7. VCO Frequency vs. Timing Capacitor Figure 8. Typical fO vs. Power Supply
Characteristics
Normalized Frequency Drift (% of f O)
+1.0
1MΩ
R0=10K
+0.5
500K
R0=50K
0
50K
R0=500K 10K
-0.5
V+ = 12V
R0=1MΩ R1 = 10 R0
fO = 1 kHz
-1.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 3.01
12
XR-2211
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.
Step 1: Calculate fO: from design instructions
(a) f O + Ǹ1200·2200 =1624
Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K. (See design instructions (b))
ǒ Ǔ
(b) R T + 10 ) 10 + 15K
2
Step 3: Calculate C0 from design instructions
(c) C O + 1 + 39nF
15000·1624
Step 4: Calculate R1 : from design instructions
(d) R 1 + 20000·1624·2 + 51, 000

(2200–1200)
Step 5: Calculate C1 : from design instructions
(e) C 1 + 1250·39nF2 + 3.9nF

51000·0.5
Step 6: Calculate RF : RF should be at least five times R1, RF = 51,000⋅5 = 255 KW

Step 7: Calculate RB : RB should be at least five times RF, RB = 255,000⋅5 = 1.2 MW
Step 8: Calculate RSUM :
(R F ) R 1)·R B
R SUM + + 240K
(R F ) R 1 ) R B )
Step 9: Calculate CF :
CF + 0.25 + 1nF
ǒ R SUM·Baud Rate Ǔ
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
13
XR-2211
VCC
RB
RL
1.8m 5% 5.1K
Loop 11 RF 178K 8 5%
Phase 7
Detect C1 5% CF Data
2.7nF 1nF 10% FSK Output
5% R1 Comp.
35.2K 10
2 12 1% Internal
Input VCO 0.1µF Reference
Signal R0
0.1µF
14 13 20K
1%
CO
27nF 5% VCO
Fine
Rx Tune
20K
6
+ LDOQ
Quad
Phase LDOQN
Detect 5
Lock
Detect
Comp.
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals
(Bell 202 Format)
VCC
RB
RL
Loop 11 RF 8 5.1k
Phase 7
+
Detect C1 CF
FSK
Comp.
R1 10
2 12 Internal
Input VCO Reference
Signal 0.1µF
0.1µF 14 13 R0
C0
Rx
6 LDOQ
Quad
Phase
Detect 3 5 LDOQN
Lock
Detect
RD Comp.
CD
Between 400K and 600K
Figure 11. External Connectors for FSK Demodulation with Carrier

Detect Capability
Rev. 3.01
14
XR-2211
VCC
Loop 11 8
Phase 7
+
Detect C1
220pF FSK
5% R1 Comp.
200K 10
2 12 1% Internal
VCO 0.1µF Reference
0.1µF R0
14 13 VCC
20K
Tone C0 5% 1%
Input 50nF
VCO
Rx Fine
5K Tune RL2 RL3
5.1K 5.1K
6 LDOQ
+
Quad Logic Output
Phase
Detect 3 5 LDOQN
Lock
Detect
CD Comp.
RD
470K 80nF
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect

The lock detect section of XR-2211 can be used as a frequency approaches the capture bandwidth.
carrier detect option for FSK decoding. The Excessively large values of CD will slow the response time
recommended circuit connection for this application is of the lock detect output. For Caller I.D. applications
shown in Figure 11. The open collector lock detect output, choose CD = 0.1mF.
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “low” state, until there is a carrier within
Tone Detection
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
Figure 12 shows the generalized circuit connection for
Note: Data Output is “Low” When No Carrier is Present.
tone detection. The logic outputs, LDOQN and LDOQ at
The minimum value of the lock detect filter capacitance pins 5 and 6 are normally at “high” and “low” logic states,
CD is inversely proportional to the capture range, +Dfc. respectively. When a tone is present within the detection
This is the range of incoming frequencies over which the band of the PLL, the logic state at these outputs become
loop can acquire lock and is always less than the tracking reversed for the duration of the input tone. Each logic
range. It is further limited by C1. For most applications, Dfc output can sink 5mA of load current.
> Df/2. For RD = 470KW, the approximate minimum value
of CD can be determined by: Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors RL2 and
RL3, as shown in Figure 12.
C D § 16 C in F and f in Hz.
f With reference to Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
C in mF and f in Hz. follows: R0 and C0 set VCO center frequency; R1 sets the
With values of CD that are too small, chatter can be detection bandwidth; C1 sets the low pass-loop filter time
observed on the lock detect output as an incoming signal constant and the loop damping factor.
Rev. 3.01
15
XR-2211
Design Instructions:
The circuit of Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components:
R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these parameters are calculated as follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 7 fS = fO:
CO + 1
R 0·fs
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R 0·f 0·2
R1 +
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C1 for a given loop damping factor:
1250·C 0
C1 +
R 1·j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D § 16 C in mF
Df
Increasing CD slows down the logic output response time.
Design Examples:
Tone detector with a detection band of + 100Hz:

a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20 KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 6 fS = fO:
C0 + 1 + 1 + 50nF
R 0·f S 20, 000·1, 000
Rev. 3.01
16
XR-2211
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R 0·f O·2 20, 000·1, 000·2

R1 + + + 400K
f 100
Note: The total detection bandwidth covers the frequency range of fO +f
d) Calculate value of C0 for a given loop damping factor:
1250·C 0
+ 1250·50·10 2 + 6.25pF
–9
C1 +
R 1· 2 400, 000·0.5
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D + 16 w 16 w 80nF
f 200
Increasing CD slows down the logic output response time.

f) Fine tune center frequency with 5KW potentiometer, RX.
VCC
VCC
RF
0.1µF
100K 4
Loop 11 8 3
7 + 1
Phase + CF 2
Detect C1 Demodulated
FSK 11 LM324 Output
Comp
.
R1 10
2 12 Internal
VCO 0.1µF Reference
FM 0.1µF 14 R0
13
Input
C0 6
+ LDOQ
Quad
Phase LDOQN
Detect 5
Lock
Detect
Comp.
Figure 13. Linear FM Detector Using XR-2211 and an External Op Amp.

(See Section on Design Equation for Component Values.)
Rev. 3.01
17
XR-2211
Linear FM Detection
XR-2211 can be used as a linear FM detector for a wide The FM detector gain, i.e., the output voltage change per
range of analog communications and telemetry unit of FM deviation can be given as:
applications. The recommended circuit connection for
this application is shown in Figure 13. The demodulated
R 1·V REF
output is taken from the loop phase detector output (pin V OUT
100·R 0
11), through a post-detection filter made up of RF and CF,
and an external buffer amplifier. This buffer amplifier is
necessary because of the high impedance output at pin where VR is the internal reference voltage (VREF = VCC /2
11. Normally, a non-inverting unity gain op amp can be - 650mV). For the choice of external components R1, R0,
used as a buffer amplifier, as shown in Figure 13. CD, C1 and CF, see the section on design equations.
V+
1 REF
20K Voltage
Output Input Lock
2 Detect
10
B Filter
From 3
10K 10K VCO 6
B’
Lock Detect
20K
Outputs
5
Internal Voltage Input Preamplifier Quadrature Lock Detect

Reference and Limiter Phase Detector Comparator
2K 2K
8
A Timing A’ 11
Capacitor A FSK
From Loop Comparator
13 C0 14 VCO Detector Input 7
B B’ A’ Output
FSK
Data
Output
12
R0 Timing 8K
4 Resistor
Ground
Voltage Controlled Loop Phase Detector FSK Comparator
Oscillator
Figure 14. Equivalent Schematic Diagram
Rev. 3.01
18
XR-2211
14 LEAD CERAMIC DUAL-IN-LINE

(300 MIL CDIP)
Rev. 1.00
14 8
1 7
D E1
Base A1
Plane A
Seating L
Plane
e c
B B1 α
INCHES MILLIMETERS
A 0.100 0.200 2.54 5.08

A1 0.015 0.060 0.38 1.52
B 0.014 0.026 0.36 0.66
B1 0.045 0.065 1.14 1.65
c 0.008 0.018 0.20 0.46
D 0.685 0.785 17.40 19.94
E1 0.250 0.310 6.35 7.87
E 0.300 BSC 7.62 BSC
e 0.100 BSC 2.54 BSC
L 0.125 0.200 3.18 5.08
α 0° 15° 0° 15°
Rev. 3.01
19
XR-2211
14 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP)
Rev. 1.00
14 8
E1
1 7
D E
A2
Seating A
Plane L C
A1 α
B
e B1 eA
eB
INCHES MILLIMETERS
A 0.145 0.210 3.68 5.33

A1 0.015 0.070 0.38 1.78
A2 0.115 0.195 2.92 4.95
B 0.014 0.024 0.36 0.56
B1 0.030 0.070 0.76 1.78
C 0.008 0.014 0.20 0.38
D 0.725 0.795 18.42 20.19
E 0.300 0.325 7.62 8.26
E1 0.240 0.280 6.10 7.11
e 0.100 BSC 2.54 BSC
eA 0.300 BSC 7.62 BSC
eB 0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
α 0° 15° 0° 15°
Rev. 3.01
20
XR-2211
14 LEAD SMALL OUTLINE

(150 MIL JEDEC SOIC)
Rev. 1.00
14 8
E H
1
7
C
A
Seating
Plane α
A1
e B
INCHES MILLIMETERS
A 0.053 0.069 1.35 1.75
A1 0.004 0.010 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.007 0.010 0.19 0.25
D 0.337 0.344 8.55 8.75
E 0.150 0.157 3.80 4.00
e 0.050 BSC 1.27 BSC
H 0.228 0.244 5.80 6.20
L 0.016 0.050 0.40 1.27
α 0° 8° 0° 8°
Note: The control dimension is the millimeter column
Rev. 3.01
21
XR-2211
Notes
Rev. 3.01
22
XR-2211
Notes
Rev. 3.01
23
XR-2211
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1995 EXAR Corporation

Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.01
24
L293D
L293DD
PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES
600mA OUTPUT CURRENT CAPABILITY

PER CHANNEL
1.2A PEAK OUTPUT CURRENT (non repeti-
tive) PER CHANNEL
ENABLE FACILITY
OVERTEMPERATURE PROTECTION
LOGICAL ”0” INPUT VOLTAGE UP TO 1.5 V
(HIGH NOISE IMMUNITY)
INTERNAL CLAMP DIODES SO(12+4+4) Powerdip (12+2+2)
ORDERING NUMBERS:
DESCRIPTION
The Device is a monolithic integrated high volt- L293DD L293D
age, high current four channel driver designed to
accept standard DTL or TTL logic levels and drive
inductive loads (such as relays solenoides, DC
and stepping motors) and switching power tran-
sistors.
To simplify use as two bridges each pair of chan-
nels is equipped with an enable input. A separate The L293D is assembled in a 16 lead plastic
supply input is provided for the logic, allowing op- packaage which has 4 center pins connected to-
eration at a lower voltage and internal clamp di- gether and used for heatsinking
odes are included. The L293DD is assembled in a 20 lead surface
This device is suitable for use in switching appli- mount which has 8 center pins connected to-
cations at frequencies up to 5 kHz. gether and used for heatsinking.
BLOCK DIAGRAM
June 1996 1/7

L293D - L293DD

Symbol Parameter Value Unit
VS Supply Voltage 36 V
V SS Logic Supply Voltage 36 V
Vi Input Voltage 7 V
V en Enable Voltage 7 V
Io Peak Output Current (100 µs non repetitive) 1.2 A
P tot Total Power Dissipation at Tpins = 90 °C 4 W
Tstg, Tj Storage and Junction Temperature – 40 to 150 °C
PIN CONNECTIONS (Top view)
SO(12+4+4) Powerdip(12+2+2)
THERMAL DATA
Symbol Decription DIP SO Unit
Rth j-pins Thermal Resistance Junction-pins max. – 14 °C/W
Rth j-amb Thermal Resistance junction-ambient max. 80 50 (*) °C/W
Rth j-case Thermal Resistance Junction-case max. 14 –
(*) With 6sq. cm on board heatsink.
2/7
L293D - L293DD
ELECTRICAL CHARACTERISTICS (for each channel, VS = 24 V, VSS = 5 V, Tamb = 25 °C, unless

otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VS Supply Voltage (pin 10) VSS 36 V
V SS Logic Supply Voltage (pin 20) 4.5 36 V
IS Total Quiescent Supply Current Vi = L ; IO = 0 ; Ven = H 2 6 mA
(pin 10) Vi = H ; IO = 0 ; Ven = H 16 24 mA
Ven = L 4 mA
ISS Total Quiescent Logic Supply Vi = L ; IO = 0 ; Ven = H 44 60 mA
Current (pin 20) Vi = H ; IO = 0 ; Ven = H 16 22 mA
Ven = L 16 24 mA
V IL Input Low Voltage (pin 2, 9, 12, – 0.3 1.5 V
19)
VIH Input High Voltage (pin 2, 9, VSS ≤ 7 V 2.3 VSS V
12, 19) VSS > 7 V 2.3 7 V
IIL Low Voltage Input Current (pin VIL = 1.5 V – 10 µA
2, 9, 12, 19)
IIH High Voltage Input Current (pin 2.3 V ≤ VIH ≤ VSS – 0.6 V 30 100 µA
2, 9, 12, 19)
Ven L Enable Low Voltage – 0.3 1.5 V
(pin 1, 11)
Ven H Enable High Voltage VSS ≤ 7 V 2.3 VSS V
(pin 1, 11) VSS > 7 V 2.3 7 V
Ien L Low Voltage Enable Current Ven L = 1.5 V – 30 – 100 µA
(pin 1, 11)
Ien H High Voltage Enable Current 2.3 V ≤ Ven H ≤ VSS – 0.6 V ± 10 µA
(pin 1, 11)
VCE(sat)H Source Output Saturation IO = – 0.6 A 1.4 1.8 V
Voltage (pins 3, 8, 13, 18)
VCE(sat)L Sink Output Saturation Voltage IO = + 0.6 A 1.2 1.8 V
(pins 3, 8, 13, 18)
VF Clamp Diode Forward Voltage IO = 600nA 1.3 V
tr Rise Time (*) 0.1 to 0.9 VO 250 ns
tf Fall Time (*) 0.9 to 0.1 VO 250 ns
ton Turn-on Delay (*) 0.5 Vi to 0.5 VO 750 ns
toff Turn-off Delay (*) 0.5 Vi to 0.5 VO 200 ns
(*) See fig. 1.
3/7
L293D - L293DD
TRUTH TABLE (one channel) Figure 1: Switching Times
Inpu t Enable (*) Output

H H H
L H L
H L Z
L L Z
Z = High output impedance

(*) Relative to the considered channel
Figure 2: Junction to ambient thermal resistance vs. area on board heatsink (SO12+4+4 package)
4/7
L293D - L293DD
POWERDIP16 PACKAGE MECHANICAL DATA
mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.85 1.40 0.033 0.055
b 0.50 0.020
b1 0.38 0.50 0.015 0.020
D 20.0 0.787
E 8.80 0.346
e 2.54 0.100
e3 17.78 0.700
F 7.10 0.280
I 5.10 0.201
L 3.30 0.130
Z 1.27 0.050
5/7
L293D - L293DD
SO20 PACKAGE MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45 1.772
D 1 12.6 0.039 0.496
E 10 10.65 0.394 0.419
e 1.27 0.050
e3 11.43 0.450
F 1 7.4 0.039 0.291
G 8.8 9.15 0.346 0.360
L 0.5 1.27 0.020 0.050
M 0.75 0.030
S 8° (max.)
6/7
L293D - L293DD
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
7/7
MAX232, MAX232I
DUAL EIA-232 DRIVERS/RECEIVERS
SLLS047I – FEBRUARY 1989 – REVISED OCTOBER 2002
D Meet or Exceed TIA/EIA-232-F and ITU MAX232 . . . D, DW, N, OR NS PACKAGE

Recommendation V.28 MAX232I . . . D, DW, OR N PACKAGE
(TOP VIEW)
D Operate With Single 5-V Power Supply
D Operate Up to 120 kbit/s C1+ 1 16 VCC
D Two Drivers and Two Receivers VS+ 2 15 GND
D ±30-V Input Levels

C1–
C2+
3
4
14
13
T1OUT
R1IN
D Low Supply Current . . . 8 mA Typical C2– 5 12 R1OUT
D Designed to be Interchangeable With VS– 6 11 T1IN
Maxim MAX232 T2OUT 7 10 T2IN
D ESD Protection Exceeds JESD 22 R2IN 8 9 R2OUT
– 2000-V Human-Body Model (A114-A)
D Applications
TIA/EIA-232-F
Battery-Powered Systems
Terminals
Modems
Computers
description/ordering information
The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply EIA-232 voltage
levels from a single 5-V supply. Each receiver converts EIA-232 inputs to 5-V TTL/CMOS levels. These
receivers have a typical threshold of 1.3 V and a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each
driver converts TTL/CMOS input levels into EIA-232 levels. The driver, receiver, and voltage-generator
functions are available as cells in the Texas Instruments LinASIC library.
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP (N) Tube MAX232N MAX232N
Tube MAX232D
SOIC (D) MAX232
Tape and reel MAX232DR
0°C to 70°C
Tube MAX232DW
SOIC (DW) MAX232
Tape and reel MAX232DWR
SOP (NS) Tape and reel MAX232NSR MAX232
PDIP (N) Tube MAX232IN MAX232IN
Tube MAX232ID
SOIC (D) MAX232I
–40°C to 85°C Tape and reel MAX232IDR
Tube MAX232IDW
SOIC (DW) MAX232I
Tape and reel MAX232IDWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinASIC is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MAX232, MAX232I
Function Tables
EACH DRIVER
INPUT OUTPUT
TIN TOUT
L H
H L
H = high level, L = low
level
EACH RECEIVER
INPUT OUTPUT
RIN ROUT
L H
H L
H = high level, L = low
level
logic diagram (positive logic)

11 14
T1IN T1OUT
10 7
T2IN T2OUT
12 13
R1OUT R1IN
9 8
R2OUT R2IN
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MAX232, MAX232I
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Positive output supply voltage range, VS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC – 0.3 V to 15 V
Negative output supply voltage range, VS– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –15 V
Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output voltage range, VO: T1OUT, T2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS– – 0.3 V to VS+ + 0.3 V
R1OUT, R2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Short-circuit duration: T1OUT, T2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage (T1IN,T2IN) 2 V
VIL Low-level input voltage (T1IN, T2IN) 0.8 V
R1IN, R2IN Receiver input voltage ±30 V
MAX232 0 70
TA Operating free
free-air
air temperature °C
MAX232I –40 85
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 3 and Figure 4)
PARAMETER TEST CONDITIONS MIN TYP‡ MAX UNIT
VCC = 5.5 V, All outputs open,
ICC Supply current 8 10 mA
TA = 25°C
‡ All typical values are at VCC = 5 V and TA = 25°C.
NOTE 3: Test conditions are C1–C4 = 1 µF at VCC = 5 V ± 0.5 V.

MAX232, MAX232I
DRIVER SECTION
temperature range (see Note 3)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VOH High-level output voltage T1OUT, T2OUT RL = 3 kΩ to GND 5 7 V
VOL Low-level output voltage‡ T1OUT, T2OUT RL = 3 kΩ to GND –7 –5 V
ro Output resistance T1OUT, T2OUT VS+ = VS– = 0, VO = ±2 V 300 Ω
IOS§ Short-circuit output current T1OUT, T2OUT VCC = 5.5 V, VO = 0 ±10 mA
IIS Short-circuit input current T1IN, T2IN VI = 0 200 µA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage
levels only.
§ Not more than one output should be shorted at a time.
switching characteristics, VCC = 5 V, TA = 25°C (see Note 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 3 kΩ to 7 kΩ,
SR Driver slew rate 30 V/µs
See Figure 2
SR(t) Driver transition region slew rate See Figure 3 3 V/µs
Data rate One TOUT switching 120 kbit/s
RECEIVER SECTION
temperature range (see Note 3)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VOH High-level output voltage R1OUT, R2OUT IOH = –1 mA 3.5 V
VOL Low-level output voltage‡ R1OUT, R2OUT IOL = 3.2 mA 0.4 V
Receiver positive-going input
VIT+ R1IN, R2IN VCC = 5 V, TA = 25°C 1.7 2.4 V
threshold voltage
Receiver negative-going input
VIT– R1IN, R2IN VCC = 5 V, TA = 25°C 0.8 1.2 V
threshold voltage
Vhys Input hysteresis voltage R1IN, R2IN VCC = 5 V 0.2 0.5 1 V
ri Receiver input resistance R1IN, R2IN VCC = 5, TA = 25°C 3 5 7 kΩ
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage
levels only.
switching characteristics, VCC = 5 V, TA = 25°C (see Note 3 and Figure 1)

PARAMETER TYP UNIT
tPLH(R) Receiver propagation delay time, low- to high-level output 500 ns
tPHL(R) Receiver propagation delay time, high- to low-level output 500 ns

MAX232, MAX232I
PARAMETER MEASUREMENT INFORMATION

VCC
R1OUT RL = 1.3 kΩ
R1IN
or
or
Pulse R2OUT See Note C
R2IN
Generator
(see Note A)
CL = 50 pF
(see Note B)
TEST CIRCUIT
≤10 ns ≤10 ns
3V
90% 90%
Input 50% 50%
10% 10%
0V
500 ns
tPLH
tPHL
VOH
Output 1.5 V 1.5 V
VOL
WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
Figure 1. Receiver Test Circuit and Waveforms for tPHL and tPLH Measurements

MAX232, MAX232I
PARAMETER MEASUREMENT INFORMATION

T1IN or T2IN T1OUT or T2OUT
Pulse
Generator EIA-232 Output
(see Note A)
CL = 10 pF
RL
(see Note B)
TEST CIRCUIT
≤10 ns ≤10 ns
3V
90% 90%
Input 50% 50%
10% 10%
0V
5 µs
tPLH
tPHL
90% VOH
90%
Output
10% 10%
VOL
tTHL tTLH
+
0.8 (V – V ) 0.8 (V – V )
OH OL OL OH
SR or
t t
TLH THL
WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
B. CL includes probe and jig capacitance.
Figure 2. Driver Test Circuit and Waveforms for tPHL and tPLH Measurements (5-µs Input)
Pulse
Generator EIA-232 Output
(see Note A)
3 kΩ CL = 2.5 nF
TEST CIRCUIT
≤10 ns ≤10 ns
Input
90% 90%
10% 1.5 V 1.5 V 10%
20 µs
tTLH
tTHL
VOH
3V 3V
Output
–3 V –3 V
VOL
SR +t 6 V
or t
THL TLH
WAVEFORMS
NOTE A: The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%.
Figure 3. Test Circuit and Waveforms for tTHL and tTLH Measurements (20-µs Input)

MAX232, MAX232I
APPLICATION INFORMATION
5V
+
CBYPASS = 1 µF
–
16
C3† 1 µF
VCC
1 2
C1+ 8.5 V
C1 1 µF 3 VS+
C1–
4 6
VS– –8.5 V
C2+
C2 1 µF 5 C4 1 µF
C2– +
11 14
EIA-232 Output
From CMOS or TTL
10 7
EIA-232 Output
12 13
EIA-232 Input
To CMOS or TTL
9 8
EIA-232 Input
0V
15
GND
† C3 can be connected to VCC or GND.
Figure 4. Typical Operating Circuit

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2002, Texas Instruments Incorporated

This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

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TELEMETRI KETINGGIAN AIR SEBAGAI PENGATUR

MODEL PINTU AIR BERBASIS

BRIATMA KURNIA PUTRA PRISTIWADI

PROGRAM STUDI TEKNIK ELEKTRO

PROGRAM STUDI TEKNIK ELEKTRO

ELECTRICAL ENGINEERING DEPARTMENT

tidak memuat karya atau bagian karya orang lain,

kecuali yang telah disebutkan dalam kutipan dan daftar pustaka,

sebagaimana layaknya karya ilmiah.”

Yogyakarta, 23 Juni 2007

Briatma Kurnia Putra Pristiwadi

Jenius adalah 1 % inspirasi dan 99 % keringat. Tidak ada yang

Yang terpenting dalam Olimpiade bukanlah kemenangan, tetapi

Baron Pierre De Coubertin

Kupersembahkan Karya ini :

Telemetri ketinggian air memberikan kemudahan dalam mengukur ketinggian

Kata kunci : ketinggian air, FSK, Visual Basic

Water level telemetry provides simple alternative to measure water level on

Key words : water level, FSK, Visual Basic

memberikan kasih karunia, anugerah, dan berkat-Nya, sehingga penulis dapat

menyelesaikan penulisan tugas akhir dengan baik.

Penulis menyadari bahwa dalam penulisan tugas akhir ini, penilis

hormat, penulis mengucapkan terima kasih yang sebesar-besarnya kepada:

1. Romo Ir. Greg. Heliarko SJ.,SS.,BST.,MA.,MSC Selaku Dekan Fakultas

Teknik Universitas Sanata Dharma Yogyakarta.

2. Bapak A. Bayu Primawan, S.T., M.Eng selaku Ketua Jurusan Teknik

Elektro Universitas Sanata Dharma Yogyakarta dan selaku pembimbing II

yang membimbing dan mengarahkan dalam penyusunan tugas akhir ini.

3. Bapak Martanto, S.T, M.T selaku pembimbing I atas segala pemikiran

dalam membimbing dan mengarahkan penulis dari awal hingga akhir.

4. Seluruh dosen di Fakultas Teknik Elektro yang tidak dapat di sebutkan

tentang Teknik Elektronika.

5. Seluruh Staf Perpustakaan Universitas Sanata Dharma yang sudah

memberikan layanan dan bantuan selama proses pencarian referensi.

penulis dapat menyelesaikan tugas akhir ini.

ke-Betean ku selama penyusunan tugas akhir ini.

8. Teman-teman teknik Elekro yang sudah membantu : Nango, Hugo, Antin,

Alex, BE”JO”lin (makasih buat pinjaman kabelnya), Ratna, Dwi, Wiryadi,

Eric “Decoy” (thank you buat laptop Vaionya).

9. Teman-teman di “ROSO KANGEN.EO” : Rinto, Gogon, Mbah Oko,

Kecer, Mendrik yang telah membantu dalam memotong aklirik dan

pinjaman pompa airnya.

10. Rekan-rekan di : NANDI Elektronik and Comp, QUANTUM Elektronik,

Mas Pri di SONY Group Elektronik, CHRISTAMAS Elektronik yang

telah memberikan saran-saran dan bantuan dalam penyusunan tugas akhir

ini. Bengkel bubut SUMBER WIDODO yang telah membuatkan gerigi,

dan mur baut model pintu air.

sobatku dari SMU hingga sekarang.

13. Marcopolo Team : Bule, Gepenk, Me2t, Plenthong, Koten, Lambezz,

Andex, Ahox yang selalu menjadi sumber inspirasiku dan sumber

senyumku. Jangan selamanya jadi “BATMAN”

selama mas Broto cuti.

senyum di waktu aku BT banget.

dalam satu pelayanan. Makasih atas dukungannya.

setia menemani perjalanan SOLO – YOGYA, yang rela kehujanan dan

kepanasan waktu cari komponen. Jangan cepet-cepet jadi barang

18. Kamar kecil 3 x 2.5 bertuliskan “RUANG TEKNIK”, di tempat ini

kutulis semua angan-angan dan harapan hidupku.

tidak dapat disebutkan satu persatu atas setiap bantuannya.

membangun sangat penulis harapkan.

penulis maupun pembaca semuanya.

Yogyakarta, 26 Juli 2007

HALAMAN JUDUL ...................................................................... i