BERBASIS
MIKROKONTROLER ATtiny2313
TUGAS AKHIR
Disusun oleh :
i
DIGITAL SWR METER AND POWER METER
BASED ON MICROCONTROLLER ATtiny2313
FINAL PROJECT
by:
ii
LEMBAR PENGESAHAN OLEH PEMBIMBING TUGAS AKHIR
disusun oleh
Fransiskus Xaverius Ari Bandioko
NIM : 025114019
Pembimbing I
Pembimbing II
iii
TUGAS AKHIR
iv
PERNYATAAN KEASLIAN KARYA
Dengan ini saya menyatakan bahwa dalam Tugas Akhir ini tidak terdapat karya
Tinggi, dan sepanjang sepengetahuan saya juga tidak terdapat karya atau pendapat
yang pernah ditulis atau diterbitkan oleh orang lain, kecuali yang secara tertulis
Penulis
v
vi
“ A pessimist sees a difficult in every
opportunity, but an optimist sees an
opportunity in every difficult”
(Sir Winston Churchill)
Dengan segala puji dan syukur ke hadirat Allah Bapa, Allah Putra, dan
Allah Roh Kudus, penulis persembahkan karya ini kepada:
• Ayah dan ibuku tercinta, kasih dan cinta kalian tak akan pernah
tergantikan oleh apapun
• Mbak Novin, Mas Iwan dan Nadine serta adikku Hendrikus Deka
Pranajaya, terima kasih telah menjadi sumber semangat hidupku.
vii
Intisari
viii
Abstract
ix
KATA PENGANTAR
Puji dan syukur penulis panjatkan kepada Tuhan Yang Maha Esa atas
ATTiny2313.”
Tugas akhir ini disusun sebagai salah satu syarat untuk memperoleh gelar
Pembuatan tugas akhir ini tidak terlepas dari bantuan dan bimbingan
berbagai pihak, untuk itu penulis ingin mengucapkan terima kasih kepada :
1. Ir. Gregorius Heliarko, S.J., S.S., BST., M.A., M.Sc selaku Dekan
4. Martanto, S.T., M.T selaku Ketua Tim Penguji yang telah memberikan
x
5. Ir. Th. Prima Ari Setyani, M.T selaku penguji yang juga telah memberikan
8. Ayah dan ibu tercinta: Bapak Ignatius Parmuji dan Ibu Lucia Sri
Damayanti.
9. Mbak Novin, mas Iwan dan Nadine, adikku Hendrikus Deka Pranajaya
10. Seseorang yang pernah mengisi dihatiku, neng Lava, mau menemani
dalam suka dan duka, terima kasih atas kebersamaan, dukungan, cinta,
kekompakannya.
14. Mas Gede, Mas Bowo, Mas Ucup, Robby, Andre Bhule, Andre PK, dan
Andre Krupuk, terima kasih atas bantuan dan semangat yang kalian
tularkan.
15. Keluarga besar Sidomulyo (Tutik, mas Bowo, de’ Eta, mbak Nia).
16. Semua pihak yang telah membantu dan tidak dapat disebutkan satu per
xi
Penulis dengan penuh kesadaran memahami dalam penelitian ini masih
tugas akhir ini dapat bermanfaat bagi pembaca khususnya dan dunia elektronika
umumnya.
Yogyakarta, 27 Nopember2007
Penulis
xii
DAFTAR ISI
Halaman ......................................................................................................................... i
Abstract ........................................................................................................................ ix
BAB I PENDAHULUAN............................................................................................ 1
xiii
1.5 Perumusan Masalah ............................................................................................... 3
2.1 Pengukuran.............................................................................................................. 7
xiv
2.5.1.1 DDRAM .......................................................................................... 28
2.6 LM 331.................................................................................................................. 31
3.2.1.2 Osilator............................................................................................. 39
xv
3.2.4 Hubungan V to F Converter dan Mikrokontroler Attiny2313 .................... 45
4.3.1 Pengukuran tegangan maju (Vfwd), tegangan balik (Vrev) dan data
4.3.3 Pengukuran Frekuensi Maju (Pf), Frekuensi Balik (Pr), Nilai SWR........... 59
4.4 Pembahasan........................................................................................................... 62
4.4.1 Analisa Data Pengukuran Frekuensi Maju, Frekuensi Balik dan SWR....... 62
4.4.3.2 Penampil Frekuensi Maju (Pf), Frekuensi Balik (Pr), dan SWR ..... 68
xvi
BAB V KESIMPULAN DAN SARAN ................................................................... 71
xvii
DAFTAR GAMBAR
Gambar 2.2 Blok Diagram SWR Meter dan Power Meter Digital ............................. 10
Gambar 2.5 Rangkaian SWR Meter dan Power Meter Analog .................................. 13
Gambar 3.1 Diagram Blok SWR Meter dan Power Meter Digital ............................. 36
xviii
Gambar 3.5 Rangkaian Analog Interface.................................................................... 41
xix
DAFTAR TABEL
Tabel 4.2 Data pengukuran tegangan maju,tegangan balik, dan perhitungan SWR.. 55
Tabel 4.5 Konversi Penyesuaian fout LM331 teoritis dengan fout AFG..................... 60
Tabel 4.6 Data pengukuran Frekuensi Maju (Pf) dan Frekuensi Balik (Pr) .............. 61
Tabel 4.7 Data pengukuran Frekuensi Maju (Pf) dan Frekuensi Balik (Pr) dengan
Tabel 4.8 Data pengukuran Frekuensi Maju (Pf) dan Frekuensi Balik (Pr) dengan
Tabel 4.9 Tingkat kesalahan dan deviasi SWR meter dan Power meter terkalibrasi
(analog interface)....................................................................................... 64
(analog interface)...................................................................................... 65
Tabel 4.11 Tingkat kesalahan dan deviasi SWR meter digital ................................... 66
xx
DAFTAR LAMPIRAN
ATTiny2313 Datasheet.
xxi
BAB I
PENDAHULUAN
I.1 Judul
AVR Attiny2313
dalam hal ini adalah radio yang menggunakan modulasi FM, sangatlah
penting. Hal ini dipengaruhi oleh seberapa besar daya pancar dan daya
pantul, yang keduanya hanya dapat diukur oleh Power Meter. Selain itu,
interferensi yang terjadi antara daya pancar dan daya pantul yang
1
2
kualitas instrumen yang digunakan, apakah baik atau buruk. Jenis SWR
Meter dan Power Meter yang sekarang ini masih terbatas pada jenis
analog. Tentunya cukup banyak kekurangan yang terdapat pada jenis ini,
diatas, maka penelitian ini berupaya membuat suatu instrumen yang dapat
lebih akurat.
pemasangan antena.
sebagai berikut:
serangkaian percobaan.
.
5
1. BAB I – Pendahuluan
batasan masalahnya.
4. Bab IV – Pembahasan
maksimal.
.
BAB II
DASAR TEORI
2.1 Pengukuran
Standar
berikut:
1. Presisi ( ketelitian )
7
8
2. Akurasi ( ketepatan )
tertentu.
3. Sensivitas ( kepekaan )
mempengaruhi keluaran.
5. Treshold
6. Linearitas.
meteran.
bentuk digital. Besaran digital dapat terdiri dari sejumlah pulsa diskrit dan
Gambar 2.2 Blok Diagram SWR Meter dan Power Meter digital
transmisi mempunyai parameter daya (P) yang terdiri dari tegangan (V)
dan arus (I) . Analog Interface adalah rangkaian SWR analog yang mampu
mendeteksi adanya daya pancar dan daya pantul. Setelah terjadi proses
pendeteksian tegangan pada daya pancar dan daya pantul, maka dapat
diinginkan.
11
sebagian dari energi pada gelombang datang akan dipantulkan pada beban.
sumber tidak sesuai dengan impedansi saluran, maka akan kembali timbul
didefinisikan sebagai :
VMAKS
VSWR = (2-1)
VMIN
Pf + Pr
SWR = (2-2)
Pf − Pr
Diketahui Pf = 9 watt ,
Pr = 3 watt ,
Pf + Pr 9 + 3 12
SWR = = = =2
Pf − Pr 9 -3 6
13
( Z L ). Fungsi dioda (D1 dan D2) adalah sebagai detektor tegangan yang
beban ( antena ).
Pada gambar 2.5, keluaran dari daya pancar dan daya pantul
transmisi yang sering digunakan adalah kabel coaxial, karena kabel jenis
adalah kabel elektrik yang terdiri dari jaringan konduksi yang diselimuti
lingkaran, dan pada bagian terluar ditutupi oleh lapisan insulator (jacket).
15
Keterangan gambar
A : plastic jacket
B : metallic shield
C : dielectric insulator
D : centre core
sebagai acuan (Dummy Load), yang harus bebas dari pengaruh frekuensi
dalam satu instruksi yaitu satu siklus clock. Hasil dari arsitektur ini lebih
17
efisien sepuluh kali dari mikrokontroler jenis CISC seperti AT89Cxxx atau
AT89Sxxx.
128 byte EEPROM, 128 byte SRAM, 18 saluran general purpose I/O line,
Standby.
terjadi interupsi atau sebuah instruksi call dijalankan, alamat asal program
18
bit.
nonvolatile.
(a) (b)
Gambar 2.7 (a) Peta Memory Progam ; (b) Peta Data Memory
19
6. RESET merupakan reset input, yang akan aktif apabila pin ini
1. Port B
masing pin dalam port ini juga memiliki fasilitas berupa resistor
pull-up eksternal.
yaitu :
2. Port D
adalah:
$11.
alternatif lain.
3. Port A
$1A($3A).
sebagai berikut :
t
RC
Vc = Vcc(1 e ) (2-3)
R = resistansi ( )
C = kapasitansi (Farad)
dan tes bit. Terdapat beberapa operasi “skip” yang dapat melewati (skip)
yaitu, LDS (Load Direct From Data Spac ) dan STS Store Direct to Data
Space).
dilakukan yaitu:
yang mengambil data pada alamat program memory yang ditunjuk register
tersebut maka yang harus dilakukan adalah mengatur setting bit pada
2.4.7.1 Timer/Counter
yang sama.
Sumber clock dipilih melalui clock select logic yang dikontrol oleh
(pin T1). Sumber clock dipilih melalui clock select logic yang
register TCCR1B.
30pF
XTAL1
30pF
XTAL2
GND
karakter huruf atau gambar. LCD tersusun dari 2 buah kaca dengan
( liquid crystal ).
Ketika tidak terdapat medan listrik di antara kedua elektroda, kristal cair
antara kedua elektroda, kristal cair akan membentuk pola yang seragam
dan tidak ada cahaya yang diputar, sehingga tidak ada cahaya yang
menembus kaca bagian depan. Dengan susunan dan bentuk pola elektroda
Setiap karakter dibentuk oleh 8x5 atau 10x5 pixel. Kapasitas RAM sebesar
diakses.
1 = mode pembacaan ;
0 = mode penulisan.
4,5Volt.
0Volt.
ditampilkan berada. Contoh, untuk karakter ‘A’ atau 41H yang ditulis pada
alamat 00h, maka karakter tersebut akan tampil pada baris pertama dan
kolom pertama dari LCD. Apabila karakter tersebut ditulis di alamat 40h,
maka karakter tersebut akan tampil pada baris kedua kolom pertama dari
2.13.
memori ini akan hilang saat power supply tidak aktif, sehingga pola
bersifat permanen, sehingga pola karakter tidak akan hilang meski power
2.5.1.4 Register
tempat status dari HD44780 dapat dibaca pada saat pembacaan data.
Enable clock lagi. Untuk mode 8 bit interface, proses penulisan dapat
langsung dilakukan 8 bit (bit 7 ... bit 0) dan diawali sebuah pulsa logika
1 pada E Clock.
untuk melihat status busy dari LCD atau membaca Address Counter. RS
diatur pada logika 0 untuk akses ke register perintah, R/W diatur pada
nibble rendah dibaca diawali pulsa logika 1 pada Enable Clock. Untuk
menuliskan atau membaca data ke atau dari DDRAM. Penulisan data pada
data yang akan ditampilkan pada LCD. Proses diawali dengan logika 1
31
pada logika 0 yang menunjukkan proses penulisan data. Data 4 bit nibble
tinggi (bit 7 hingga bit 4) dikirimkan diawali pulsa logika 1 pada sinyal
Enable Clock dan kemudian diikuti 4 bit nibble rendah (bit 3 hingga bit
kembali data yang tampil pada LCD. Proses dilakukan dengan mengatur
data. Data 4 bit nibble tinggi (bit 7 hingga bit 4) dibaca dengan diawali
adanya pulsa logika 1 pada E Clock dan dilanjutkan dengan data 4 bit
nibble rendah (bit 3 hingga bit 0) yang juga diawali dengan pulsa logika
1 pada E Clock.
2.6 LM 331
dari timer akan aktif (on) bersamaan dengan frekuensi keluaran dan
sumber arus untuk periode (T) tertentu. Besar nilai periode (T) dapat
T = 1.1 x Rt x C t (2-4)
resistansi R L .
VX VIN
IO = (2-6)
RL RL
Bila tegangan V IN lebih besar dua kali lipat, frekuensi juga akan lebih
4. Ground.
Untuk mencegah efek arus bias pada pin 6 dan juga untuk
menjaga besar gain yang dihasilkan sesuai dengan toleransi gain LM 131.
berikut :
V IN RS 1
f OUT = x x (2-7)
2.09v RL Rt .C t
R L = resistansi beban ( ),
Rt = resistansi pewaktuan ( ),
PERANCANGAN ALAT
Pada bab ini berisi tentang perancangan SWR Meter dan Power Meter
M1632 ukuran 16 x 2.
Attiny2313 adalah suatu alat pengembangan dari alat yang telah ada
ditampilkan pada tampilan LCD 16x2. Diagram blok dari sistem kerja alat
Gambar 3.1 Diagram blok SWR dan Power Meter Digital berbasis
mikrokontroler Attiny2313
36
37
Reset terjadi apabila pin reset mendapat logika 0 selama lebih dari
50ns. Pin reset dihubungkan dengan resistor (R1) yang terhubung ke VCC
tegangan maksimal yang harus diberikan pada pin ini Vc = 0,85 Vcc
persamaan (2-3)
t
RC
Vc = Vcc(1 - e )
t
RC
Vcc (1 - e ) = 0 ,85 Vcc ; t = 1ms
38
1 ms
RC
(1 - e ) = 0 , 85
1 ms
RC
-e = 0 ,85 - 1
1 ms
RC
-e = - 0 ,15
1 ms
= ln 0 ,15
RC
1ms = ln 0,15 × RC
1ms
RC =
ln 0,15
3
RC = 0,5271 × 10
3
RC = 0,5271 × 10
3
10k × C = 0,5271 × 10
3
0,5271× 10
C=
10k
9
C = 52,7114 × 10
39
3.2.1.2 Osilator
suatu instruksi.
clock input dengan dua kapasitor C2 dan C3 sebesar 22pF (datasheet AVR
AVR ATtiny2313.
40
Power Meter , yang mempunyai dua buah point pengukuran yaitu forward
besar daya pancar dan daya pantul yang berada di saluran transmisi.
Sesuai dengan fungsi detektor tegangan, maka dioda (D1 dan D2)
converter.
41
yang impedansinya diketahui secara pasti sebagai acuan dan beban yang
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
1 1 1
= + ........ +
R total R1 R 20
42
1 1 1
= + ........ +
R total 1k 1k
1 20
=
R total 1k
1k
R total =
20
R total = 50
dimaksudkan untuk memberi hasil yang lebih baik. Penentuan besar nilai-
43
100k , sehingga arus bias pada pin 7 sebesar -80 nA (datasheet LM331)
akan mencegah efek arus bias pada pin 6, dan juga membantu memberikan
fungsi filter yang baik, kapasitor yang digunakan sebesar 1uF. Dengan
nilai kapasitor itu, maka apabila waktu konstan pada RC bersesuaian, step
menjaga besar gain yang dihasilkan sesuai dengan toleransi gain LM 331.
VIN RS 1
f OUT = x x
2.09 v R L R t .C t
V IN = 10 V (full scale),
1.9V
RS = ; i = 135 uA (typical datasheet LM331),
i
1.9V
RS = = 14074.074 14k .
135uA
Maka :
VIN RS 1
f OUT = x x
2.09 v R L R t .C t
10V 14k 1
f OUT = x x
2.09V 100k (6.8k )(0.01uF )
tegangan VIN :
U2
U1A U1B 2 12
1 2 3 4 3 PD0/RXD PB0/AIN0 13
6 PD1/TXD PB1/AIN1 14
74LS14 74LS14 RS PD2/INTO PB2
7 15
E PD3/INT1 PB3/OC1
8 16
9 PD4/TO PB4 17
VCC 11 PD5/T1 PB5/MOSI 18
C2 = 22PF1 PD6/ICP PB6/MISO 19
R1 CRY STAL 5 PB7/SC K
U3
1 8 4 XTAL1
R2 I Out VCC 6K8 J1 Y1 1 XTAL2
3
2 7 C3 = 22PF1 RESET
R3 I Ref COMP Out 1 20
12K 3 6 2 VCC
2 5K f Out THRES
4 5 C1 Vin FWD VCC ATTiny 2313
GN D R/C 0,1 VCC
LM131 R4
10K
1
VCC C2
R5 0,01
3
C3
R6 1u 100K SW1 C4
1M R7 10u
SW PUSHBUTTON DB0
2
U1C U1D DB1
DB2
22K R8 5 6 9 8
DB3
47
74LS14 74LS14 DB4
1
DB5
DB6
DB7
VCC
J3
R9 Vin REV
U4
1 8
R10 I Out VC C
1
2
3
2 7 6K8
R11 I Ref COMP Out
12K 3 6
2 5K f Out THRES
4 5 C5
GND R/C 0,1
LM131
1
VCC R12
3
C7 C6
R13 R14 1u 10K 0,01
1M
2
22K R15
47
1
kaki PB.5 terhubung dengan R/S. LCD hanya difungsikan dalam kondisi
tulis, jadi pada LCD kaki R/W selalu dalam kondisi low (dihubungkan
dengan ground).
mode pengiriman data bus, pengaturan jumlah baris dan jumlah dot-matrix
setiap karakternya.
47
VCC
U5
LCD
3
2
1
VCC
VEE
vcc
GND
4
RS RS
U2 5
6 R/W
E E
2 12 7
PD0/RXD PB0/AIN0 DB0 DB0 DB0
LCD 16 X 2
3 13 8
PD1/TXD PB1/AIN1 DB1 DB1 DB1
6 14 9
RS PD2/INTO PB2 DB2 DB2 DB2
7 15 10
E PD3/INT1 PB3/OC1 DB3 DB3 DB3
8 16 11
FWD PD4/TO PB4 DB4 DB4 DB4
9 17 12
REV PD5/T1 PB5/MOSI DB5 DB5 DB5
11 18 13
PD6/ICP PB6/MISO DB6 DB6 DB6
C2 = 22PF1 19 14
PB7/SCK DB7 DB7 DB7
5
4 XTAL1
Y1 1 XTAL2
C3 = 22PF1 4Mhz RESET
20
VCC
R4
10K
SW1 C4
10u
RESET
2 7 C3 = 22PF1
R3 I Ref COMP Out 1 20
12K 3 6 2 VCC
2 5K f Out THRES VCC
4 5 C1 Vin FWD VCC ATTiny2313
GND R/C 0,1 VCC
LM131 R4
10K
1
U5
VCC C2 LCD
3
2
R5 0,01 1
3
C3
VE E
vcc
GND
R6 1u 100K SW1 C4 4
R7 10u RS RS
1M 5
2 SW PUSHBUTTON 6 R/W
U1C U1D E E
7
DB0 DB0
LC D 16 X 2
22K R8 5 6 9 8 8
DB1 DB1
47 9
74LS14 74LS14 DB2 DB2
10
1
DB3 DB3
VCC 11
DB4 DB4
12
DB5 DB5
13
J2 DB6 DB6
14
DB7 DB7
VCC
1
J3 2
R9 Vin REV
U4
1 8 VCC 5V
R10 I Out VCC
1
2
3
2 7 6K8
R11 I Ref COMP Out
12K 3 6
2 5K f Out THRES
4 5 C5
GND R/C 0,1
LM131
1
VCC C6
R12 0,01
3
C7
R13 1u 10K
1M R14
2
22K R15
47
1
LM 331, proses pengolahan data dan penghitungan nilai SWR, dan proses
overflow akan aktif. Pada saat interupsi ini dilakukan pembacaan jumlah
counter pulsa dari INT0 (untuk forward) dan INT1 (untuk reverse).
mengetahui bit apa yang akan dipakai, dimana ada terdapat dua pilihan 8
bit atau 4 bit. Kemudian cursor dinyalakan atau tidak, serta bentuk tulisan
yang akan digunakan, dimana terdapat dua pilihan juga 8x10 dot atau 8x7
LCD.
51
Pada bab ini berisi tentang hasil perancangan SWR Meter dan Power Meter
Untuk mendapatkan pengukuran yang baik, alat ukur harus dikalibrasi terlebih
dahulu. Metode untuk kalibrasi alat ukur dilakukan dengan membandingkan dengan
alat ukur acuan yaitu SWR dan Power Meter Analog SX-200 Diamond Antena.
(Pemancar), SWR dan Power Meter analog SX-200 Diamond Antena dan
antena (dummy load) pada konektor yang sesuai (TX ke pesawat, ANT ke
antena).
52
53
2. Letakkan VU Meter pada masing-masing titik maju (FWD) dan titik balik
maksimum, dan jarum pada titik balik (REV) menunjuk ke suatu angka.
3. Balik posisi SWR meter. TX (pemancar) ke antena (dummy load) dan pesawat
ke ANT, lalu ulangi langkah 2 sampai jarum harus menunjuk angka yang
sama.
kalibrasi yang menjadi data acuan proses pengujian dan pengukuran alat ukur.
54
10 Watt, maka besar nilai SWR untuk perubahan kenaikan daya pancar
keluaran dari 1 Watt sampai 10 Watt pada SWR dan Power Meter analog SX-
200 Diamond Antena dapat langsung dilihat dengan mengatur posisi saklar
pada fungsi pengukuran SWR. Data untuk kalibrasi seperti pada tabel 4.1
dibawah :
Daya Pemancar
SWR
(Watt)
10 1,10
9 1,10
8 1,10
7 1,10
6 1,09
5 1,09
4 1,08
3 1,06
2 1,05
1 1,05
frekuensi keluaran LM331, data frekuensi maju (Pf) dan frekuensi balik (Pr)
4.3.1 Pengukuran tegangan maju (Vfwd), tegangan balik (Vrev) dan data
perhitungan SWR
Tabel 4.2 Data pengukuran tegangan maju (Vfwd), tegangan balik (Vrev)
dan data perhitungan SWR
Daya Vfwd Vrev SWR
Pemancar (v) (v)
(Watt)
10 0,375 0,016 1,09
9 0,35 0,015 1,09
8 0,325 0,014 1,09
7 0,3 0,012 1,08
6 0,275 0,011 1,08
5 0,25 0,01 1,08
4 0,225 0,009 1,08
3 0,2 0,007 1,07
2 0,15 0,005 1,07
1 0,1 0,002 1,04
Data hasil SWR pada tabel 4.2 didapat dengan melakukan perhitungan
Vf wd + Vrev
SWR =
Vfwd - Vrev
Perhitungan data SWR sesuai dengan data pengukuran Vfwd dan Vrev yang
sebagai berikut :
0,375 + 0,016
SWR = = 1,09
0,375 - 0,016
56
0,35 + 0,015
SWR = = 1,09
0,35 - 0,015
0,325 + 0,014
SWR = = 1,09
0,325 - 0,014
0,3 + 0,012
SWR = = 1,08
0,3 - 0,012
0,275 + 0,011
SWR = = 1,08
0,275 - 0,011
0,25 + 0,01
SWR = = 1,08
0,25 - 0,01
0,225 + 0,009
SWR = = 1,08
0,225 - 0,009
0,2 + 0,007
SWR = = 1,07
0,2 - 0,007
57
0,15 + 0,005
SWR = = 1,07
0,15 - 0,005
0,1 + 0,002
SWR = = 1,04
0,1 - 0,002
LM331 dengan input tegangan sesuai data tabel 4.2 melalui frequency counter
V IN R 1
f OUT = x S x
2 . 09 v R L R t .C t
4.3.3 Pengukuran Frekuensi Maju (Pf), Frekuensi Balik (Pr), Nilai SWR
dan pin 7). Hal ini dilakukan karena frekuensi keluaran dari LM331 yang
scale factor adalah sebesar 1 kHz V yang artinya setiap perubahan kenaikan 1
Tabel 4.5 Konversi penyesuaian f OUT LM331 teoritis dengan f OUT AFG
TeganganMaju
0,3 295,5249 290 AFG1
0,275 270,8978 270
0,25 246,2708 240 FWD
0,225 221,6437 220
0,2 197,0166 190
0,15 147,7625 140
0,1 98,5803 95
VIN (V) f OUT LM331(Hz) f OUT AFG (Hz
0,016 15,7613 15
0,015 14,7762 14
0,014 13,7911 13
Tegangan Balik
Pada tabel 4.6 data pengukuran frekuensi maju (Pf) dan frekuensi
balik (Pr) dengan input AFG1 FWD adalah frekuensi konversi penyesuaian
sesuai input tegangan maju (Vfwd) dan AFG2 REV adalah frekuensi konversi
keluaran AFG sesuai input tegangan balik (Vrev). Pada tabel 4.7 dan 4.8
terlihat data pengukuran frekuensi maju (Pf) dan frekuensi balik (Pr) dengan
Tabel 4.6 Data pengukuran Frekuensi Maju (Pf) dan Frekuensi Balik (Pr)
AFG 1 FWD AFG 2 REV Pf Pr SWR
(Hz) (Hz) (LCD) (LCD) (LCD)
370 15 38,6 01,6 1,08
340 14 35,4 01,4 1,08
320 13 33,2 01,3 1,08
290 11 30,1 01,2 1,08
270 10 27,9 01,1 1,08
240 9 24,8 00,9 1,07
220 8 22,6 00,8 1,07
190 7 19,5 00,7 1,07
140 5 14,3 00,4 1,05
95 2 09,6 00,2 1,04
Tabel 4.7 Data pengukuran Frekuensi Maju (Pf) dan Frekuensi Balik (Pr)
dengan input AFG1 FWD bervariasi dan AFG2 REV konstan
AFG 1 FWD AFG 2 REV Pf Pr SWR
(Hz) (Hz) (LCD) (LCD) (LCD)
370 95 38,6 09,6 1,66
340 95 35,4 09,6 1,74
320 95 33,2 09,6 1,82
290 95 30,1 09,6 1,94
270 95 27,9 09,6 2,05
240 95 24,8 09,6 2,26
220 95 22,6 09,6 2,48
190 95 19,5 09,6 2,94
140 95 14,3 09,6 5,08
95 95 09,6 09,6
Tabel 4.8 Data pengukuran Frekuensi Maju (Pf) dan Frekuensi Balik (Pr)
dengan input AFG1 FWD dan Input AFG2 REV bervariasi
AFG 1 FWD AFG 2 REV Pf Pr SWR
(Hz) (Hz) (LCD) (LCD) (LCD)
370 2 38,6 00,2 1,01
340 5 35,4 00,4 1,02
320 7 33,2 00,7 1,04
290 8 30,1 00,8 1,05
270 9 27,9 00,9 1,06
240 10 24,8 01,1 1,09
220 11 22,6 01,2 1,11
190 13 19,5 01,3 1,14
140 14 14,3 01,4 1,22
95 15 09,6 01,6 1,40
62
4.4 Pembahasan
4.4.1 Analisa Data Pengukuran Frekuensi Maju, Frekuensi Balik, dan SWR
balik, dan nilai SWR dilakukan untuk memperlihatkan bahwa program untuk
Pf + Pr
SWR =
Pf − Pr
sebagai berikut :
38,6 + 1,6
Nilai SWR teoritis = = 1,08
38,6 − 1,6
9,6 + 0,2
Nilai SWR teoritis = = 1,04
9,6 − 0,2
38,6 + 9,6
Nilai SWR teoritis = = 1,66
38,6 − 9,6
27,9 + 9,6
Nilai SWR teoritis = = 2,05
27,9 − 9,6
9,6 + 9,6
Nilai SWR teoritis = =∞
9,6 − 9,6
Dari hasil contoh analisa diatas, nilai SWR yang ditampilkan oleh
penampil (LCD) adalah sesuai dengan perhitungan nilai SWR secara teoritis.
Apabila frekuensi maju sangat besar dibandingkan frekuensi balik, maka nilai
SWR yang terukur pada penampil adalah nilai SWR yang kecil. Sedangkan,
frekuensi maju, maka nilai SWR yang terukur pada penampil adalah nilai
SWR dan besar daya pancar (FWD Power) pada alat ukur acuan dengan data
pengujian ini ditentukan besar perubahan kenaikan daya pancar pemancar dari
Sebagai data acuan digunakan data kalibrasi SWR dan Power meter
Error (E) adalah selisih antara nilai hasil pengukuran dengan alat ukur
dibandingkan dengan data acuan. Analisa statistik yang lain untuk melihat
data pengukuran alat ukur terkalibrasi (analog interface) dengan data acuan.
kenaikan daya pancar untuk pengukuran nilai SWR alat ukur terkalibrasi
(analog interface).
Tabel 4.9 Tingkat kesalahan dan deviasi SWR Meter dan Power Meter
terkalibrasi (analog interface)
Data SWR
Daya
Data SWR analog x-y
Pancar E = × 100 Deviasi
Acuan interface x
Pemancar pengukuran
(x) (y)
(Watt)
10 1,10 1,09 1% 0,01
9 1,10 1,09 1% 0,01
8 1,10 1,09 1% 0,01
7 1,10 1,08 2% 0,02
6 1,09 1,08 1% 0,01
5 1,09 1,08 1% 0,01
4 1,08 1,08 0% 0
3 1,06 1,07 1% 0,01
2 1,05 1,07 2% 0,02
1 1,05 1,04 1% 0,01
65
dengan tingkat ketelitiannya. Untuk tingkat ketelitian alat ukur yang dibuat
pengukuran pada tabel 4.6 dengan data pengukuran pada tabel 4.2 seperti
Tabel 4.11 Tingkat kesalahan dan deviasi data SWR Meter digital
x y
Data SWR Data SWR E = × 100 % Deviasi
x
tabel 4.2 (x) tabel 4.8 (y) pengukuran
1,09 1,08 0,92% 0,01
1,09 1,08 0,92% 0,01
1,09 1,08 0,92% 0,01
1,08 1,08 0% 0
1,08 1,08 0% 0
1,08 1,07 0,92% 0,01
1,08 1,07 0,92% 0,01
1,07 1,07 0% 0
1,07 1,05 1,87% 0,02
1,04 1,04 0% 0
sebesar :
Spesifikasi alat :
pengukuran besar SWR dan Power antara daya keluaran pemancar 1 Watt –
maju (forward) berkisar antara 0,1 volt – 0,375 volt dan level tegangan balik
pengukuran dengan data kalibrasi SWR dan Power Meter SX-200 Diamond
data SWR dan Power meter digital harus dilakukan dengan menggunakan
alat bantu yaitu AFG sebagai pembangkit frekuensi yang linier sesuai data
pengukuran tegangan pada titik maju (forward) dan titik balik (reverse),
data pengukuran besar SWR dengan alat bantu hitung atau menempatkan
switch untuk pengukuran SWR (pada SWR dan Power Meter Analog SX-
pemancar.
4.2.2.2 Penampil Frekuensi Maju (Pf), Frekuensi Balik (Pr), dan SWR
AFG adalah gelombang pulsa. Penyesuaian nilai frekuensi keluaran dari AFG
menjadi frekuensi keluaran dari AFG dapat dilihat pada tabel 4.5.
panel range frekuensi. Sesuai dengan definisi bahwa frekuensi adalah jumlah
Unit operasi penampil frekuensi maju (Pf) dan frekuensi balik (Pr)
terdiri dari mikrokontroler, LCD , dan tombol reset. Tombol reset digunakan
untuk me-reset nilai frekuensi maju (Pf), frekuensi balik (Pr), dan nilai SWR.
BAB V
pada bab ini akan diambil beberapa kesimpulan dan saran yang berguna untuk
5.1 Kesimpulan
Dari hasil pengujian dan analisis data dapat diambil kesimpulan sebagai
berikut:
Level tegangan maju adalah 0,1 volt – 0,375 volt dan level tegangan balik
dan balik dapat bekerja dengan baik, begitu pula dengan program
71
72
4. Terdapat tingkat kesalahan dan deviasi pada data pengukuran SWR yang
dibandingkan dengan data kalibrasi alat ukur acuan (SWR dan Power
dan Power meter terkalibrasi (analog interface) dan SWR dan Power
1) Analog Interface
5.2 Saran
sebagai berikut.
1. Pengukuran besar nilai SWR dan Power dapat dikembangkan pada frekuensi
yang lebih tinggi yaitu VHF (Very High Frequency) misal pada range
pemancar dan daya balik bagi instansi radio pemancar FM agar selalu dalam
73
(antena).
DAFTAR PUSTAKA
74
75
http://pdf.alldatasheet.net
LAMPIRAN
Lampiran
U2
U1A U1B 2 12
PD0/RXD PB0/AIN0 DB0
1 2 3 4 3 13
PD1/TXD PB1/AIN1 DB1
6 14
74LS14 74LS14 RS PD2/INTO PB2 DB2
7 15
E PD3/INT1 PB3/OC1 DB3
8 16
PD4/TO PB4 DB4
9 17
PD5/T1 PB5/MOSI DB5
VCC 11 18
PD6/ICP PB6/MISO DB6
C2 = 22PF1 19
R1 PB7/SCK DB7
U3 CRYSTAL 5
1 8 4 XTAL1
R2 I Out VCC 6K8 J1 Y1 1 XTAL2
RESET
3
2 7 C3 = 22PF1
R3 I Ref COMP Out 1 20
12K 3 6 2 VCC
2 5K f Out THRES VCC
4 5 C1 Vin FWD VCC ATTiny 2313
GND R/C 0,1 VCC
LM131 R4
10K
1
U5
VCC C2 LCD
3
2
1
R5 0,01
3
C3
VEE
vcc
GND
R6 1u 100K SW1 C4 4
R7 10u RS RS
1M 5
2 SW PUSHBUTTON 6 R/W
U1C U1D E E
7
DB0 DB0
LCD 16 X 2
22K R8 5 6 9 8 8
DB1 DB1
47 9
74LS14 74LS14 DB2 DB2
10
1 DB3 DB3
VCC 11
DB4 DB4
12
DB5 DB5
13
J2 DB6 DB6
14
DB7 DB7
VCC
1
J3 2
R9 Vin REV
U4
1 8 VCC 5V
R10 I Out VCC
1
2
3
2 7 6K8
R11 I Ref COMP Out
12K 3 6
2 5K f Out THRES
4 5 C5
GND R/C 0,1
LM131
1
VCC C6
R12 0,01
3
C7
R13 1u 10K
1M R14
2
22K R15
47
1
Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
• Data and Non-volatile Program and Data Memories
– 2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
– 128 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
8-bit
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
Microcontroller
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode with 2K Bytes
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels In-System
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator Programmable
– USI – Universal Serial Interface
•
– Full Duplex USART
Special Microcontroller Features
Flash
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
ATtiny2313/V
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages Preliminary
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF Summary
• Operating Voltages
– 1.8 - 5.5V (ATtiny2313V)
– 2.7 - 5.5V (ATtiny2313)
• Speed Grades
– ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Typical Power Consumption
– Active Mode
1 MHz, 1.8V: 230 µA
32 kHz, 1.8V: 20 µA (including oscillator)
– Power-down Mode
< 0.1 µA at 1.8V
Rev. 2543IS–AVR–04/06
Pin Configurations Figure 1. Pinout ATtiny2313
PDIP/SOIC
MLF
PB7 (UCSK/SCK/PCINT7)
PB6 (MISO/DO/PCINT6)
PA2 (RESET/dW)
PD0 (RXD)
VCC
20
19
18
17
16
(TXD) PD1 1 15 PB5 (MOSI/DI/SDA/PCINT5)
XTAL2) PA1 2 14 PB4 (OC1B/PCINT4)
(XTAL1) PA0 3 13 PB3 (OC1A/PCINT3)
(CKOUT/XCK/INT0) PD2 4 12 PB2 (OC0A/PCINT2)
(INT1) PD3 5 11 PB1 (AIN1/PCINT1)
10
6
7
8
9
(T0) PD4
(OC0B/T1) PD5
GND
(ICP) PD6
(AIN0/PCINT0) PB0
Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2 ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Block Diagram
XTAL1 XTAL2
PA0 - PA2
PORTA DRIVERS
MCU CONTROL
PROGRAM REGISTER
SRAM
FLASH
MCU STATUS ON-CHIP
REGISTER DEBUGGER
INSTRUCTION GENERAL
REGISTER PURPOSE TIMER/
REGISTER COUNTERS
INSTRUCTION INTERRUPT
DECODER UNIT
EEPROM
CONTROL ALU
LINES
USI
STATUS
REGISTER
PROGRAMMING
SPI USART
LOGIC
COMPARATOR
3
2543IS–AVR–04/06
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATtiny2313 provides the following features: 2K bytes of In-System Programmable
Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general
purpose working registers, a single-wire Interface for On-chip Debugging, two flexible
Timer/Counters with compare modes, internal and external interrupts, a serial program-
mable USART, Universal Serial Interface with Start Condition Detector, a programmable
Watchdog Timer with internal Oscillator, and three software selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and
interrupt system to continue functioning. The Power-down mode saves the register con-
tents but freezes the Oscillator, disabling all other chip functions until the next interrupt
or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, or by a conventional non-volatile memory programmer.
By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono-
lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATtiny2313 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-
cuit Emulators, and Evaluation kits.
4 ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Pin Descriptions
GND Ground.
Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313 as listed
on page 53.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313 as listed
on page 53.
Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313 as listed
on page 56.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Input
is an alternate function for PA2 and dW.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL1 is an alternate function for PA0.
XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.
Resources A comprehensive set of development tools, application notes and datasheets are avail-
able for downloadon http://www.atmel.com/avr.
5
2543IS–AVR–04/06
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F (0x5F) SREG I T H S V N Z C 7
0x3E (0x5E) Reserved – – – – – – – –
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 10
0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 78
0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – – 60
0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – – 62
0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 79, 110
0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 79
0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN 156
0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 78
0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 53
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 37
0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 77
0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 78
0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 25
0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 74
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1BO – – WGM11 WGM10 105
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 108
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 109
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 109
0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 109
0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 109
0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 110
0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 110
0x27 (0x47) Reserved – – – – – – – –
0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 27
0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 110
0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 110
0x23 (0x43) GTCCR – – – – – – – PSR10 82
0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 109
0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 42
0x20 (0x40) PCMSK PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 62
0x1F (0x3F) Reserved – – – – – – – –
0x1E (0x3E) EEAR – EEPROM Address Register 15
0x1D (0x3D) EEDR EEPROM Data Register 16
0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 16
0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 58
0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 58
0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 58
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 58
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 58
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 58
0x15 (0x35) GPIOR2 General Purpose I/O Register 2 20
0x14 (0x34) GPIOR1 General Purpose I/O Register 1 20
0x13 (0x33) GPIOR0 General Purpose I/O Register 0 20
0x12 (0x32) PORTD – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 58
0x11 (0x31) DDRD – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 58
0x10 (0x30) PIND – PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 58
0x0F (0x2F) USIDR USI Data Register 145
0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 146
0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 147
0x0C (0x2C) UDR UART Data Register (8-bit) 130
0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 130
0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 132
0x09 (0x29) UBRRL UBRRH[7:0] 134
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 150
0x07 (0x27) Reserved – – – – – – – –
0x06 (0x26) Reserved – – – – – – – –
0x05 (0x25) Reserved – – – – – – – –
0x04 (0x24) Reserved – – – – – – – –
0x03 (0x23) UCSRC – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 133
0x02 (0x22) UBRRH – – – – UBRRH[11:8] 134
0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 151
0x00 (0x20) Reserved – – – – – – – –
6 ATtiny2313/V
2543IS–AVR–04/06
ATtiny2313/V
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
7
2543IS–AVR–04/06
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
8 ATtiny2313/V
2543IS–AVR–04/06
LM131A/LM131, LM231A/LM231, LM331A/LM331 Precision Voltage-to-Frequency Converters
December 1994
Typical Applications
VIN R 1 TL/H/5680 – 1
fOUT e # S#
2.09 V RL RtCt
*Use stable components with low temperature coefficients. See Typical Applications section.
**0.1mF or 1mF, See ‘‘Principles of Operation.’’
2
Electrical Characteristics TA e 25§ C unless otherwise specified (Note 2) (Continued)
Parameter Conditions Min Typ Max Units
TIMER
Timer Threshold Voltage, Pin 5 0.63 0.667 0.70 c VS
3
Functional Block Diagram
TL/H/5680 – 2
Pin numbers apply to 8-pin packages only. See connection diagram for LM231WM pin numbers.
FIGURE 1a
TeflonÉ registered trademark of DuPont
4
Typical Performance Characteristics
(All electrical characteristics apply for the circuit of Figure 3 , unless otherwise noted.)
Nonlinearity Error, LM131
Family, as Precision V-to-F Nonlinearity Error, LM131 Nonlinearity vs Power Supply
Converter (Figure 3 ) Family Voltage
100 kHz Nonlinearity Error, Nonlinearity Error, LM131 Input Current (Pins 6, 7) vs
LM131 Family (Figure 4 ) (Figure 1 ) Temperature
TL/H/5680 – 3
5
Typical Applications (Continued)
PRINCIPLES OF OPERATION OF A SIMPLIFIED DETAIL OF OPERATION, FUNCTIONAL BLOCK
VOLTAGE-TO-FREQUENCY CONVERTER DIAGRAM (FIGURE 1a )
The LM131 is a monolithic circuit designed for accuracy and The block diagram shows a band gap reference which pro-
versatile operation when applied as a voltage-to-frequency vides a stable 1.9 VDC output. This 1.9 VDC is well regulated
(V-to-F) converter or as a frequency-to-voltage (F-to-V) con- over a VS range of 3.9V to 40V. It also has a flat, low tem-
verter. A simplified block diagram of the LM131 is shown in perature coefficient, and typically changes less than (/2%
Figure 2 and consists of a switched current source, input over a 100§ C temperature change.
comparator, and 1-shot timer. The current pump circuit forces the voltage at pin 2 to be at
The operation of these blocks is best understood by going 1.9V, and causes a current i e 1.90V/RS to flow. For
through the operating cycle of the basic V-to-F converter, Rs e 14k, i e 135 mA. The precision current reflector pro-
Figure 2 , which consists of the simplified block diagram of vides a current equal to i to the current switch. The current
the LM131 and the various resistors and capacitors con- switch switches the current to pin 1 or to ground depending
nected to it. on the state of the RS flip-flop.
The voltage comparator compares a positive input voltage, The timing function consists of an RS flip-flop, and a timer
V1, at pin 7 to the voltage, Vx, at pin 6. If V1 is greater, the comparator connected to the external RtCt network. When
comparator will trigger the 1-shot timer. The output of the the input comparator detects a voltage at pin 7 higher than
timer will turn ON both the frequency output transistor and pin 6, it sets the RS flip-flop which turns ON the current
the switched current source for a period t e 1.1 RtCt. During switch and the output driver transistor. When the voltage at
this period, the current i will flow out of the switched current pin 5 rises to )/3 VCC, the timer comparator causes the RS
source and provide a fixed amount of charge, Q e i c t, into flip-flop to reset. The reset transistor is then turned ON and
the capacitor, CL. This will normally charge Vx up to a higher the current switch is turned OFF.
level than V1. At the end of the timing period, the current i However, if the input comparator still detects pin 7 higher
will turn OFF, and the timer will reset itself. than pin 6 when pin 5 crosses )/3 VCC, the flip-flop will not
Now there is no current flowing from pin 1, and the capaci- be reset, and the current at pin 1 will continue to flow, in its
tor CL will be gradually discharged by RL until Vx falls to the attempt to make the voltage at pin 6 higher than pin 7. This
level of V1. Then the comparator will trigger the timer and condition will usually apply under start-up conditions or in
start another cycle. the case of an overload voltage at signal input. It should be
The current flowing into CL is exactly IAVE e i c (1.1 c RtCt) noted that during this sort of overload, the output frequency
c f, and the current flowing out of CL is exactly Vx/RL j will be 0; as soon as the signal is restored to the working
VIN/RL. If VIN is doubled, the frequency will double to main- range, the output frequency will be resumed.
tain this balance. Even a simple V-to-F converter can pro- The output driver transistor acts to saturate pin 3 with an
vide a frequency precisely proportional to its input voltage ON resistance of about 50X. In case of overvoltage, the
over a wide range of frequencies. output current is actively limited to less than 50 mA.
The voltage at pin 2 is regulated at 1.90 VDC for all values of
i between 10 mA to 500 mA. It can be used as a voltage
reference for other components, but care must be taken to
ensure that current is not taken from it which could reduce
the accuracy of the converter.
PRINCIPLES OF OPERATION OF BASIC VOLTAGE-
TO-FREQUENCY CONVERTER (FIGURE 1 )
The simple stand-alone V-to-F converter shown in Figure 1
includes all the basic circuitry of Figure 2 plus a few compo-
nents for improved performance.
A resistor, RIN e 100 kX g 10%, has been added in the path
to pin 7, so that the bias current at pin 7 ( b80 nA typical)
will cancel the effect of the bias current at pin 6 and help
provide minimum frequency offset.
The resistance RS at pin 2 is made up of a 12 kX fixed
resistor plus a 5 kX (cermet, preferably) gain adjust rheo-
TL/H/5680–4 stat. The function of this adjustment is to trim out the gain
FIGURE 2. Simplified Block Diagram of Stand-Alone tolerance of the LM131, and the tolerance of Rt, RL and Ct.
Voltage-to-Frequency Converter Showing LM131 and
External Components
6
Typical Applications (Continued)
For best results, all the components should be stable low- The average current fed into the op amp’s summing point
temperature-coefficient components, such as metal-film re- (pin 2) is i c (1.1 RtCt) c f which is perfectly balanced with
sistors. The capacitor should have low dielectric absorption; b VIN/RIN. In this circuit, the voltage offset of the LM131
depending on the temperature characteristics desired, NPO input comparator does not affect the offset or accuracy of
ceramic, polystyrene, Teflon or polypropylene are best the V-to-F converter as it does in the stand-alone V-to-F
suited. converter; nor does the LM131 bias current or offset cur-
A capacitor CIN is added from pin 7 to ground to act as a rent. Instead, the offset voltage and offset current of the
filter for VIN. A value of 0.01 mF to 0.1 mF will be adequate in operational amplifier are the only limits on how small the
most cases; however, in cases where better filtering is re- signal can be accurately converted. Since op amps with
quired, a 1 mF capacitor can be used. When the RC time voltage offset well below 1 mV and offset currents well be-
constants are matched at pin 6 and pin 7, a voltage step at low 2 nA are available at low cost, this circuit is recommend-
VIN will cause a step change in fOUT. If CIN is much less ed for best accuracy for small signals. This circuit also re-
than CL, a step at VIN may cause fOUT to stop momentarily. sponds immediately to any change of input signal (which a
stand-alone circuit does not) so that the output frequency
A 47X resistor, in series with the 1 mF CL, is added to give
will be an accurate representation of VIN, as quickly as 2
hysteresis effect which helps the input comparator provide
output pulses’ spacing can be measured.
the excellent linearity (0.03% typical).
In the precision mode, excellent linearity is obtained be-
DETAIL OF OPERATION OF PRECISION V-TO-F cause the current source (pin 1) is always at ground poten-
CONVERTER (FIGURE 3 ) tial and that voltage does not vary with VIN or fOUT. (In the
In this circuit, integration is performed by using a conven- stand-alone V-to-F converter, a major cause of non-linearity
tional operational amplifier and feedback capacitor, CF. is the output impedance at pin 1 which causes i to change
When the integrator’s output crosses the nominal threshold as a function of VIN).
level at pin 6 of the LM131, the timing cycle is initiated. The circuit of Figure 4 operates in the same way as Figure 3 ,
but with the necessary changes for high speed operation.
b VIN RS 1
fOUT e # #
2.09 V RIN RtCt
TL/H/5680 – 5
*Use stable components with low temperature coefficients. See Typical Applications section.
**This resistor can be 5 kX or 10 kX for VS e 8V to 22V, but must be 10 kX for VS e 4.5V to 8V.
***Use low offset voltage and low offset current op amps for A1: recommended types LM108, LM308A, LF411A
FIGURE 3. Standard Test Circuit and Applications Circuit, Precision Voltage-to-Frequency Converter
7
Typical Applications (Continued)
DETAILS OF OPERATION, FREQUENCY-TO- 0.1 second time constant, and settling of 0.7 second to
VOLTAGE CONVERTERS (FIGURES 5 AND 6 ) 0.1% accuracy.
In these applications, a pulse input at fIN is differentiated by In the precision circuit, an operational amplifier provides a
a C-R network and the negative-going edge at pin 6 causes buffered output and also acts as a 2-pole filter. The ripple
the input comparator to trigger the timer circuit. Just as with will be less than 5 mV peak for all frequencies above 1 kHz,
a V-to-F converter, the average current flowing out of pin 1 and the response time will be much quicker than in Figure 5 .
is IAVERAGE e i c (1.1 RtCt) c f. However, for input frequencies below 200 Hz, this circuit will
In the simple circuit of FIGURE 5 , this current is filtered in have worse ripple than Figure 5 . The engineering of the filter
the network RL e 100 kX and 1 mF. The ripple will be less time-constants to get adequate response and small enough
than 10 mV peak, but the response will be slow, with a ripple simply requires a study of the compromises to be
made. Inherently, V-to-F converter response can be fast,
but F-to-V response can not.
TL/H/5680 – 6
FIGURE 4. Precision Voltage-to-Frequency Converter,
100 kHz Full-Scale, g 0.03% Non-Linearity
TL/H/5680–7
RL RF
VOUT e fIN c 2.09V c c (RtCt) VOUT e b fIN c 2.09V c c (RtCt)
RS RS TL/H/5680 – 8
8
Typical Applications (Continued)
Light Intensity to Frequency Converter
TL/H/5680 – 9
*L14F-1, L14G-1 or L14H-1, photo transistor (General Electric Co.) or similar
TL/H/5680 – 10
TL/H/5680 – 11
TL/H/5680 – 12
9
Typical Applications (Continued)
Analog-to-Digital Converter with Microprocessor
TL/H/5680 – 13
Remote Voltage-to-Frequency Converter with 2-Wire Transmitter and Receiver
TL/H/5680 – 14
Voltage-to-Frequency Converter with Square-Wave Output Using d 2 Flip-Flop
TL/H/5680 – 15
Voltage-to-Frequency Converter with Isolators
TL/H/5680 – 16
10
Typical Applications (Continued)
TL/H/5680 – 17
TL/H/5680 – 18
TL/H/5680 – 19
11
Connection Diagrams
TL/H/5680–20
Note: Metal case is connected to pin 4 (GND.)
TL/H/5680 – 21
Order Number LM131H/883 or LM131AH/883 Order Number LM231AN, LM231N, LM331AN,
See NS Package Number H08C or LM331N
See NS Package Number N08E
Small-Outline Package
TL/H/5680 – 24
Top View
Order Number LM231WM
See NS Package Number M14B
12
Schematic Diagram
TL/H/5680 – 22
13
14
Physical Dimensions inches (millimeters)
15
LM131A/LM131, LM231A/LM231, LM331A/LM331 Precision Voltage-to-Frequency Converters
Physical Dimensions inches (millimeters) (Continued)
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Listing Program
.cseg
.org 0x000
rjmp RESET
.org 0x001
rjmp INT_FWD
.org 0x002
rjmp INT_RWD
.org 0x005
rjmp TIM1_OVF
;
RESET:
ldi temp,RAMEND
out SPL,temp
ldi temp,0xFF
out DDRB,temp
ldi temp,0b11110011
out DDRD,temp
rcall initlcd
ldi temp,0x30
mov ratusan,temp
mov puluhan,temp
mov satuan,temp
mov ratusan1,temp
mov puluhan1,temp
mov satuan1,temp
mov ratusan2,temp
mov puluhan2,temp
mov satuan2,temp
clr ForwardL
clr ForwardH
clr ReverstL
clr ReverstH
ldi temp,0b00000001
rcall write_inst
; Inisialisasi Interupsi Eksternal
ldi temp,0b00101011
out MCUCR,temp
ldi temp,0b11000000
out GIMSK,temp
; Inisialisasi Timer 1 sebagai Pewaktu 1 detik
ldi temp,0b10000000 ; Interupsi Timer1 Overflow enable
out TIMSK,temp
ldi temp,high(0xC2F7) ; Waktu 1 detik
out TCNT1H,temp
ldi temp,low(0xC2F7)
out TCNT1L,temp
ldi temp,0b00000100 ; Prescaler 256
out TCCR1B,temp
rcall Tampilkan
sei
tunggu:
sleep
rjmp tunggu
;
TIM1_OVF:
ldi temp,high(0xC2F7)
out TCNT1H,temp
ldi temp,low(0xC2F7)
out TCNT1L,temp
ldi temp,0b10000000
out TIFR,temp
cli
mov dd16uH,ForwardH
mov dd16uL,ForwardL
rcall Hitung_SWR1
mov dd16uH,ReverstH
mov dd16uL,ReverstL
rcall Hitung_SWR2
rcall Hitung_SWR3
rcall Tampilkan
clr ForwardL
clr ForwardH
clr ReverstL
clr ReverstH
sei
reti
;
INT_FWD:
adiw ForwardL,1
reti
;
INT_RWD:
adiw ReverstL,1
reti
;
Hitung_SWR1:
ldi temp1,0x30
ldi titipH,high(16500)
ldi titipL,low(16500)
sub ForwardL,titipL
sbc ForwardH,titipH
mov dv16uL,ForwardL
mov dv16uH,ForwardH
ldi dv16uL,low(10000)
ldi dv16uH,high(10000)
rcall div16u
mov ratusan,dres16uL
add ratusan,temp1
mov dd16uL,drem16uL
mov dd16uH,drem16uH
ldi dv16uL,low(1000)
ldi dv16uH,high(1000)
rcall div16u
mov puluhan,dres16uL
add puluhan,temp1
mov dd16uL,drem16uL
mov dd16uH,drem16uH
ldi dv16uL,low(100)
ldi dv16uH,high(100)
rcall div16u
mov satuan,dres16uL
add satuan,temp1
ret
;
Hitung_SWR2:
ldi temp1,0x30
mov dv16uL,ReverstL
mov dv16uH,ReverstH
ldi dv16uL,low(10000)
ldi dv16uH,high(10000)
rcall div16u
mov ratusan1,dres16uL
add ratusan1,temp1
mov dd16uL,drem16uL
mov dd16uH,drem16uH
ldi dv16uL,low(1000)
ldi dv16uH,high(1000)
rcall div16u
mov puluhan1,dres16uL
add puluhan1,temp1
mov dd16uL,drem16uL
mov dd16uH,drem16uH
ldi dv16uL,low(100)
ldi dv16uH,high(100)
rcall div16u
mov satuan1,dres16uL
add satuan1,temp1
ret
;
Hitung_SWR3:
push ReverstL
push ReverstH
add ReverstL,ForwardL
adc ReverstH,ForwardH
mov titipL,ReverstL
mov titipH,ReverstH
pop ReverstH
pop ReverstL
sub ForwardL,ReverstL
sbc ForwardH,ReverstH
mov dd16uH,titipH
mov dd16uL,titipL
mov dv16uL,ForwardL
mov dv16uH,ForwardH
rcall div16u
mov titipL,drem16uL
mov titipH,drem16uH
ldi dv16uL,low(10)
ldi dv16uH,high(10)
rcall div16u
ldi temp1,0x30
mov ratusan2,dres16uL
add ratusan2,temp1
mov puluhan2,drem16uL
add puluhan2,temp1
mov dd16uL,titipL
mov dd16uH,titipH
ldi dv16uL,low(1000)
ldi dv16uH,high(1000)
rcall div16u
mov satuan2,dres16uL
add satuan2,temp1
ret
;
Tampilkan:
ldi temp,0b00000010
rcall write_inst
ldi temp,'P'
rcall write_data
ldi temp,'f'
rcall write_data
ldi temp,'='
rcall write_data
mov temp,ratusan
rcall write_data
mov temp,puluhan
rcall write_data
ldi temp,','
rcall write_data
mov temp,satuan
rcall write_data
ldi temp,' '
rcall write_data
ldi temp,'P'
rcall write_data
ldi temp,'r'
rcall write_data
ldi temp,'='
rcall write_data
mov temp,ratusan1
rcall write_data
mov temp,puluhan1
rcall write_data
ldi temp,','
rcall write_data
mov temp,satuan1
rcall write_data
ldi temp,0b11000000
rcall write_inst
ldi temp,'S'
rcall write_data
ldi temp,'W'
rcall write_data
ldi temp,'R'
rcall write_data
ldi temp,' '
rcall write_data
ldi temp,'='
rcall write_data
ldi temp,' '
rcall write_data
mov temp,ratusan2
rcall write_data
mov temp,puluhan2
rcall write_data
ldi temp,','
rcall write_data
mov temp,satuan2
rcall write_data
ret
;
.def drem16uL =r18
.def drem16uH =r19
.def dres16uL =r20
.def dres16uH =r21
.def dd16uL =r20
.def dd16uH =r21
.def dv16uL =r22
.def dv16uH =r23
.def dcnt16u =r24
;***** Code
div16u:
clr drem16uL ;clear remainder Low byte
sub drem16uH,drem16uH;clear remainder High byte and carry
ldi dcnt16u,17 ;init loop counter
d16u_1:
rol dd16uL ;shift left dividend
rol dd16uH
dec dcnt16u ;decrement counter
brne d16u_2 ;if done
ret ; return
d16u_2:
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_3 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_1 ;else
d16u_3:
sec ; set carry to be shifted into result
rjmp d16u_1
;
initlcd:
ldi timeout,256
rcall delay
ldi temp,0x30
rcall write_inst
ldi timeout,65
rcall delay
ldi temp,0x30
rcall write_inst
ldi timeout,2
rcall delay
ldi temp,0b00000001
rcall write_inst
ldi temp,0b00000010
rcall write_inst
ldi temp,0b00000110 ;set mode untuk menaikan alamat
rcall write_inst
ldi temp,0b00001100 ;mengaktifkan kursor
rcall write_inst
ldi temp,0b00111000 ;inisialisasi LCD untuk 8 bit
rcall write_inst ;operasi dan dua line
ret
;
tulis:
lpm
tst r0
brne terus
ret
terus:
mov temp,r0
rcall write_data
adiw zl,1
rjmp tulis
write_inst:
cbi portD,0
out portB,temp
sbi portD,1
cbi portD,1
rcall delay
ret
;
write_data:
sbi portD,0
out portB,temp
sbi portD,1
cbi portD,1
rcall delay
ret
;
delay:
ldi temp,64
mov delay1,temp
wait:
dec delay1
brne wait
dec timeout
brne delay
ret
;
Ldelay:
ldi temp,40
mov delay3,temp
waitmore2:
rcall tunda
dec delay3
brne waitmore2
ret
tunda:
ldi temp,0xff
mov delay2,temp
waitsome:
ldi temp,0xff
mov delay1,temp
waitmore:
dec delay1
brne waitmore
dec delay2
brne waitsome
ret