Field Effect Transistor - FET

Mengapa kita masih perlu transistor jenis

lain?
BJT mempunyai sedikit masalah.
BJT selalu memerlukan arus basis IB,
walaupun arus ini kecil, tetapi tidak bisa
diabaikan, terutama sekali saat BJT
digunakan sebagai saklar, pasti dibutuhkan
arus yang cukup besar untk membuat
transistor jenuh. 1
 Field Effect Transistor - FET
Apakah ada jenis transistor lain yang bisa
digerakkan dengan tegangan tanpa
membutuhkan arus ?
Jawabannya ada di FET.
Dengan perantaraan FET, kita dapat menghubungkan
peralatan komputer atau transduser yang tidak bisa
menghasilkan arus, dengan alat yang lebih besar.
FET bisa digunakan sbg bufer, sehingga tidak
membutuhkan arus dari komputer/trasduser.
Teknologi modern pembuatan IC, ternyata dimensi transistor
FET bisa dibuat sangat kecil, sehingga pembuatan IC saat ini
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berdasarkan transistor FET ini.
 FET vs BJT

FET BJT
Gate (G) Base (B)
Drain(D) Collector (C)
Emitter(E)
Source(S)
Base current
Gate Voltage
Collector current
Drain current
Collector-Emitter Voltage
Drain-source voltage

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 Jenis-jenis FET
• JFET (Junction FET)
• MOSFET (Metal Oxide Silikon FET)
• PMOS ( MOS saluran P)
• NMOS (MOS saluran N)
• Masih banyak lagi

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 ID

FET
FET VDS

Parameter FET : ID, VGS, VDS.

VGS
Dasar pemikiran FET: IS
Ada arus ID = IS yang mengalir melalui
saluran, yang besarnya saluran dikendalikan
oleh tegangan VGS.
Karena arus lewat saluran (yang berupa
hambatan) maka ada tegangan VDS.
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Junction FETs

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JFET saluran N
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Daerah deplesi membesar dengan bertambahnya tegangan balik
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Saluran N

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Arus Drain current vs tegangan drain-ke-source
(tegangan gate-source = 0) 14
n-Channel FET for vGS = 0.
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Typical drain characteristics of an n-channel JFET.
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If vDG exceeds the breakdown voltage VB,
drain current increases rapidly. 17
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 KURVA KARAKTERISTIK Junction FET

Hubungan
VGS dan ID

I D  k VGS  VP 
2

k : konstanta
VP : tegangan pinch-off atau threshold.
Arus dibatasi hanya saat tegangan VGS = 0
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Transkonduktansi

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 Junction FET – Sumber Arus
VDD

RLoad

RS

Kurva tak dipengaruhi tegangan VDS.

Arus hanya dipengaruhi VGS bukan VDS.
RS membuat VGS selalu negatip.
Misalnya RS = 4K,  VGS = -4 V.
Arus di Rload = 1 mA. 21
 KURVA VDS-ID Junction FET

Linear Ada dua daerah operasi

Saturation
:
saturation
linear.
I D  k VGS  VP 
2
Linear
 2

I D  2k VGS  VP VDS 
VDS
Saturation 
 2 

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 JFET - variable resistor
VDD

For low values of VDS the

slopes, change from
RD
a resistance
(~5v/2.7mA~1.9k) to
RG a resistance
VGS
(5v/10mA~0.5k).

A resistance is
controlled by an
input voltage. VDS, DRAIN-SOURCE
VOLTAGE, (Volts)

This makes it possible to have an element in a

circuit that can be electronically adjusted.
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 JFET - variable resistor (2)
VDD Now lets analyze the circuit. In the linear region
we had a relationship between ID and VDS.

 2

I D  2k VGS  VT VDS 
VDS
RD 
 2 
To find the effective resistance this is the voltage
RG across the channel divided by the current through
VGS
the channel.

 VDS 
 2k VGS  VT  
1 ID
 
RDS VDS  2 
If it wasn’t for the last term, we would have a value of 1/RDS that was
proportional to VGS, the control voltage and didn’t depend on VDS
(remember VT is a constant of the FET, the pinch off voltage). This is like
a resistor, and it forms a VOLTAGE DIVIDER with RD.
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 Latihan Soal
Diketahui N-channel JFET, IDSS = 8.7 mA, VP = –3 V,
VGS = –1 V. Hitunglah:
(i) ID (ii) gmo (iii) gm

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Diketahui JFET sebagai berikut: yos = 40 μS, IDSS = 8 mA,
dan VGS(off) = -4 Volt.
Tentukanlah:
(a) Titik kerja: VGSQ dan IDQ
(b) Penguatan tegangan (Av)

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n-Channel depletion MOSFET.
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 n-Channel enhancement MOSFET
showing channel length L and channel width W.
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 n-Channel depletion MOSFET
showing channel length L and channel width W.
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enhancement-mode n-channel MOSFET
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vGS < Vto  pn junction antara drain dan
body  reverse biased  iD=0. 31
 Terbentuk saluran N

vGS < Vto  pn junction antara drain dan

body  reverse biased  iD=0. 32
For vGS < Vto the pn junction between drain and body
is reverse biased and iD=0. 33
 vGS >Vto  terbentuk saluran n.
vGS bertambah  saluran membesar.
vDS kecil ,I D sebanding dengan vDS.
resistor tergantung nilai vGS. 34
vDS bertambah, saluran mengecil di drain dan
Laju pertambahan iD : melambat
Saat vDS> vGS -Vto,  iD tetap 35
Threshold Voltage
Vto (VP)
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Kurva karakteristik transistor NMOS
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Drain characteristics
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Rangkaian penguat sederhana menggunakan NMOS .
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Drain characteristics and load line
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vDS versus time.
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Graphical solution
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The more nearly horizontal bias line results in less change in the Q-point.

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Sinyal campuran
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Rangkaian Ekivalen FET
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Rangkaian ekivalen FET ( iD terpengaruh vDS)
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Penentuan gm dan rd
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Common-source amplifier.
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Rangkaian Ekivalen Common-Source amplifier.
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Common-source amplifier dengan nilai R
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vo(t) dan vin(t) versus time 53
Gain magnitude versus frequency
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Source follower.
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Rangkaian Ekivalen Source Follower.
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Common-gate amplifier.
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n-Channel depletion MOSFET.
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Drain current versus vGS in the saturation region
for n-channel devices.
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p-Channel FET circuit symbols.
Sama = n-channel devices,
kecuali arah panah 60
 MOSFET-switch
VDD

RLOAD IRF510

RG
Power MOSFET dapat dialiri arus
VGS besar sampai 75 A, dan daya 150 W.
Saat ON punya hambatan sekitar 10
Ohm.
Contoh : IRF510
Mempunyai arus maksimum 5,6 A
dab hambatan saat ON 0,4 Ohm. 61
 MOSFET-switch (2)
Note the
log scale!
Kurva ID vs. VGS.
Ideal saklar:
saat OFF  Arus =0.
ON
Dari kuva terlihat :
Tegangan VGS
< 3 volt,  ID = 0
>5V  arus besar.
OFF

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 PMOS
gate
In this device the gate controls hole
source P-MOS drain
flow from source to drain.
p p
It is made in n-type silicon. n-type Si

|VGS |>|Vt |
+ -
What if we apply a big negative
gate voltage on the gate?
drain
If |VGS |>|Vt | (both negative)
p p then we induce a + charge on
n-type Si the surface (holes)
source
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 NMOS and PMOS Compared
NMOS PMOS
“Body” – p-type “Body” – n-type
Source – n-type Source – p-type
Drain – n-type Drain – p-type
VGS – positive VGS – negative
VT – positive VT – negative
VDS – positive VDS – negative
ID – positive (into drain) ID – negative (into drain)
G G
S D S D
ID ID
n p n p
n
B B
ID ID
1 mA
VGS=3V VGS= 3V
1 mA
(for IDS =
(for IDS =
1mA) VGS=0 -1mA) VGS=0
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VDS VDS
1 2 3 4 1 2 3 4
 CIRCUIT SYMBOLS

D D

G G

S S

NMOS circuit symbol PMOS circuit symbol

A small circle is drawn at the gate

to remind us that the polarities are
reversed for PMOS.

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 PMOS Transistor Switch Model
Operation compared to NMOS: It is complementary.
VDD VDD S
S S VG =0
G G G
VDD VG = VDD
V=0
D D
Switch OPEN Switch CLOSED D

For PMOS for the normal circuit connection is to connect

S to VDD (The function of the device is a “pull up”)

Switch is closed: Drain (D) is connected to Source (S) when VG =0

Switch is open : Drain (D) is disconnected from Source (S) when VG = VDD

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