2 Bit Comparator

Subarnoto (15/386039/SV/09425)
Jurusan Elektronika dan Instrumentasi SV UGM
Sekip Unit 1, Caturtunggal, D.I. Yogyakarta 55281 INDONESIA
subarnoto@ugm.ac.id

I. SPESIFIKASI
a. Input 2 bit binary pertama (A0, A1) dan Input 2 bit binary kedua (B0,B1) akan
menggunakan Push Button pada FPGA input.
b. Output ada tiga yaitu E = Equal (A=B), G = Greater than(A>B), L = Less than(A<B)
akan menggunakan led pada FPGA sebagai indikator output.
II. INPUT DAN OUTPUT

III. METODE PERANCANGAN

- Membuat tabel kebenaran dari hubungan Input dan Output 2 Bit Comparator. Berikut ini
tabel kebenaran 2 bit comparator(Gambar 3.1) :

Gambar 3.1 Tabel Kebenaran 2 Bit Comparator

- Dari tabel kebenaran seperti diatas lalu dibuatkan k–map. Berikut ini K-map yang
didapatkan dari tabel kebenaran(Gambar 3.2a, Gambar 3.2b, Gambar 3.2c) :
OUTPUT G

Gambar 3.2a

OUTPUT E

Gambar 3.2b

OUTPUT L

Gambar 3.3c

- Dari K-map yang telah dilakukan, didapatkan persamaan seperti berikut:

G = A0 B1’ BO’ + A1 B1’ + A1 A0 B0’

E = A’ A0’ B1’ B0’ + A1’ A0 B1’ B0 + A1 A0’ B1 B0’ + A1 A0 B1 B0
L = A1’ A0’ B0 + A1’ B1 + A0’ B1 B0

- Dari persamaan yang didapatkan dibuatkan rangkaian pada Quartus. Berikut ini
Rangkaian 2 Bit Comparator di Quartus
 Gambar 3.4 Rangakaian 2 Bit Comparator

- Dari rangkaian diatas, selanjutnya bisa digunakan untuk simulasi di modelsim-altera dan
implementasi di FPGA

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY \2BitComparator\ IS
PORT
(
a1 : IN STD_LOGIC;
a0 : IN STD_LOGIC;
 b1 : IN STD_LOGIC;
b0 : IN STD_LOGIC;
G : OUT STD_LOGIC;
E : OUT STD_LOGIC;
L : OUT STD_LOGIC
);
END \2BitComparator\;

ARCHITECTURE bdf_type OF \2BitComparator\ IS

SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC;

SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_35 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC;

BEGIN

SYNTHESIZED_WIRE_34 <= NOT(a1);

SYNTHESIZED_WIRE_33 <= NOT(a0);

SYNTHESIZED_WIRE_12 <= NOT(SYNTHESIZED_WIRE_33 OR SYNTHESIZED_WIRE_34 OR

SYNTHESIZED_WIRE_35 OR SYNTHESIZED_WIRE_36);

SYNTHESIZED_WIRE_15 <= a1 AND SYNTHESIZED_WIRE_33 AND b1 AND SYNTHESIZED_WIRE_36;

SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_34 AND a0 AND SYNTHESIZED_WIRE_35 AND b0;

SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_34 AND SYNTHESIZED_WIRE_33 AND
SYNTHESIZED_WIRE_35 AND SYNTHESIZED_WIRE_36;

SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13 OR

SYNTHESIZED_WIRE_14 OR SYNTHESIZED_WIRE_15;

E <= NOT(SYNTHESIZED_WIRE_16);

L <= NOT(SYNTHESIZED_WIRE_17);

SYNTHESIZED_WIRE_23 <= a1 AND a0 AND SYNTHESIZED_WIRE_36;

SYNTHESIZED_WIRE_35 <= NOT(b1);

SYNTHESIZED_WIRE_22 <= a0 AND SYNTHESIZED_WIRE_35 AND SYNTHESIZED_WIRE_36;

SYNTHESIZED_WIRE_17 <= SYNTHESIZED_WIRE_21 OR SYNTHESIZED_WIRE_22 OR

SYNTHESIZED_WIRE_23;

SYNTHESIZED_WIRE_21 <= a1 AND SYNTHESIZED_WIRE_35;

SYNTHESIZED_WIRE_36 <= NOT(b0);

SYNTHESIZED_WIRE_31 <= SYNTHESIZED_WIRE_33 AND b1 AND b0;

SYNTHESIZED_WIRE_29 <= SYNTHESIZED_WIRE_34 AND b1;

SYNTHESIZED_WIRE_30 <= SYNTHESIZED_WIRE_34 AND SYNTHESIZED_WIRE_33 AND b0;

SYNTHESIZED_WIRE_32 <= SYNTHESIZED_WIRE_29 OR SYNTHESIZED_WIRE_30 OR

SYNTHESIZED_WIRE_31;

G <= NOT(SYNTHESIZED_WIRE_32);
END bdf_type;